Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19746

1

T2

168

T3

3

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3588

1

T1

11

T7

30

T9

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17652

1

T2

168

T3

2

T4

16

auto[1]

5682

1

T1

11

T3

1

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T133	13		T148	15		T149	1
values[0]	94	1			T301	19		T164	13		T329	21
values[1]	630	1			T30	20		T40	2		T49	1
values[2]	658	1			T3	1		T7	21		T113	1
values[3]	729	1			T11	1		T49	11		T141	1
values[4]	671	1			T114	12		T101	1		T141	1
values[5]	2876	1			T6	26		T12	14		T13	50
values[6]	644	1			T7	9		T99	11		T140	1
values[7]	758	1			T114	13		T29	21		T30	12
values[8]	481	1			T3	1		T16	3		T29	33
values[9]	986	1			T1	11		T3	1		T9	4
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T113	1		T30	20		T40	2
values[1]	502	1			T3	1		T7	21		T56	2
values[2]	889	1			T11	1		T114	12		T49	11
values[3]	2937	1			T6	26		T12	14		T13	50
values[4]	585	1			T17	2		T140	1		T56	4
values[5]	675	1			T7	9		T30	12		T99	11
values[6]	765	1			T114	13		T29	54		T208	13
values[7]	421	1			T3	1		T16	3		T30	23
values[8]	847	1			T3	1		T9	4		T28	1
values[9]	174	1			T1	11		T133	13		T326	1
minimum	14791	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T113	1		T40	2		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T30	8		T227	12		T134	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T56	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	2		T156	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T114	1		T49	5		T235	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	1		T44	6		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T6	2		T12	14		T13	50
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T101	1		T141	1		T130	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	1		T140	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T109	1		T132	10		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T30	8		T208	1		T237	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	1		T99	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T114	1		T29	35		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T208	1		T57	11		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T3	1		T104	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	3		T30	12		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T28	1		T223	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	4		T101	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T326	1		T316	1		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T1	3		T133	1		T94	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14554	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T241	11		T212	1		T301	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T132	5		T223	3		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	12		T227	13		T134	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T56	1		T103	12		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	19		T156	9		T142	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T114	11		T49	6		T235	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T133	16		T136	10		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T6	24		T14	23		T39	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T130	1		T149	10		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	1		T56	3		T109	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T109	1		T132	9		T148	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	4		T208	7		T235	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	8		T99	10		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T114	12		T29	19		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T208	12		T57	11		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T213	5		T226	2		T294	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	11		T223	1		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T223	12		T151	28		T153	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T56	1		T148	7		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T325	8		T256	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T1	8		T133	12		T94	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T301	7		T347	9		T318	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T151	15		T94	1		T316	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T133	1		T148	8		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T164	13		T329	9		T348	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T301	12		T335	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	2		T49	1		T132	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	8		T227	12		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T113	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	2		T156	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T49	5		T141	1		T207	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T44	6		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T114	1		T134	6		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T101	1		T141	1		T130	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T6	2		T12	14		T13	50
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T109	1		T132	10		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T208	1		T237	18		T160	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T99	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T114	1		T29	14		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T209	14		T208	1		T57	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	1		T29	21		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	3		T30	12		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T28	1		T223	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T1	3		T9	4		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T151	16		T94	2		T325	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T133	12		T148	7		T160	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T329	12		T348	20		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T301	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T132	5		T223	3		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	12		T227	13		T134	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	1		T103	12		T207	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	19		T156	9		T142	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	6		T207	2		T235	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T133	16		T210	10		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T114	11		T134	10		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	1		T136	10		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T6	24		T14	23		T39	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T109	1		T132	9		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T208	7		T160	5		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	8		T99	10		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T114	12		T29	7		T30	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T208	12		T57	11		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T29	12		T222	7		T213	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	11		T223	1		T236	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T223	12		T151	12		T153	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T1	8		T56	1		T135	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T113	1		T40	2		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T30	13		T227	14		T134	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T56	2		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	21		T156	10		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T114	12		T49	7		T235	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	1		T44	6		T133	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T6	26		T12	1		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	1		T141	1		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	2		T140	1		T56	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T109	2		T132	10		T148	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	5		T208	8		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	9		T99	11		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T114	13		T29	21		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T208	13		T57	12		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	1		T104	1		T213	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T16	3		T30	12		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T28	1		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	3		T101	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T326	1		T316	1		T325	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T1	9		T133	13		T94	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14656	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T241	1		T212	1		T301	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T132	17		T223	3		T138	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T30	7		T227	11		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T207	8		T150	12		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T142	11		T212	11		T253	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	4		T235	14		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T136	8		T169	12		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T12	13		T13	47		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	2		T149	8		T269	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T109	1		T224	11		T234	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	9		T148	11		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T30	7		T237	17		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T209	13		T150	11		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	33		T214	8		T139	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T57	10		T132	10		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T255	5		T226	6		T294	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T30	11		T215	8		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T223	17		T151	25		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T148	7		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T310	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T1	2		T94	13		T263	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T20	1		T164	12		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T241	10		T301	11		T347	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T151	17		T94	3		T316	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T133	13		T148	8		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T164	1		T329	13		T348	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	8		T335	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T40	2		T49	1		T132	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	13		T227	14		T134	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T113	1		T56	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	21		T156	10		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	7		T141	1		T207	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T44	6		T133	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T114	12		T134	11		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T101	1		T141	1		T130	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T6	26		T12	1		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T109	2		T132	10		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T208	8		T237	1		T160	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	9		T99	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T114	13		T29	8		T30	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T209	1		T208	13		T57	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	1		T29	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	3		T30	12		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	1		T28	1		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T1	9		T9	3		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T151	14		T310	11		T264	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T148	7		T214	5		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T164	12		T329	8		T348	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	17		T223	3		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	7		T227	11		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T207	5		T150	12		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T142	11		T37	11		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	4		T207	3		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T169	12		T210	17		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T134	5		T150	9		T225	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T130	2		T136	8		T269	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T12	13		T13	47		T34	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T132	9		T148	11		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T237	17		T160	7		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	11		T161	13		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	13		T30	7		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T209	13		T57	10		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T29	20		T214	8		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	11		T215	8		T236	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T223	17		T151	11		T225	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	2		T9	1		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13