Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17486

1

T1

11

T2

168

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

5848

1

T3

1

T6

26

T7

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17375

1

T1

11

T2

168

T3

1

auto[1]

5959

1

T3

2

T6

26

T7

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	147	1			T42	1		T233	14		T187	1
values[0]	61	1			T137	1		T233	25		T257	1
values[1]	755	1			T7	8		T9	4		T30	20
values[2]	767	1			T1	11		T3	1		T56	2
values[3]	744	1			T7	22		T113	1		T140	1
values[4]	719	1			T30	23		T44	6		T135	27
values[5]	476	1			T99	11		T57	22		T109	3
values[6]	678	1			T114	13		T29	21		T40	2
values[7]	581	1			T28	1		T30	12		T49	1
values[8]	596	1			T3	1		T11	1		T32	2
values[9]	3206	1			T3	1		T6	26		T12	14
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	729	1			T3	1		T9	4		T101	1
values[1]	3068	1			T1	11		T6	26		T12	14
values[2]	774	1			T7	22		T113	1		T140	1
values[3]	681	1			T30	23		T44	6		T207	12
values[4]	524	1			T40	2		T99	11		T17	2
values[5]	654	1			T114	13		T29	21		T101	1
values[6]	454	1			T11	1		T28	1		T30	12
values[7]	674	1			T3	1		T32	2		T140	2
values[8]	722	1			T3	1		T114	12		T29	33
values[9]	140	1			T16	3		T42	1		T103	13
minimum	14914	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	4		T101	1		T143	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T3	1		T132	29		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	3		T156	1		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1739	1			T6	2		T12	14		T13	50
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T161	7		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T113	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T150	10		T237	18		T214	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	12		T44	6		T207	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T99	1		T57	11		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	2		T17	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T114	1		T29	14		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T208	1		T132	10		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	1		T28	1		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T227	12		T131	1		T160	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T32	2		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	1		T136	9		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T49	5		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T114	1		T29	21		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T152	8		T94	8		T263	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T16	3		T42	1		T103	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14600	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T7	1		T137	2		T222	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T233	7		T293	10		T254	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	5		T139	10		T349	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	8		T156	9		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	990	1			T6	24		T14	23		T39	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	12		T161	5		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	8		T134	10		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T150	7		T213	5		T225	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	11		T207	6		T150	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T99	10		T57	11		T109	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	1		T133	10		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T114	12		T29	7		T273	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T208	7		T132	9		T133	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	4		T56	1		T109	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T227	13		T250	8		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	12		T223	3		T235	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	10		T136	10		T235	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	6		T56	3		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T114	11		T29	12		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T94	10		T263	13		T258	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T103	12		T350	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	2		T8	2		T30	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T7	7		T222	6		T234	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T233	7		T187	1		T263	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T42	1		T253	5		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T137	1		T257	1		T264	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	4		T30	8		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T132	18		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	3		T156	1		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T56	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T161	7		T152	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	1		T113	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T150	10		T237	18		T214	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	12		T44	6		T135	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T99	1		T57	11		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T133	1		T149	9		T150	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T114	1		T29	14		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	2		T17	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	1		T30	8		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T208	1		T227	12		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T11	1		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	1		T215	9		T235	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T49	5		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1796	1			T6	2		T12	14		T13	50
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T233	7		T263	13		T288	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T302	8		T350	7		T256	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T233	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T264	13		T307	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T30	12		T150	7		T151	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	7		T132	5		T222	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	8		T156	9		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T56	1		T142	18		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	12		T161	5		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	8		T134	10		T223	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T150	7		T213	5		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T30	11		T135	12		T207	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T99	10		T57	11		T109	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T133	10		T149	10		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T114	12		T29	7		T210	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	1		T132	9		T148	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T30	4		T56	1		T109	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T208	7		T227	13		T133	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T148	2		T235	7		T160	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T134	10		T235	11		T292	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	6		T56	3		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1083	1			T6	24		T14	23		T39	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	3		T101	1		T143	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T132	7		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	9		T156	10		T134	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T6	26		T12	1		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	13		T161	6		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	9		T113	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T150	8		T237	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	12		T44	6		T207	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T99	11		T57	12		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	2		T17	2		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T114	13		T29	8		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T208	8		T132	10		T133	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T28	1		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T227	14		T131	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T32	2		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	11		T136	11		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T49	7		T56	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T114	12		T29	13		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T152	1		T94	11		T263	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T16	3		T42	1		T103	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14717	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T7	8		T137	2		T222	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	1		T233	2		T293	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T132	27		T138	11		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	2		T134	8		T223	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1404	1			T12	13		T13	47		T34	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T161	6		T225	14		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	5		T135	14		T139	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T150	9		T237	17		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	11		T207	5		T150	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T57	10		T109	1		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	8		T214	5		T139	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T29	13		T241	10		T232	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T132	9		T148	7		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T30	7		T148	11		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T227	11		T160	7		T145	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T223	3		T241	15		T235	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	8		T215	8		T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	4		T233	6		T351	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	20		T209	13		T130	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T152	7		T94	7		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T350	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T30	7		T150	12		T151	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T222	10		T234	7		T188	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T233	8		T187	1		T263	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T42	1		T253	1		T302	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T137	1		T257	1		T264	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	3		T30	13		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	8		T132	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	9		T156	10		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	1		T56	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	13		T161	6		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	9		T113	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T150	8		T237	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T30	12		T44	6		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T99	11		T57	12		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	11		T149	11		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T114	13		T29	8		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	2		T17	2		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	1		T30	5		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T208	8		T227	14		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T11	1		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	11		T215	1		T235	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T49	7		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1443	1			T6	26		T12	1		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T233	6		T263	12		T288	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T253	4		T350	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T233	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T264	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T30	7		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T132	17		T222	10		T238	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	2		T134	8		T223	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T132	10		T214	8		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T161	6		T152	17		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	5		T139	4		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T150	9		T237	17		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T30	11		T135	14		T207	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T57	10		T109	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T149	8		T150	11		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	13		T241	10		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T132	9		T148	7		T214	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T30	7		T135	10		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T227	11		T136	8		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T148	11		T241	15		T235	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T215	8		T235	14		T269	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	4		T223	3		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1436	1			T12	13		T13	47		T29	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13