Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T113	1		T104	1		T207	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	6		T223	4		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T30	13		T212	1		T225	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	3		T101	1		T56	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T114	13		T132	17		T133	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T101	1		T140	1		T208	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T3	1		T6	26		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	8		T99	11		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	1		T17	2		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	1		T207	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	2		T57	12		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	13		T32	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	9		T3	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	8		T156	10		T148	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T56	6		T141	1		T227	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T103	13		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	9		T114	12		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	3		T29	13		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T30	12		T243	1		T244	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T146	12		T245	1		T246	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T247	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T207	5		T161	13		T151	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T223	3		T18	1		T235	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	7		T225	4		T232	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T149	8		T214	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T132	36		T214	2		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T134	5		T241	10		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T12	13		T13	47		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T148	7		T150	11		T214	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T209	13		T160	9		T239	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T207	3		T241	15		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T57	10		T109	1		T223	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	2		T150	9		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T1	2		T37	11		T212	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	13		T148	11		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T227	11		T138	11		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T134	8		T135	10		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T30	7		T139	4		T226	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T29	20		T49	4		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T30	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T246	4		T248	2		T172	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T247	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T162	10		T94	3		T170	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T249	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T113	1		T104	1		T223	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	6		T223	4		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	13		T132	10		T207	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	3		T56	2		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T132	7		T133	17		T224	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	1		T140	1		T208	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T3	1		T6	26		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	8		T101	1		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	1		T17	2		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T99	11		T241	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T57	12		T109	2		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	13		T11	1		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T40	2		T149	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	8		T156	10		T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	9		T3	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	1		T103	13		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	9		T114	12		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T16	3		T29	13		T49	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T162	2		T170	13		T254	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T161	13		T151	14		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T223	3		T18	1		T164	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	7		T132	9		T207	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T149	8		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T132	27		T152	7		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T241	10		T139	8		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T12	13		T13	47		T34	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	5		T148	7		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T209	13		T150	12		T222	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T241	15		T215	8		T210	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T57	10		T109	1		T223	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T130	2		T142	11		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T237	17		T37	11		T255	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	13		T148	11		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	2		T138	11		T233	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T134	8		T224	11		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	18		T227	11		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T29	20		T49	4		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13