Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23334 1 T1 11 T2 168 T3 3


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 17449 1 T1 11 T2 168 T3 2
auto[ADC_CTRL_FILTER_COND_OUT] 5885 1 T3 1 T6 26 T7 17


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17313 1 T1 11 T2 168 T3 1
auto[1] 6021 1 T3 2 T6 26 T7 30


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19552 1 T1 3 T2 168 T3 3
auto[1] 3782 1 T1 8 T5 2 T6 24


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 7 1 T42 1 T256 6 - -
values[0] 69 1 T233 25 T188 4 T257 1
values[1] 783 1 T1 11 T7 8 T9 4
values[2] 762 1 T3 1 T101 1 T140 1
values[3] 677 1 T7 22 T113 1 T134 16
values[4] 710 1 T30 23 T44 6 T135 27
values[5] 499 1 T99 11 T109 3 T133 11
values[6] 709 1 T114 13 T29 21 T40 2
values[7] 604 1 T30 12 T49 1 T56 2
values[8] 561 1 T3 1 T11 1 T114 12
values[9] 3349 1 T3 1 T6 26 T12 14
minimum 14604 1 T2 168 T4 16 T5 22


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 1003 1 T3 1 T7 8 T9 4
values[1] 3178 1 T1 11 T6 26 T12 14
values[2] 703 1 T7 22 T113 1 T140 1
values[3] 637 1 T30 23 T44 6 T207 12
values[4] 565 1 T40 2 T99 11 T57 22
values[5] 674 1 T114 13 T29 21 T17 2
values[6] 432 1 T11 1 T28 1 T30 12
values[7] 684 1 T3 2 T32 2 T140 1
values[8] 752 1 T114 12 T29 33 T49 11
values[9] 102 1 T16 3 T42 1 T130 6
minimum 14604 1 T2 168 T4 16 T5 22


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19240 1 T1 9 T2 168 T3 3
auto[1] 4094 1 T1 2 T9 1 T12 13


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 264 1 T9 4 T30 8 T101 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 296 1 T3 1 T7 1 T132 18
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T1 3 T156 1 T157 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1845 1 T6 2 T12 14 T13 50
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T7 1 T223 18 T161 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T7 1 T113 1 T140 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T237 18 T214 3 T210 5
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T30 12 T44 6 T207 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T99 1 T57 11 T109 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T40 2 T104 1 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 137 1 T114 1 T29 14 T101 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T17 1 T208 1 T132 10
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T11 1 T28 1 T30 8
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 106 1 T227 12 T131 1 T160 8
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T3 2 T32 2 T140 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T134 1 T136 9 T215 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T49 5 T56 1 T152 8
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 251 1 T114 1 T29 21 T141 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 31 1 T258 1 T259 3 T260 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 27 1 T16 3 T42 1 T130 5
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14503 1 T2 168 T4 16 T5 20
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 236 1 T30 12 T134 10 T150 7
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T7 7 T132 5 T139 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T1 8 T156 9 T224 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1042 1 T6 24 T14 23 T39 25
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T7 12 T223 12 T161 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T7 8 T135 12 T223 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T210 7 T213 5 T261 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T30 11 T207 6 T150 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 87 1 T99 10 T57 11 T109 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T133 10 T149 10 T224 16
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T114 12 T29 7 T109 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T17 1 T208 7 T132 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T30 4 T56 1 T148 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 92 1 T227 13 T250 8 T144 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T133 12 T223 3 T235 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T134 10 T136 10 T235 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 115 1 T49 6 T56 3 T233 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T114 11 T29 12 T208 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 30 1 T258 6 T259 2 T262 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T130 1 T263 13 - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 101 1 T5 2 T8 2 T32 2


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T42 1 T256 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 13 1 T233 13 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 25 1 T188 3 T257 1 T264 18
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 218 1 T1 3 T9 4 T30 8
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T7 1 T132 18 T137 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T101 1 T156 1 T134 9
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 279 1 T3 1 T140 1 T56 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T7 1 T212 1 T225 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T7 1 T113 1 T134 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T150 10 T237 18 T214 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T30 12 T44 6 T135 15
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T99 1 T109 2 T210 5
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T133 1 T149 9 T150 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T114 1 T29 14 T101 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 233 1 T40 2 T17 1 T104 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 110 1 T30 8 T49 1 T56 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T208 1 T227 12 T131 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T3 1 T11 1 T28 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T114 1 T134 1 T215 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T3 1 T49 5 T140 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1843 1 T6 2 T12 14 T13 50
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14503 1 T2 168 T4 16 T5 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T256 5 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T233 12 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T188 1 T264 13 T265 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T1 8 T30 12 T150 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T7 7 T132 5 T222 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T156 9 T134 10 T223 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T56 1 T142 18 T139 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 105 1 T7 12 T225 10 T266 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T7 8 T134 10 T223 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T150 7 T213 5 T225 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T30 11 T135 12 T207 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 54 1 T99 10 T109 1 T210 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T133 10 T149 10 T150 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T114 12 T29 7 T57 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T17 1 T132 9 T148 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T30 4 T56 1 T109 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T208 7 T227 13 T133 16
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T148 2 T235 7 T160 5
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 102 1 T114 11 T134 10 T235 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T49 6 T56 3 T133 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1110 1 T6 24 T14 23 T39 25
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 101 1 T5 2 T8 2 T32 2


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 290 1 T9 3 T30 13 T101 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 259 1 T3 1 T7 8 T132 6
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T1 9 T156 10 T157 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1386 1 T6 26 T12 1 T13 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T7 13 T223 13 T161 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T7 9 T113 1 T140 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 139 1 T237 1 T214 1 T210 8
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T30 12 T44 6 T207 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T99 11 T57 12 T109 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T40 2 T104 1 T133 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T114 13 T29 8 T101 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T17 2 T208 8 T132 10
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T11 1 T28 1 T30 5
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 110 1 T227 14 T131 1 T160 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T3 2 T32 2 T140 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T134 11 T136 11 T215 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T49 7 T56 4 T152 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 274 1 T114 12 T29 13 T141 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 37 1 T258 7 T259 3 T260 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 23 1 T16 3 T42 1 T130 4
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14604 1 T2 168 T4 16 T5 22
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T9 1 T30 7 T134 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 244 1 T132 17 T138 11 T139 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T1 2 T233 2 T164 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1501 1 T12 13 T13 47 T34 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T223 17 T161 6 T225 26
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T135 14 T139 4 T222 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T237 17 T214 2 T210 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T30 11 T207 5 T150 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T57 10 T109 1 T150 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T149 8 T214 5 T18 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 104 1 T29 13 T135 10 T241 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T132 9 T148 7 T169 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 92 1 T30 7 T148 11 T207 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 88 1 T227 11 T160 7 T145 17
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T223 3 T241 15 T235 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T136 8 T215 8 T235 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T49 4 T152 7 T233 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T29 20 T209 13 T255 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 24 1 T259 2 T262 9 T267 5
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 18 1 T130 2 T253 4 T263 12


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 7 1 T42 1 T256 6 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 13 1 T233 13 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 26 1 T188 3 T257 1 T264 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T1 9 T9 3 T30 13
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T7 8 T132 6 T137 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T101 1 T156 10 T134 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T3 1 T140 1 T56 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T7 13 T212 1 T225 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T7 9 T113 1 T134 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T150 8 T237 1 T214 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T30 12 T44 6 T135 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 81 1 T99 11 T109 2 T210 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T133 11 T149 11 T150 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T114 13 T29 8 T101 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T40 2 T17 2 T104 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T30 5 T49 1 T56 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T208 8 T227 14 T131 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T3 1 T11 1 T28 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 125 1 T114 12 T134 11 T215 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T3 1 T49 7 T140 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1474 1 T6 26 T12 1 T13 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14604 1 T2 168 T4 16 T5 22
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T233 12 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 18 1 T188 1 T264 17 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T1 2 T9 1 T30 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T132 17 T222 10 T238 19
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T134 8 T223 17 T161 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T132 10 T214 8 T142 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T225 10 T189 3 T268 5
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T134 5 T139 4 T222 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T150 9 T237 17 T214 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T30 11 T135 14 T207 5
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T109 1 T210 4 T155 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T149 8 T150 11 T139 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T29 13 T57 10 T241 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T132 9 T148 7 T214 5
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 82 1 T30 7 T135 10 T207 3
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T227 11 T136 8 T169 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T148 11 T241 15 T235 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T215 8 T235 14 T269 15
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T49 4 T223 3 T152 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1479 1 T12 13 T13 47 T29 20


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19240 1 T1 9 T2 168 T3 3
auto[1] auto[0] 4094 1 T1 2 T9 1 T12 13