Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23334 1 T1 11 T2 168 T3 3


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 20198 1 T2 168 T3 2 T4 16
auto[ADC_CTRL_FILTER_COND_OUT] 3136 1 T1 11 T3 1 T9 4


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17465 1 T1 11 T2 168 T3 3
auto[1] 5869 1 T6 26 T7 8 T11 1


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19552 1 T1 3 T2 168 T3 3
auto[1] 3782 1 T1 8 T5 2 T6 24


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 29 1 T20 3 T270 10 T271 1
values[0] 36 1 T11 1 T16 3 T214 6
values[1] 526 1 T56 2 T104 1 T133 17
values[2] 3205 1 T1 11 T6 26 T12 14
values[3] 546 1 T7 9 T113 1 T32 2
values[4] 740 1 T3 1 T141 1 T103 13
values[5] 715 1 T3 1 T30 23 T101 1
values[6] 732 1 T114 13 T30 20 T156 10
values[7] 566 1 T40 2 T101 1 T209 14
values[8] 546 1 T3 1 T9 4 T99 11
values[9] 1089 1 T7 21 T114 12 T29 21
minimum 14604 1 T2 168 T4 16 T5 22


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 854 1 T1 11 T11 1 T16 3
values[1] 3065 1 T6 26 T12 14 T13 50
values[2] 583 1 T7 9 T49 1 T42 1
values[3] 697 1 T3 2 T101 1 T141 1
values[4] 782 1 T114 13 T30 20 T141 1
values[5] 583 1 T30 23 T156 10 T227 25
values[6] 568 1 T40 2 T140 1 T209 14
values[7] 609 1 T3 1 T9 4 T49 11
values[8] 727 1 T7 21 T114 12 T29 21
values[9] 247 1 T44 6 T135 23 T37 23
minimum 14619 1 T2 168 T4 16 T5 22


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19240 1 T1 9 T2 168 T3 3
auto[1] 4094 1 T1 2 T9 1 T12 13


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T11 1 T16 3 T29 21
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T1 3 T208 1 T149 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1689 1 T6 2 T12 14 T13 50
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 232 1 T32 2 T140 1 T134 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T7 1 T49 1 T42 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T272 1 T241 11 T169 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T3 1 T141 1 T250 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T3 1 T101 1 T103 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 253 1 T114 1 T141 1 T57 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T30 8 T149 1 T139 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T156 1 T227 12 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T30 12 T137 1 T223 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T40 2 T130 5 T132 18
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T140 1 T209 14 T132 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T3 1 T49 5 T207 6
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T9 4 T99 1 T101 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T7 2 T29 14 T30 8
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T114 1 T17 1 T140 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 95 1 T37 12 T151 12 T236 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 66 1 T44 6 T135 11 T273 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14504 1 T2 168 T4 16 T5 20
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T29 12 T56 1 T133 16
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T1 8 T208 12 T149 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 996 1 T6 24 T14 23 T39 25
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T134 10 T150 10 T161 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T7 8 T150 7 T145 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 87 1 T139 6 T233 7 T274 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T250 8 T236 1 T146 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T103 12 T148 2 T150 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T114 12 T57 11 T223 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T30 12 T139 10 T225 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 88 1 T156 9 T227 13 T133 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T30 11 T223 1 T222 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T130 1 T132 5 T148 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 106 1 T132 9 T134 10 T136 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T49 6 T207 6 T145 16
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T99 10 T56 1 T222 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T7 19 T29 7 T30 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T114 11 T17 1 T208 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 40 1 T37 11 T151 12 T23 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 46 1 T135 12 T273 2 T228 15
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 115 1 T5 2 T8 2 T32 2


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum , values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T271 1 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T20 2 T270 1 T275 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 4 1 T11 1 T16 3 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 27 1 T214 6 T276 13 T180 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T56 1 T104 1 T133 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 111 1 T149 9 T235 9 T213 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1725 1 T6 2 T12 14 T13 50
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 269 1 T1 3 T140 1 T208 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T7 1 T113 1 T49 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 135 1 T32 2 T237 18 T241 27
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T3 1 T141 1 T214 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 253 1 T103 1 T131 1 T150 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T141 1 T57 11 T131 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T3 1 T30 12 T101 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T114 1 T156 1 T227 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T30 8 T277 1 T222 9
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T40 2 T136 1 T210 18
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T101 1 T209 14 T132 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T3 1 T130 5 T132 18
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T9 4 T99 1 T140 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 362 1 T7 2 T29 14 T30 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T114 1 T17 1 T56 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14503 1 T2 168 T4 16 T5 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T20 1 T270 9 T275 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T278 5 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T56 1 T133 16 T134 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 93 1 T149 10 T235 7 T213 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 993 1 T6 24 T14 23 T39 25
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 218 1 T1 8 T208 12 T134 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T7 8 T150 7 T224 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 72 1 T139 6 T161 12 T274 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T250 8 T236 1 T146 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T103 12 T150 7 T151 16
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T57 11 T223 12 T142 18
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T30 11 T148 2 T139 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T114 12 T156 9 T227 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T30 12 T222 13 T235 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T210 10 T220 12 T279 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T132 9 T134 10 T136 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T130 1 T132 5 T148 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 111 1 T99 10 T222 7 T151 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 290 1 T7 19 T29 7 T30 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 218 1 T114 11 T17 1 T56 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 101 1 T5 2 T8 2 T32 2


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 257 1 T11 1 T16 3 T29 13
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 217 1 T1 9 T208 13 T149 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1334 1 T6 26 T12 1 T13 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T32 2 T140 1 T134 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T7 9 T49 1 T42 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T272 1 T241 1 T169 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 200 1 T3 1 T141 1 T250 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T3 1 T101 1 T103 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T114 13 T141 1 T57 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T30 13 T149 1 T139 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T156 10 T227 14 T133 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 224 1 T30 12 T137 1 T223 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T40 2 T130 4 T132 6
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T140 1 T209 1 T132 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 213 1 T3 1 T49 7 T207 7
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T9 3 T99 11 T101 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T7 21 T29 8 T30 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T114 12 T17 2 T140 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 52 1 T37 12 T151 13 T236 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 62 1 T44 6 T135 13 T273 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14619 1 T2 168 T4 16 T5 22
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T29 20 T134 5 T135 14
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T1 2 T149 8 T214 5
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1351 1 T12 13 T13 47 T34 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T150 11 T237 17 T241 15
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T150 9 T214 2 T145 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T241 10 T169 12 T139 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 85 1 T164 13 T280 19 T281 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T148 11 T150 12 T151 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 213 1 T57 10 T223 17 T142 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T30 7 T139 11 T225 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 92 1 T227 11 T210 17 T255 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T30 11 T222 8 T235 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T130 2 T132 17 T148 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T209 13 T132 9 T134 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T49 4 T207 5 T18 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T9 1 T132 10 T222 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T29 13 T30 7 T109 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T210 4 T255 3 T20 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 83 1 T37 11 T151 11 T236 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 50 1 T135 10 T228 13 T259 2


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum , values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T271 1 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 17 1 T20 2 T270 10 T275 5
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 4 1 T11 1 T16 3 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 9 1 T214 1 T276 1 T180 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T56 2 T104 1 T133 17
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T149 11 T235 8 T213 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1330 1 T6 26 T12 1 T13 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 257 1 T1 9 T140 1 T208 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T7 9 T113 1 T49 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 101 1 T32 2 T237 1 T241 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T3 1 T141 1 T214 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T103 13 T131 1 T150 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T141 1 T57 12 T131 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T3 1 T30 12 T101 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T114 13 T156 10 T227 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T30 13 T277 1 T222 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T40 2 T136 1 T210 11
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T101 1 T209 1 T132 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T3 1 T130 4 T132 6
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T9 3 T99 11 T140 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 354 1 T7 21 T29 8 T30 5
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T114 12 T17 2 T56 2
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14604 1 T2 168 T4 16 T5 22
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 11 1 T20 1 T275 10 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 23 1 T214 5 T276 12 T278 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T134 5 T135 14 T207 3
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 90 1 T149 8 T235 8 T255 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1388 1 T12 13 T13 47 T29 20
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T1 2 T150 11 T234 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T150 9 T145 4 T253 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 106 1 T237 17 T241 25 T139 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T214 2 T282 11 T164 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T150 12 T169 12 T151 14
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T57 10 T223 17 T142 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T30 11 T148 11 T139 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T227 11 T255 11 T162 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T30 7 T222 8 T235 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 94 1 T210 17 T155 8 T283 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T209 13 T132 9 T134 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T130 2 T132 17 T148 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T9 1 T132 10 T222 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 298 1 T29 13 T30 7 T49 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T135 10 T210 4 T255 3


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19240 1 T1 9 T2 168 T3 3
auto[1] auto[0] 4094 1 T1 2 T9 1 T12 13