Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20001

1

T1

11

T2

168

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T3

2

T7

30

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17576

1

T1

11

T2

168

T3

2

auto[1]

5758

1

T3

1

T6

26

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	384	1			T3	1		T141	1		T44	6
values[0]	1	1			T219	1		-	-		-	-
values[1]	684	1			T28	1		T29	33		T30	12
values[2]	530	1			T7	9		T9	4		T16	3
values[3]	637	1			T140	1		T132	23		T134	16
values[4]	698	1			T3	1		T7	8		T114	25
values[5]	679	1			T1	11		T3	1		T113	1
values[6]	692	1			T30	43		T40	2		T156	10
values[7]	565	1			T101	1		T208	8		T133	13
values[8]	596	1			T7	13		T49	11		T209	14
values[9]	3264	1			T6	26		T11	1		T12	14
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	564	1			T7	9		T16	3		T29	54
values[1]	536	1			T9	4		T140	1		T56	2
values[2]	647	1			T7	8		T141	1		T132	23
values[3]	743	1			T3	1		T113	1		T114	12
values[4]	770	1			T1	11		T3	1		T114	13
values[5]	510	1			T40	2		T134	19		T148	15
values[6]	2934	1			T6	26		T12	14		T13	50
values[7]	539	1			T7	13		T49	11		T101	1
values[8]	1114	1			T3	1		T11	1		T32	2
values[9]	92	1			T151	24		T284	1		T228	29
minimum	14885	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	11		T207	4		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T16	3		T29	35
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	4		T140	1		T109	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T56	1		T208	1		T130	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T141	1		T134	6		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T132	18		T135	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T17	1		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T113	1		T114	1		T223	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	3		T114	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	1		T30	20		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	2		T134	9		T148	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T151	15		T225	11		T285	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1748	1			T6	2		T12	14		T13	50
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T101	1		T133	1		T223	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	5		T131	1		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T101	1		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T32	2		T140	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T3	1		T11	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	12		T284	1		T228	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T248	3		T286	1		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14580	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T99	1		T104	1		T207	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T57	11		T207	2		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	8		T29	19		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T109	1		T132	9		T210	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T56	1		T208	12		T130	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T134	10		T220	12		T170	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	7		T132	5		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T134	10		T222	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T114	11		T223	3		T222	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	8		T114	12		T109	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T30	23		T56	1		T156	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	10		T148	7		T139	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T151	16		T225	10		T263	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T6	24		T14	23		T39	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T133	12		T223	12		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	6		T149	10		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	12		T148	2		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T56	3		T103	12		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T135	12		T142	18		T224	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T151	12		T228	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T248	6		T287	2		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	2		T8	2		T30	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T99	10		T207	6		T37	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T151	12		T236	9		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	1		T141	1		T44	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	1		T30	8		T57	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T29	21		T49	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T9	4		T109	2		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T16	3		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	1		T134	6		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T132	18		T135	15		T214	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T114	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T114	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	3		T17	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	1		T113	1		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T40	2		T133	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	20		T156	1		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T208	1		T214	9		T233	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T101	1		T133	1		T223	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	5		T209	14		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T148	12		T150	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T6	2		T12	14		T13	50
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	1		T101	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T151	12		T236	9		T288	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T224	16		T289	1		T254	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	4		T57	11		T207	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T29	12		T99	10		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T109	1		T132	9		T223	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	8		T29	7		T56	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T134	10		T210	1		T189	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T132	5		T135	12		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T114	12		T134	10		T222	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	7		T114	11		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	8		T17	1		T109	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	1		T224	2		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	10		T134	10		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	23		T156	9		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T208	7		T233	7		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T133	12		T223	12		T139	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	6		T149	10		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T7	12		T148	2		T150	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T6	24		T14	23		T39	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T135	12		T142	18		T222	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T57	12		T207	3		T223	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	9		T16	3		T29	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	3		T140	1		T109	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T56	2		T208	13		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	1		T134	11		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	8		T132	6		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T17	2		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T113	1		T114	12		T223	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	9		T114	13		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T30	25		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	2		T134	11		T148	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	17		T225	11		T285	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T6	26		T12	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T101	1		T133	13		T223	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T49	7		T131	1		T149	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	13		T101	1		T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T32	2		T140	1		T56	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T3	1		T11	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T151	13		T284	1		T228	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T248	7		T286	1		T287	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14667	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T99	11		T104	1		T207	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T57	10		T207	3		T281	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	33		T136	8		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T109	1		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T130	2		T214	2		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	5		T155	10		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	17		T135	14		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T132	10		T138	11		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T223	3		T237	17		T222	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	2		T226	6		T290	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	18		T150	11		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T134	8		T148	7		T214	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T151	14		T225	10		T285	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T12	13		T13	47		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T223	17		T139	4		T225	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	4		T149	8		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T148	11		T150	9		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T227	11		T210	4		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T135	10		T241	25		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T151	11		T228	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	2		T230	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T30	7		T169	12		T152	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T207	5		T160	7		T37	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T151	13		T236	10		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	1		T141	1		T44	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T28	1		T30	5		T57	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	13		T49	1		T99	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	3		T109	2		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	9		T16	3		T29	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	1		T134	11		T210	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T132	6		T135	13		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T114	13		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	8		T114	12		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	9		T17	2		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T113	1		T56	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	2		T133	11		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T30	25		T156	10		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T208	8		T214	1		T233	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T101	1		T133	13		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	7		T209	1		T149	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	13		T148	3		T150	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T6	26		T12	1		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	1		T101	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T151	11		T236	8		T240	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T241	15		T224	11		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	7		T57	10		T207	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	20		T136	8		T207	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T9	1		T109	1		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	13		T130	2		T235	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	5		T155	10		T189	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	17		T135	14		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	11		T222	10		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T223	3		T222	6		T210	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	2		T132	10		T226	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T237	17		T235	8		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	8		T148	7		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	18		T150	11		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T214	8		T233	2		T238	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T223	17		T139	4		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	4		T209	13		T149	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T148	11		T150	9		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T12	13		T13	47		T34	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T135	10		T241	10		T142	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13