Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20350

1

T2

168

T3

1

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

2984

1

T1

11

T3

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17534

1

T1

11

T2

168

T3

2

auto[1]

5800

1

T3

1

T6

26

T7

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T298	13		-	-		-	-
values[0]	88	1			T241	16		T151	16		T273	3
values[1]	637	1			T113	1		T28	1		T49	11
values[2]	813	1			T7	8		T101	2		T132	23
values[3]	705	1			T30	23		T103	13		T136	19
values[4]	732	1			T9	4		T140	1		T109	2
values[5]	637	1			T30	12		T99	11		T17	2
values[6]	551	1			T7	9		T114	12		T29	33
values[7]	609	1			T1	11		T3	2		T49	1
values[8]	2883	1			T3	1		T6	26		T12	14
values[9]	1062	1			T7	13		T11	1		T114	13
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T113	1		T28	1		T49	11
values[1]	875	1			T7	8		T30	23		T132	23
values[2]	746	1			T9	4		T103	13		T136	19
values[3]	682	1			T17	2		T140	1		T104	1
values[4]	530	1			T30	12		T99	11		T156	10
values[5]	534	1			T1	11		T3	1		T7	9
values[6]	3101	1			T3	1		T6	26		T12	14
values[7]	479	1			T3	1		T16	3		T29	21
values[8]	779	1			T7	13		T11	1		T141	1
values[9]	102	1			T114	13		T282	12		T245	1
minimum	14619	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T28	1		T56	1		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T113	1		T49	5		T101	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T132	18		T148	12		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	1		T30	12		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T103	1		T169	13		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	4		T136	9		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T104	1		T149	9		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	1		T140	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T99	1		T44	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	8		T156	1		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T7	1		T30	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	3		T114	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1783	1			T6	2		T12	14		T13	50
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T49	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	3		T29	14		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T56	1		T109	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	1		T209	14		T223	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	1		T141	1		T237	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T114	1		T292	9		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T282	12		T245	1		T300	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14516	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T56	1		T227	13		T133	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	6		T208	19		T142	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	5		T148	2		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	7		T30	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T103	12		T139	6		T301	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T136	10		T150	7		T225	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T149	10		T150	10		T224	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T17	1		T109	1		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T99	10		T207	2		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T30	4		T156	9		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	8		T30	12		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	8		T114	11		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T6	24		T14	23		T39	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T57	11		T207	6		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T29	7		T133	10		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T56	1		T109	1		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	12		T223	12		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T139	8		T145	16		T236	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T114	12		T292	6		T302	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	6		T304	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T298	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T241	16		T151	10		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T305	4		T306	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	1		T56	1		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T113	1		T49	5		T208	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T132	18		T148	12		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	1		T101	2		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T103	1		T169	13		T139	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	12		T136	9		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T149	9		T150	12		T214	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	4		T140	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T99	1		T44	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	8		T17	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	1		T29	21		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T114	1		T42	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T141	1		T223	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	3		T3	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T6	2		T12	14		T13	50
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T57	11		T109	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	1		T114	1		T29	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	1		T141	1		T132	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T151	6		T273	2		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T306	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T56	1		T227	13		T133	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	6		T208	19		T142	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	5		T148	2		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	7		T134	10		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T103	12		T139	6		T153	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	11		T136	10		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T149	10		T150	10		T224	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T109	1		T225	10		T308	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T99	10		T161	5		T233	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	4		T17	1		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	8		T29	12		T30	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T114	11		T133	16		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T223	3		T151	16		T233	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	8		T56	1		T130	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T6	24		T14	23		T39	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T57	11		T109	1		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	12		T114	12		T29	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T132	9		T134	10		T139	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T28	1		T56	2		T227	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T113	1		T49	7		T101	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T132	6		T148	3		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T7	8		T30	12		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T103	13		T169	1		T139	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	3		T136	11		T150	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T104	1		T149	11		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	2		T140	1		T109	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T99	11		T44	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T30	5		T156	10		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T7	9		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	9		T114	12		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T6	26		T12	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T49	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	3		T29	8		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T56	2		T109	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	13		T209	1		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T141	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T114	13		T292	7		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T282	1		T245	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14605	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T227	11		T134	8		T241	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	4		T132	10		T214	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T132	17		T148	11		T135	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T30	11		T134	5		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T169	12		T139	4		T236	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	1		T136	8		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	8		T150	11		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	11		T225	10		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T207	3		T210	4		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	7		T150	12		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	7		T223	3		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T1	2		T130	2		T152	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T12	13		T13	47		T29	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T57	10		T207	5		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T29	13		T160	7		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T109	1		T132	9		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T209	13		T223	17		T294	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T237	17		T139	8		T269	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T292	8		T295	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	11		T300	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T309	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T241	1		T151	7		T273	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T305	1		T306	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T28	1		T56	2		T227	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T113	1		T49	7		T208	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	6		T148	3		T135	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	8		T101	2		T134	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T103	13		T169	1		T139	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	12		T136	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T149	11		T150	11		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	3		T140	1		T109	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T99	11		T44	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	5		T17	2		T156	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	9		T29	13		T30	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T114	12		T42	1		T133	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T141	1		T223	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	9		T3	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T6	26		T12	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	1		T57	12		T109	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T7	13		T114	13		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T11	1		T141	1		T132	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T298	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T241	15		T151	9		T310	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T305	3		T306	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T227	11		T134	8		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T49	4		T132	10		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T132	17		T148	11		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	5		T135	14		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T169	12		T139	4		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	11		T136	8		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T149	8		T150	11		T214	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	1		T138	11		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T161	6		T233	6		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	7		T150	12		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T29	20		T30	7		T207	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T152	17		T251	7		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T223	3		T160	7		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	2		T130	2		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T12	13		T13	47		T34	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T57	10		T109	1		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	13		T209	13		T223	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T132	9		T237	17		T139	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13