Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19945

1

T2

168

T3

1

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3389

1

T1

11

T3

2

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17168

1

T1

11

T2

168

T3

3

auto[1]

6166

1

T6

26

T7

13

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T150	20		-	-		-	-
values[0]	89	1			T113	1		T182	18		T311	31
values[1]	532	1			T28	1		T40	2		T101	2
values[2]	499	1			T3	1		T30	23		T132	19
values[3]	731	1			T7	9		T49	1		T140	1
values[4]	548	1			T29	33		T30	12		T56	2
values[5]	3200	1			T1	11		T6	26		T7	8
values[6]	671	1			T11	1		T114	13		T16	3
values[7]	686	1			T3	1		T7	13		T114	12
values[8]	625	1			T3	1		T9	4		T56	2
values[9]	1129	1			T49	11		T209	14		T57	22
minimum	14604	1			T2	168		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	620	1			T3	1		T113	1		T28	1
values[1]	692	1			T30	23		T109	2		T131	1
values[2]	536	1			T7	9		T29	33		T49	1
values[3]	3116	1			T6	26		T12	14		T13	50
values[4]	790	1			T7	8		T114	13		T29	21
values[5]	724	1			T1	11		T7	13		T11	1
values[6]	629	1			T3	1		T32	2		T17	2
values[7]	590	1			T3	1		T9	4		T56	2
values[8]	820	1			T49	11		T209	14		T57	22
values[9]	196	1			T136	1		T149	1		T150	20
minimum	14621	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T40	2		T101	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T113	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T109	1		T207	4		T223	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	12		T131	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T29	21		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T234	6		T162	3		T253	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1687	1			T6	2		T12	14		T13	50
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T148	12		T135	11		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T30	8		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T114	1		T29	14		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T114	1		T99	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	3		T7	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	2		T42	1		T130	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T17	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T56	1		T18	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	4		T133	1		T237	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	5		T209	14		T241	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T57	11		T132	11		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T136	1		T149	1		T150	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T160	10		T282	12		T281	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	16		T312	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T109	1		T134	10		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T156	9		T133	10		T139	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T109	1		T207	2		T223	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	11		T132	9		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	8		T29	12		T56	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T234	4		T162	9		T89	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T6	24		T14	23		T39	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T148	2		T135	12		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	7		T30	12		T56	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T114	12		T29	7		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T114	11		T99	10		T208	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	8		T7	12		T220	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T130	1		T235	7		T153	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T150	7		T222	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	1		T210	10		T236	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	16		T213	5		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	6		T210	7		T151	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T57	11		T133	12		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T150	7		T224	2		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T160	10		T281	8		T302	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T150	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T311	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T113	1		T182	9		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T28	1		T40	2		T101	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T140	1		T156	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T207	4		T223	5		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	1		T30	12		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	1		T49	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T131	1		T214	9		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	21		T30	8		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	12		T135	11		T285	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1748	1			T6	2		T7	1		T12	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	3		T29	14		T148	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T99	1		T140	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T114	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T114	1		T32	2		T222	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	1		T7	1		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T56	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	4		T133	1		T237	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T49	5		T209	14		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T57	11		T132	11		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	168		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T150	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T311	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T182	9		T314	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T109	1		T134	10		T224	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T156	9		T133	10		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T207	2		T223	4		T139	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T30	11		T132	9		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	8		T109	1		T132	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T161	12		T234	4		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T29	12		T30	4		T56	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T148	2		T135	12		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T6	24		T7	7		T14	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	8		T29	7		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T99	10		T208	7		T227	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T114	12		T220	10		T297	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T114	11		T222	13		T235	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	12		T17	1		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T56	1		T130	1		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	16		T213	5		T233	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	6		T224	2		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T57	11		T133	12		T134	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T28	1		T40	2		T101	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	1		T113	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T109	2		T207	3		T223	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	12		T131	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	9		T29	13		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T234	5		T162	10		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T6	26		T12	1		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T148	3		T135	13		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	8		T30	13		T56	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T114	13		T29	8		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T114	12		T99	11		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	9		T7	13		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	2		T42	1		T130	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T17	2		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T56	2		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	3		T133	17		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	7		T209	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T57	12		T132	1		T133	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T136	1		T149	1		T150	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T160	11		T282	1		T281	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	1		T312	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T109	1		T134	8		T224	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	8		T292	12		T254	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T207	3		T223	3		T214	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T30	11		T132	9		T214	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	20		T132	17		T207	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T234	5		T162	2		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T12	13		T13	47		T30	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	11		T135	10		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	7		T135	14		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T29	13		T148	7		T161	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T227	11		T142	11		T222	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	2		T152	7		T239	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T130	2		T235	8		T255	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	9		T222	6		T155	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T18	1		T210	17		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T237	17		T152	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	4		T209	13		T241	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T57	10		T132	10		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T150	12		T139	11		T226	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T160	9		T282	11		T281	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T269	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T150	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T311	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T113	1		T182	10		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T28	1		T40	2		T101	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T140	1		T156	10		T133	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T207	3		T223	6		T139	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	1		T30	12		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	9		T49	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T131	1		T214	1		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	13		T30	5		T56	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T148	3		T135	13		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T6	26		T7	8		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	9		T29	8		T148	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T99	11		T140	1		T208	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T114	13		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T114	12		T32	2		T222	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T7	13		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T56	2		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	3		T133	17		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T49	7		T209	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T57	12		T132	1		T133	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14604	1			T2	168		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T150	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T311	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T182	8		T314	21		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T109	1		T134	8		T224	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T139	8		T269	15		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T207	3		T223	3		T139	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T30	11		T132	9		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T132	17		T207	5		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T214	8		T161	13		T234	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T29	20		T30	7		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T148	11		T135	10		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T12	13		T13	47		T30	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	2		T29	13		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T227	11		T135	14		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T239	9		T297	10		T189	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T222	8		T235	8		T236	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T150	9		T222	6		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	2		T18	1		T210	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T237	17		T152	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T49	4		T209	13		T241	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T57	10		T132	10		T134	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13