Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

11

T2

168

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20416

1

T2

168

T3

1

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

2918

1

T1

11

T3

2

T113

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17172

1

T2

167

T3

3

T4

16

auto[1]

6162

1

T1

11

T2

1

T6

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19552

1

T1

3

T2

168

T3

3

auto[1]

3782

1

T1

8

T5

2

T6

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	553	1			T2	1		T10	5		T16	3
values[0]	20	1			T113	1		T150	17		T315	2
values[1]	655	1			T7	9		T9	4		T11	1
values[2]	2978	1			T6	26		T12	14		T13	50
values[3]	621	1			T7	8		T30	12		T99	11
values[4]	700	1			T30	20		T141	1		T132	19
values[5]	649	1			T1	11		T3	1		T16	3
values[6]	665	1			T7	13		T28	1		T40	2
values[7]	551	1			T3	1		T101	1		T56	2
values[8]	781	1			T3	1		T30	23		T49	11
values[9]	858	1			T114	12		T29	33		T49	1
minimum	14303	1			T2	167		T4	16		T5	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T11	1		T29	21		T17	2
values[1]	2954	1			T6	26		T12	14		T13	50
values[2]	643	1			T7	8		T30	20		T99	11
values[3]	645	1			T141	1		T132	19		T133	17
values[4]	582	1			T1	11		T3	1		T16	3
values[5]	731	1			T7	13		T104	1		T130	6
values[6]	519	1			T3	1		T40	2		T101	1
values[7]	781	1			T3	1		T30	23		T49	11
values[8]	825	1			T114	12		T29	33		T49	1
values[9]	154	1			T101	1		T222	22		T257	1
minimum	14856	1			T2	168		T4	16		T5	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

4094

1

T1

2

T9

1

T12

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T29	14		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T131	1		T149	9		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T6	2		T12	14		T13	50
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	8		T56	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	1		T223	18		T143	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	8		T99	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T132	10		T133	1		T214	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	1		T137	1		T207	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T16	3		T227	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	3		T28	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	1		T130	5		T135	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T104	1		T133	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T101	1		T42	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T40	2		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T30	12		T49	5		T241	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	1		T208	1		T57	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T114	1		T29	21		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	1		T132	11		T134	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T222	9		T257	1		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T101	1		T317	15		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14527	1			T2	168		T4	16		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T113	1		T140	1		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	7		T17	1		T156	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T149	10		T160	10		T250	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T6	24		T14	23		T39	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T30	4		T56	3		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	7		T223	12		T160	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	12		T99	10		T103	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	9		T133	16		T225	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T207	6		T150	7		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T227	13		T135	12		T281	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	8		T231	14		T89	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	12		T130	1		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T133	10		T163	3		T228	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T109	1		T233	7		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T56	1		T150	10		T151	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	11		T49	6		T222	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T208	7		T57	11		T132	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T114	11		T29	12		T109	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T134	10		T139	10		T297	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	13		T259	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T317	5		T318	4		T248	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	2		T7	8		T8	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T150	7		T210	1		T233	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T2	1		T10	5		T16	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T101	1		T134	6		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T113	1		T150	10		T315	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	1		T9	4		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T140	1		T131	1		T149	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1771	1			T6	2		T12	14		T13	50
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T56	1		T214	6		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	1		T143	2		T255	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	8		T99	1		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	10		T223	18		T214	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	8		T141	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T16	3		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	3		T140	1		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T135	11		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	1		T40	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T101	1		T109	1		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T56	1		T209	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T30	12		T49	5		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	1		T208	1		T57	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T114	1		T29	21		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T49	1		T132	11		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14202	1			T2	167		T4	16		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T134	10		T278	8		T319	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T134	10		T274	9		T317	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T150	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	8		T29	7		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	10		T210	1		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T6	24		T14	23		T39	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T56	3		T250	8		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	7		T273	2		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	4		T99	10		T103	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	9		T223	12		T160	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	12		T207	6		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T227	13		T133	16		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	8		T150	7		T151	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	12		T135	12		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T133	10		T163	3		T228	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T109	1		T130	1		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T56	1		T247	10		T320	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	11		T49	6		T222	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T208	7		T57	11		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T114	11		T29	12		T109	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T139	10		T297	6		T283	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	2		T8	2		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	1		T29	8		T17	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T131	1		T149	11		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T6	26		T12	1		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	5		T56	4		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	8		T223	13		T143	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	13		T99	11		T103	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	10		T133	17		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T141	1		T137	1		T207	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T16	3		T227	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	9		T28	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T7	13		T130	4		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T104	1		T133	11		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T101	1		T42	1		T109	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	1		T40	2		T56	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T30	12		T49	7		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T208	8		T57	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T114	12		T29	13		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	1		T132	1		T134	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T222	14		T257	1		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T101	1		T317	6		T318	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14656	1			T2	168		T4	16		T5	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T113	1		T140	1		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	13		T169	12		T210	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T149	8		T160	9		T274	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T12	13		T13	47		T34	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T30	7		T207	3		T214	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T223	17		T160	7		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T30	7		T136	8		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	9		T214	8		T160	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T207	5		T150	12		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T227	11		T135	14		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	2		T237	17		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T130	2		T135	10		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T253	13		T268	12		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T233	2		T162	2		T94	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T209	13		T150	11		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T30	11		T49	4		T241	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T57	10		T132	17		T235	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T29	20		T109	1		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	10		T134	5		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T222	8		T259	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T317	14		T248	2		T296	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T9	1		T18	1		T236	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T150	9		T152	17		T233	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T2	1		T10	5		T16	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T101	1		T134	11		T274	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T113	1		T150	8		T315	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	9		T9	3		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T140	1		T131	1		T149	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T6	26		T12	1		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T56	4		T214	1		T250	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	8		T143	2		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T30	5		T99	11		T103	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	10		T223	13		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T30	13		T141	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T16	3		T227	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	9		T140	1		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	13		T135	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	1		T40	2		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T101	1		T109	2		T130	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T3	1		T56	2		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	12		T49	7		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T208	8		T57	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T114	12		T29	13		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	1		T132	1		T139	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14303	1			T2	167		T4	16		T5	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T134	8		T239	9		T305	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T134	5		T317	14		T182	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T150	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T29	13		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T149	8		T160	9		T152	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T12	13		T13	47		T34	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T214	5		T321	13		T264	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T255	5		T292	12		T263	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	7		T136	8		T207	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	9		T223	17		T214	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	7		T207	5		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T227	11		T135	14		T214	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	2		T150	12		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T135	10		T223	3		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T253	13		T268	12		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	2		T161	6		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T209	13		T255	11		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T30	11		T49	4		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T57	10		T132	17		T150	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	20		T109	1		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	10		T139	11		T297	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19240

1

T1

9

T2

168

T3

3

auto[1]

auto[0]

4094

1

T1

2

T9

1

T12

13