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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.68 99.07 96.67 100.00 100.00 98.83 98.33 90.84


Total test records in report: 920
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T111 /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.906567545 Aug 16 05:13:48 PM PDT 24 Aug 16 05:14:03 PM PDT 24 8327268968 ps
T795 /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3555908303 Aug 16 05:14:59 PM PDT 24 Aug 16 05:17:57 PM PDT 24 323114175490 ps
T796 /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4278604602 Aug 16 05:13:14 PM PDT 24 Aug 16 05:25:57 PM PDT 24 329074369945 ps
T797 /workspace/coverage/default/46.adc_ctrl_alert_test.2761698305 Aug 16 05:15:24 PM PDT 24 Aug 16 05:15:26 PM PDT 24 343174227 ps
T798 /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2605324118 Aug 16 05:12:54 PM PDT 24 Aug 16 05:17:11 PM PDT 24 489724951684 ps
T799 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2879426678 Aug 16 05:12:14 PM PDT 24 Aug 16 05:12:16 PM PDT 24 488454741 ps
T58 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2101169355 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:32 PM PDT 24 8058569594 ps
T67 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2990449420 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 417142462 ps
T77 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1994994034 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:09 PM PDT 24 461807979 ps
T55 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3969367350 Aug 16 05:11:50 PM PDT 24 Aug 16 05:11:51 PM PDT 24 536583622 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2666710095 Aug 16 05:11:40 PM PDT 24 Aug 16 05:11:41 PM PDT 24 511741200 ps
T800 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.535129187 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:14 PM PDT 24 469353488 ps
T52 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.486625688 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:26 PM PDT 24 5142612978 ps
T116 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3895490039 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:10 PM PDT 24 557911833 ps
T801 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3825721260 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:08 PM PDT 24 450145516 ps
T802 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1743347354 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:21 PM PDT 24 469247928 ps
T803 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.269411753 Aug 16 05:12:00 PM PDT 24 Aug 16 05:12:02 PM PDT 24 497328064 ps
T76 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1274544079 Aug 16 05:11:48 PM PDT 24 Aug 16 05:11:51 PM PDT 24 555627337 ps
T117 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.258045288 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:20 PM PDT 24 472446996 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1576833772 Aug 16 05:11:45 PM PDT 24 Aug 16 05:11:47 PM PDT 24 1134915116 ps
T804 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1727384668 Aug 16 05:12:22 PM PDT 24 Aug 16 05:12:33 PM PDT 24 376692338 ps
T805 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1394794709 Aug 16 05:12:00 PM PDT 24 Aug 16 05:12:01 PM PDT 24 329808185 ps
T53 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1541943299 Aug 16 05:12:00 PM PDT 24 Aug 16 05:13:40 PM PDT 24 45008014062 ps
T126 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.379084624 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:10 PM PDT 24 2280464556 ps
T59 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2594250601 Aug 16 05:11:44 PM PDT 24 Aug 16 05:11:48 PM PDT 24 4924379576 ps
T119 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3231236431 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:06 PM PDT 24 617488557 ps
T60 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4232178542 Aug 16 05:12:17 PM PDT 24 Aug 16 05:12:23 PM PDT 24 8904866332 ps
T127 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2591823329 Aug 16 05:11:57 PM PDT 24 Aug 16 05:12:02 PM PDT 24 2084252677 ps
T80 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.137714666 Aug 16 05:12:15 PM PDT 24 Aug 16 05:12:17 PM PDT 24 514409799 ps
T128 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1965438901 Aug 16 05:11:38 PM PDT 24 Aug 16 05:11:39 PM PDT 24 347555487 ps
T82 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2546073035 Aug 16 05:12:15 PM PDT 24 Aug 16 05:12:17 PM PDT 24 382236593 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1895785510 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:04 PM PDT 24 525688181 ps
T102 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.801182907 Aug 16 05:12:22 PM PDT 24 Aug 16 05:12:24 PM PDT 24 392783574 ps
T807 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1476013952 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:19 PM PDT 24 370210181 ps
T808 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2334872667 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:49 PM PDT 24 600559185 ps
T129 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3079638923 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:13 PM PDT 24 339969298 ps
T809 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2043028876 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:14 PM PDT 24 448276357 ps
T810 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3062202639 Aug 16 05:12:22 PM PDT 24 Aug 16 05:12:23 PM PDT 24 433425442 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1784906287 Aug 16 05:11:40 PM PDT 24 Aug 16 05:13:08 PM PDT 24 26351774324 ps
T811 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2174208911 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:14 PM PDT 24 510138175 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1212075207 Aug 16 05:12:10 PM PDT 24 Aug 16 05:12:20 PM PDT 24 4151868466 ps
T63 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2225852752 Aug 16 05:12:20 PM PDT 24 Aug 16 05:12:25 PM PDT 24 4494990883 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2400713017 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:10 PM PDT 24 8375784778 ps
T78 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.514350060 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:09 PM PDT 24 10472592587 ps
T813 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4205281497 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:04 PM PDT 24 337429594 ps
T814 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.381055152 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:20 PM PDT 24 444081175 ps
T815 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3945603270 Aug 16 05:12:20 PM PDT 24 Aug 16 05:12:22 PM PDT 24 418894024 ps
T816 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3808504178 Aug 16 05:12:03 PM PDT 24 Aug 16 05:12:04 PM PDT 24 483534229 ps
T817 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3283819164 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:20 PM PDT 24 417080605 ps
T68 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1418958372 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:07 PM PDT 24 344452595 ps
T71 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3052008595 Aug 16 05:12:16 PM PDT 24 Aug 16 05:12:28 PM PDT 24 8283626831 ps
T818 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3024114816 Aug 16 05:12:14 PM PDT 24 Aug 16 05:12:15 PM PDT 24 512347348 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3887753231 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:50 PM PDT 24 1199868790 ps
T819 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2168976052 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:22 PM PDT 24 508791887 ps
T820 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2654073760 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:20 PM PDT 24 372996315 ps
T74 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1809867476 Aug 16 05:11:59 PM PDT 24 Aug 16 05:12:03 PM PDT 24 4428157493 ps
T79 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2682329488 Aug 16 05:12:03 PM PDT 24 Aug 16 05:12:11 PM PDT 24 8602367497 ps
T821 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.535624346 Aug 16 05:11:43 PM PDT 24 Aug 16 05:11:45 PM PDT 24 2285244316 ps
T822 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3229125552 Aug 16 05:12:23 PM PDT 24 Aug 16 05:12:25 PM PDT 24 384912546 ps
T823 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3293017824 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:24 PM PDT 24 26152486663 ps
T824 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.352988763 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:20 PM PDT 24 492615472 ps
T825 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3614312826 Aug 16 05:12:23 PM PDT 24 Aug 16 05:12:40 PM PDT 24 4426978163 ps
T69 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.936779312 Aug 16 05:12:22 PM PDT 24 Aug 16 05:12:25 PM PDT 24 397959991 ps
T75 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2663949084 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:04 PM PDT 24 541263440 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.220649727 Aug 16 05:12:01 PM PDT 24 Aug 16 05:12:05 PM PDT 24 2327033978 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3374465556 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:25 PM PDT 24 2194545554 ps
T121 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.229955150 Aug 16 05:11:40 PM PDT 24 Aug 16 05:11:46 PM PDT 24 1177420556 ps
T122 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3040553167 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:20 PM PDT 24 558238627 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.197344184 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:03 PM PDT 24 391131610 ps
T829 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4136127490 Aug 16 05:12:03 PM PDT 24 Aug 16 05:12:04 PM PDT 24 610490602 ps
T81 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2150507952 Aug 16 05:11:51 PM PDT 24 Aug 16 05:11:53 PM PDT 24 419614126 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3657608890 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:13 PM PDT 24 506560685 ps
T831 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.298979673 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:18 PM PDT 24 4153277874 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1552397097 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:06 PM PDT 24 428876196 ps
T833 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1077782941 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:13 PM PDT 24 364496662 ps
T834 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3980529523 Aug 16 05:12:00 PM PDT 24 Aug 16 05:12:01 PM PDT 24 338175664 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1998779017 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:16 PM PDT 24 2336045709 ps
T123 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3034164235 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:05 PM PDT 24 359252426 ps
T836 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.556707617 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:08 PM PDT 24 2317709229 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3878366406 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 708477973 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2077056881 Aug 16 05:12:17 PM PDT 24 Aug 16 05:12:21 PM PDT 24 426311811 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3785441673 Aug 16 05:11:58 PM PDT 24 Aug 16 05:12:02 PM PDT 24 797788793 ps
T839 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1074926172 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:10 PM PDT 24 400901351 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2927740054 Aug 16 05:12:01 PM PDT 24 Aug 16 05:12:03 PM PDT 24 472948390 ps
T841 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3980424135 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:12 PM PDT 24 980575619 ps
T842 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3634639987 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:09 PM PDT 24 369403319 ps
T843 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3372027949 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:19 PM PDT 24 289769586 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3798019378 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:07 PM PDT 24 422933647 ps
T845 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3285388508 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:21 PM PDT 24 370186645 ps
T846 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.74892665 Aug 16 05:11:41 PM PDT 24 Aug 16 05:11:43 PM PDT 24 491647895 ps
T847 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2988376298 Aug 16 05:11:48 PM PDT 24 Aug 16 05:11:49 PM PDT 24 316907624 ps
T848 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1874487933 Aug 16 05:12:14 PM PDT 24 Aug 16 05:12:16 PM PDT 24 332272336 ps
T849 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1143762858 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:23 PM PDT 24 706325628 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3654198781 Aug 16 05:12:20 PM PDT 24 Aug 16 05:12:22 PM PDT 24 507945216 ps
T851 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3743487657 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 356029846 ps
T83 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1447100547 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:14 PM PDT 24 8270237754 ps
T852 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2871940087 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:27 PM PDT 24 8703472590 ps
T853 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3332776621 Aug 16 05:11:50 PM PDT 24 Aug 16 05:11:52 PM PDT 24 383798846 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1558336410 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:06 PM PDT 24 470099362 ps
T855 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.35362090 Aug 16 05:12:07 PM PDT 24 Aug 16 05:12:08 PM PDT 24 344438954 ps
T856 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.461338070 Aug 16 05:12:00 PM PDT 24 Aug 16 05:12:04 PM PDT 24 338877768 ps
T857 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2986835242 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:12 PM PDT 24 469541825 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2983763567 Aug 16 05:11:59 PM PDT 24 Aug 16 05:12:10 PM PDT 24 4383407299 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.678683397 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:06 PM PDT 24 878673006 ps
T353 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1543318846 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:22 PM PDT 24 8262673962 ps
T860 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1513233408 Aug 16 05:12:16 PM PDT 24 Aug 16 05:12:17 PM PDT 24 357899616 ps
T861 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3759830412 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:52 PM PDT 24 584876108 ps
T862 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1441678961 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:13 PM PDT 24 557582149 ps
T352 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3268289857 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:26 PM PDT 24 8422998979 ps
T863 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1609081354 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:13 PM PDT 24 441166002 ps
T864 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1518786446 Aug 16 05:11:51 PM PDT 24 Aug 16 05:11:52 PM PDT 24 355150075 ps
T865 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2867710534 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:27 PM PDT 24 4107159079 ps
T124 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.718212161 Aug 16 05:12:16 PM PDT 24 Aug 16 05:12:19 PM PDT 24 543899605 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3057102128 Aug 16 05:12:24 PM PDT 24 Aug 16 05:12:25 PM PDT 24 416920654 ps
T867 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2165045591 Aug 16 05:12:03 PM PDT 24 Aug 16 05:12:08 PM PDT 24 5418581406 ps
T868 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1612367411 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:20 PM PDT 24 446357480 ps
T869 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3117252716 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:08 PM PDT 24 2269821156 ps
T870 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2410687831 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 398276876 ps
T871 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3486393028 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:09 PM PDT 24 447377872 ps
T872 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1882387973 Aug 16 05:12:15 PM PDT 24 Aug 16 05:12:17 PM PDT 24 528450526 ps
T873 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3147722430 Aug 16 05:11:45 PM PDT 24 Aug 16 05:11:47 PM PDT 24 325873167 ps
T874 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1335800978 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:07 PM PDT 24 1145118454 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2261663469 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:06 PM PDT 24 387830667 ps
T876 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1861404423 Aug 16 05:11:44 PM PDT 24 Aug 16 05:11:45 PM PDT 24 1149342317 ps
T877 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2405408300 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:13 PM PDT 24 514998745 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.135798415 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 514738351 ps
T879 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3981390877 Aug 16 05:12:10 PM PDT 24 Aug 16 05:12:12 PM PDT 24 551902040 ps
T880 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2065428061 Aug 16 05:12:13 PM PDT 24 Aug 16 05:12:16 PM PDT 24 603304446 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1152096191 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:09 PM PDT 24 521329578 ps
T882 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1589426255 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:21 PM PDT 24 403450695 ps
T883 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3040929783 Aug 16 05:12:19 PM PDT 24 Aug 16 05:12:22 PM PDT 24 513541701 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.665967996 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:23 PM PDT 24 1026165137 ps
T885 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2172639076 Aug 16 05:12:25 PM PDT 24 Aug 16 05:12:26 PM PDT 24 493026013 ps
T886 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2717239446 Aug 16 05:12:04 PM PDT 24 Aug 16 05:12:08 PM PDT 24 559667350 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4000525370 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:10 PM PDT 24 366388323 ps
T888 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1728406345 Aug 16 05:12:06 PM PDT 24 Aug 16 05:12:08 PM PDT 24 394506351 ps
T889 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2596098686 Aug 16 05:12:16 PM PDT 24 Aug 16 05:12:17 PM PDT 24 300305075 ps
T890 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.15991900 Aug 16 05:12:07 PM PDT 24 Aug 16 05:12:09 PM PDT 24 395451469 ps
T125 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4084912191 Aug 16 05:11:58 PM PDT 24 Aug 16 05:12:01 PM PDT 24 364787913 ps
T891 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.295375993 Aug 16 05:12:12 PM PDT 24 Aug 16 05:12:13 PM PDT 24 320877281 ps
T892 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2641074653 Aug 16 05:11:44 PM PDT 24 Aug 16 05:11:47 PM PDT 24 3893305267 ps
T893 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1372866553 Aug 16 05:12:20 PM PDT 24 Aug 16 05:12:24 PM PDT 24 4636369533 ps
T894 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3481887696 Aug 16 05:12:10 PM PDT 24 Aug 16 05:12:12 PM PDT 24 2927982240 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2845372596 Aug 16 05:12:24 PM PDT 24 Aug 16 05:12:26 PM PDT 24 409993868 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2568146038 Aug 16 05:12:16 PM PDT 24 Aug 16 05:12:19 PM PDT 24 4487812649 ps
T897 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4283569233 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:19 PM PDT 24 512068231 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2667636103 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:18 PM PDT 24 2151479415 ps
T899 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2814150692 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:51 PM PDT 24 871788046 ps
T900 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2342752141 Aug 16 05:12:22 PM PDT 24 Aug 16 05:12:24 PM PDT 24 364231961 ps
T901 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.365172075 Aug 16 05:12:02 PM PDT 24 Aug 16 05:12:03 PM PDT 24 516309037 ps
T902 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2067278041 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:29 PM PDT 24 8527196665 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3863175032 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:54 PM PDT 24 1113135829 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2307158239 Aug 16 05:11:56 PM PDT 24 Aug 16 05:12:00 PM PDT 24 831340996 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1258782445 Aug 16 05:12:18 PM PDT 24 Aug 16 05:12:20 PM PDT 24 3974572252 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1877252573 Aug 16 05:12:08 PM PDT 24 Aug 16 05:12:10 PM PDT 24 522141664 ps
T907 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.872113413 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:21 PM PDT 24 8416608516 ps
T908 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3567498971 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:23 PM PDT 24 454368179 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3159150362 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:07 PM PDT 24 373378395 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2489201635 Aug 16 05:11:49 PM PDT 24 Aug 16 05:11:52 PM PDT 24 707700183 ps
T911 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3871286721 Aug 16 05:11:53 PM PDT 24 Aug 16 05:11:55 PM PDT 24 2204348208 ps
T912 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1565384951 Aug 16 05:12:10 PM PDT 24 Aug 16 05:12:12 PM PDT 24 369686428 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1543327490 Aug 16 05:12:10 PM PDT 24 Aug 16 05:12:16 PM PDT 24 2807634255 ps
T354 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3784907935 Aug 16 05:11:38 PM PDT 24 Aug 16 05:11:43 PM PDT 24 4114611155 ps
T914 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2076861378 Aug 16 05:12:20 PM PDT 24 Aug 16 05:12:22 PM PDT 24 426028923 ps
T915 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1422350114 Aug 16 05:12:21 PM PDT 24 Aug 16 05:12:22 PM PDT 24 330147682 ps
T916 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3283156405 Aug 16 05:12:11 PM PDT 24 Aug 16 05:12:13 PM PDT 24 320993437 ps
T917 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.46115319 Aug 16 05:12:09 PM PDT 24 Aug 16 05:12:11 PM PDT 24 387205847 ps
T918 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3546418334 Aug 16 05:12:13 PM PDT 24 Aug 16 05:12:14 PM PDT 24 548261611 ps
T919 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2941586926 Aug 16 05:12:05 PM PDT 24 Aug 16 05:12:12 PM PDT 24 3952713939 ps
T920 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3316497610 Aug 16 05:12:07 PM PDT 24 Aug 16 05:12:11 PM PDT 24 4359951636 ps

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1813677328
Short name T7
Test name
Test status
Simulation time 501692312773 ps
CPU time 309.42 seconds
Started Aug 16 05:14:54 PM PDT 24
Finished Aug 16 05:20:04 PM PDT 24
Peak memory 202072 kb
Host smart-dfec4cfe-471b-421f-ae35-6d502873a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813677328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1813677328
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3020885649
Short name T2
Test name
Test status
Simulation time 110953208222 ps
CPU time 548.22 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:22:29 PM PDT 24
Peak memory 202324 kb
Host smart-4c2ac5c5-467a-4cdb-bb06-613baa9bc961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020885649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3020885649
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2788504650
Short name T30
Test name
Test status
Simulation time 496794093622 ps
CPU time 174.04 seconds
Started Aug 16 05:14:22 PM PDT 24
Finished Aug 16 05:17:16 PM PDT 24
Peak memory 202048 kb
Host smart-04079d65-2778-4e3d-b671-8c6d524c01e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788504650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2788504650
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1865646923
Short name T44
Test name
Test status
Simulation time 28620563295 ps
CPU time 10.88 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:13:31 PM PDT 24
Peak memory 210456 kb
Host smart-d3dd9e90-85aa-4bc2-aac4-9cf6cb83eb16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865646923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1865646923
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.894607116
Short name T132
Test name
Test status
Simulation time 532031429297 ps
CPU time 156.26 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:17:33 PM PDT 24
Peak memory 202116 kb
Host smart-ca9eb01e-5b8c-4202-b6dd-dd61a9fb5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894607116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.894607116
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2216012048
Short name T210
Test name
Test status
Simulation time 676944937794 ps
CPU time 815.88 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:26:52 PM PDT 24
Peak memory 201936 kb
Host smart-c8e1b0f2-14bf-4598-b7d0-f821de33fee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216012048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2216012048
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1600953917
Short name T139
Test name
Test status
Simulation time 512646462093 ps
CPU time 246.23 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:17:36 PM PDT 24
Peak memory 202076 kb
Host smart-667d70d6-2819-4990-bdc5-ce9c80632ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600953917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1600953917
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1586007874
Short name T17
Test name
Test status
Simulation time 6265995577 ps
CPU time 14.5 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 210700 kb
Host smart-263d1cbf-0466-4405-95f8-73b5a09a19f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586007874 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1586007874
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.389221946
Short name T233
Test name
Test status
Simulation time 491675537733 ps
CPU time 561.61 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:23:32 PM PDT 24
Peak memory 202044 kb
Host smart-ea956389-ff88-449d-bed1-7da52cbb6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389221946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.389221946
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1067581376
Short name T150
Test name
Test status
Simulation time 521261711777 ps
CPU time 407.85 seconds
Started Aug 16 05:12:53 PM PDT 24
Finished Aug 16 05:19:41 PM PDT 24
Peak memory 202136 kb
Host smart-c4257054-b3eb-42e6-96a2-ba6696e7bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067581376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1067581376
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3618978802
Short name T223
Test name
Test status
Simulation time 575735175256 ps
CPU time 828.37 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:27:02 PM PDT 24
Peak memory 202160 kb
Host smart-54b3cb55-0c86-4108-ad31-fea58997c19a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618978802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3618978802
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2780925587
Short name T29
Test name
Test status
Simulation time 365068611807 ps
CPU time 782.17 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:27:27 PM PDT 24
Peak memory 202044 kb
Host smart-6052e960-96f3-4cec-90c8-788224389cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780925587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2780925587
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3539900929
Short name T335
Test name
Test status
Simulation time 597840217437 ps
CPU time 2128.42 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:48:43 PM PDT 24
Peak memory 202336 kb
Host smart-bb8f69e7-2277-4f04-950b-79d78b832b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539900929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3539900929
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.600495328
Short name T3
Test name
Test status
Simulation time 480402220437 ps
CPU time 86.84 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:16:26 PM PDT 24
Peak memory 202084 kb
Host smart-fcd96120-a023-43a0-9b9e-0199f635f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600495328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.600495328
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4232178542
Short name T60
Test name
Test status
Simulation time 8904866332 ps
CPU time 5.28 seconds
Started Aug 16 05:12:17 PM PDT 24
Finished Aug 16 05:12:23 PM PDT 24
Peak memory 201044 kb
Host smart-677a0480-05b0-4419-a1d9-86cab5ed22c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232178542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4232178542
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.814578697
Short name T27
Test name
Test status
Simulation time 423604444 ps
CPU time 0.73 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:14:11 PM PDT 24
Peak memory 201940 kb
Host smart-2c750bf1-c42b-4d51-8dd4-44f6f6735c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814578697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.814578697
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3641806875
Short name T134
Test name
Test status
Simulation time 507848499917 ps
CPU time 292.57 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:18:39 PM PDT 24
Peak memory 202052 kb
Host smart-01ad8bae-ae25-448e-b763-439fd3c78492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641806875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3641806875
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1784906287
Short name T54
Test name
Test status
Simulation time 26351774324 ps
CPU time 87.82 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:13:08 PM PDT 24
Peak memory 201096 kb
Host smart-4aebc005-2b8a-4152-a52a-4048a775fa46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784906287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1784906287
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.202754304
Short name T151
Test name
Test status
Simulation time 539219190564 ps
CPU time 778.88 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:27:01 PM PDT 24
Peak memory 202076 kb
Host smart-8071c449-3b07-47d7-8216-bf6da8d67155
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202754304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.202754304
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2565637635
Short name T13
Test name
Test status
Simulation time 606357028809 ps
CPU time 711.84 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:25:54 PM PDT 24
Peak memory 202068 kb
Host smart-3d125286-69af-4250-b72f-06f375ad2945
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565637635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2565637635
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1346366118
Short name T133
Test name
Test status
Simulation time 490699129982 ps
CPU time 1043.31 seconds
Started Aug 16 05:13:45 PM PDT 24
Finished Aug 16 05:31:09 PM PDT 24
Peak memory 202100 kb
Host smart-8913479f-fef3-464a-9065-319b92b4d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346366118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1346366118
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.936779312
Short name T69
Test name
Test status
Simulation time 397959991 ps
CPU time 2.87 seconds
Started Aug 16 05:12:22 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 210384 kb
Host smart-f38755c3-f476-42e4-b365-c99a0e1032df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936779312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.936779312
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.506233924
Short name T235
Test name
Test status
Simulation time 333681630990 ps
CPU time 819.34 seconds
Started Aug 16 05:14:01 PM PDT 24
Finished Aug 16 05:27:41 PM PDT 24
Peak memory 202076 kb
Host smart-6d6357ec-5fc4-45f4-9e21-58415dce72c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506233924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.506233924
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1974717927
Short name T253
Test name
Test status
Simulation time 646305066535 ps
CPU time 741.76 seconds
Started Aug 16 05:14:09 PM PDT 24
Finished Aug 16 05:26:31 PM PDT 24
Peak memory 202016 kb
Host smart-bc967a38-82b0-4ad4-914a-a447a187ec62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974717927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1974717927
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2409890137
Short name T248
Test name
Test status
Simulation time 489713221018 ps
CPU time 526.65 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:22:08 PM PDT 24
Peak memory 202144 kb
Host smart-853f155e-d613-433b-b510-b904d26c1a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409890137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2409890137
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.581604829
Short name T94
Test name
Test status
Simulation time 516229655577 ps
CPU time 298.03 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:18:13 PM PDT 24
Peak memory 202064 kb
Host smart-2bac3531-1bf8-4ff5-8f09-e62085b7c924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581604829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.581604829
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.747838079
Short name T255
Test name
Test status
Simulation time 532072186420 ps
CPU time 1123.31 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:33:50 PM PDT 24
Peak memory 202072 kb
Host smart-6a845dd3-7b40-402d-b7f0-fff724b3fbf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747838079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.747838079
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.540341642
Short name T281
Test name
Test status
Simulation time 544056292275 ps
CPU time 329.5 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:18:43 PM PDT 24
Peak memory 202108 kb
Host smart-215fb8d6-1be8-4580-98b8-38cbc2077ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540341642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.540341642
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2838399112
Short name T222
Test name
Test status
Simulation time 488891911265 ps
CPU time 97.62 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:15:01 PM PDT 24
Peak memory 202140 kb
Host smart-218edc8c-9d9a-41bc-b68e-82ed65dbd757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838399112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2838399112
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1063752574
Short name T85
Test name
Test status
Simulation time 8092102368 ps
CPU time 6.04 seconds
Started Aug 16 05:12:30 PM PDT 24
Finished Aug 16 05:12:36 PM PDT 24
Peak memory 217512 kb
Host smart-cdc8d463-ed5b-41b7-8788-38296b777834
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063752574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1063752574
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3332586233
Short name T56
Test name
Test status
Simulation time 505609989796 ps
CPU time 439.34 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:20:33 PM PDT 24
Peak memory 202088 kb
Host smart-9f7a1874-ecbb-4b6d-b453-edf7fb25b6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332586233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3332586233
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3021734903
Short name T306
Test name
Test status
Simulation time 493815367064 ps
CPU time 139.64 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:15:49 PM PDT 24
Peak memory 202064 kb
Host smart-fc1550d4-5a34-4c41-8e16-3dc4add8965a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021734903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3021734903
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3568258681
Short name T249
Test name
Test status
Simulation time 498224564351 ps
CPU time 709.22 seconds
Started Aug 16 05:12:37 PM PDT 24
Finished Aug 16 05:24:26 PM PDT 24
Peak memory 202076 kb
Host smart-527ca661-69f7-4f0d-b0f5-94cb66525fec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568258681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3568258681
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1127696625
Short name T259
Test name
Test status
Simulation time 528515147832 ps
CPU time 314.95 seconds
Started Aug 16 05:14:07 PM PDT 24
Finished Aug 16 05:19:22 PM PDT 24
Peak memory 202012 kb
Host smart-bcbe1aef-ac67-49cc-8798-6dfcf7e0d1e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127696625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1127696625
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2591823329
Short name T127
Test name
Test status
Simulation time 2084252677 ps
CPU time 4.27 seconds
Started Aug 16 05:11:57 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 200912 kb
Host smart-6cb9a676-9084-476e-a46d-c0521d4870cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591823329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2591823329
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2473983533
Short name T47
Test name
Test status
Simulation time 110132576544 ps
CPU time 565.86 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:22:48 PM PDT 24
Peak memory 202392 kb
Host smart-cc89ab47-2b60-4e0f-ba93-f3b155bbc2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473983533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2473983533
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1672911402
Short name T302
Test name
Test status
Simulation time 477906354660 ps
CPU time 1089.76 seconds
Started Aug 16 05:14:24 PM PDT 24
Finished Aug 16 05:32:34 PM PDT 24
Peak memory 202144 kb
Host smart-97b54e0e-e6a1-483f-8359-0df3bfb69a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672911402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1672911402
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1150868280
Short name T269
Test name
Test status
Simulation time 177910161107 ps
CPU time 208.34 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:16:38 PM PDT 24
Peak memory 202068 kb
Host smart-3e7b281d-4541-40ea-b9d6-2cd5ce6c0955
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150868280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1150868280
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.203240080
Short name T180
Test name
Test status
Simulation time 498067954251 ps
CPU time 140.55 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:15:35 PM PDT 24
Peak memory 201996 kb
Host smart-8a10cb6e-4c2d-4793-a9bd-8808638907c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203240080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.203240080
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3148997052
Short name T219
Test name
Test status
Simulation time 492619966919 ps
CPU time 139.28 seconds
Started Aug 16 05:12:58 PM PDT 24
Finished Aug 16 05:15:17 PM PDT 24
Peak memory 202088 kb
Host smart-ac24da0f-a8d6-498b-8ff5-34d8e802b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148997052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3148997052
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3130561510
Short name T182
Test name
Test status
Simulation time 500463165213 ps
CPU time 262.58 seconds
Started Aug 16 05:12:30 PM PDT 24
Finished Aug 16 05:16:53 PM PDT 24
Peak memory 202196 kb
Host smart-1ffaa0ba-d599-4890-94fe-bdd2b9c06747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130561510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3130561510
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3677407388
Short name T327
Test name
Test status
Simulation time 548525648124 ps
CPU time 1250.87 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:34:05 PM PDT 24
Peak memory 202080 kb
Host smart-56dbca4e-7df9-4e7f-9798-a542bf6785d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677407388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3677407388
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1101633707
Short name T329
Test name
Test status
Simulation time 498647700278 ps
CPU time 470.8 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:21:03 PM PDT 24
Peak memory 202112 kb
Host smart-1a60f691-db2f-42b2-9998-ee7491301bf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101633707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1101633707
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1847967086
Short name T264
Test name
Test status
Simulation time 202118510638 ps
CPU time 240.09 seconds
Started Aug 16 05:15:02 PM PDT 24
Finished Aug 16 05:19:03 PM PDT 24
Peak memory 202108 kb
Host smart-91e3d6b3-c8f9-4984-88a1-8a59e2e02229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847967086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1847967086
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2465806806
Short name T298
Test name
Test status
Simulation time 166967867636 ps
CPU time 123.21 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:16:20 PM PDT 24
Peak memory 202064 kb
Host smart-6265a9a1-ebaf-4894-b4ce-ddb4044879aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465806806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2465806806
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1277188626
Short name T20
Test name
Test status
Simulation time 15071575161 ps
CPU time 19.48 seconds
Started Aug 16 05:15:04 PM PDT 24
Finished Aug 16 05:15:24 PM PDT 24
Peak memory 210640 kb
Host smart-49e3c34f-ffb2-43af-9097-af361207dbfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277188626 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1277188626
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.23558512
Short name T11
Test name
Test status
Simulation time 164229657770 ps
CPU time 93.57 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:14:49 PM PDT 24
Peak memory 202084 kb
Host smart-84f0ea54-5a2b-4511-9536-649935608ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23558512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.23558512
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.551876540
Short name T247
Test name
Test status
Simulation time 435828737981 ps
CPU time 989.37 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:29:54 PM PDT 24
Peak memory 202104 kb
Host smart-5158a799-9b62-44b9-b1e3-df09409e6c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551876540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
551876540
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2515211891
Short name T208
Test name
Test status
Simulation time 329492492984 ps
CPU time 127.53 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:16:17 PM PDT 24
Peak memory 202080 kb
Host smart-804e37ed-09f9-4139-b709-e869253c0476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515211891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2515211891
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1418958372
Short name T68
Test name
Test status
Simulation time 344452595 ps
CPU time 2.08 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:07 PM PDT 24
Peak memory 201200 kb
Host smart-863b0fa3-7239-4249-89b1-8031da088ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418958372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1418958372
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.707719172
Short name T256
Test name
Test status
Simulation time 498538897355 ps
CPU time 603.88 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:23:22 PM PDT 24
Peak memory 202076 kb
Host smart-a0a152da-caba-4e5a-b743-34ddcc635971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707719172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.707719172
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1423952187
Short name T148
Test name
Test status
Simulation time 348205435221 ps
CPU time 770.76 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:26:17 PM PDT 24
Peak memory 202092 kb
Host smart-bb99775a-4030-4456-8f9c-78d9fd91777a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423952187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1423952187
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1283814973
Short name T350
Test name
Test status
Simulation time 381500765787 ps
CPU time 870.41 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:28:11 PM PDT 24
Peak memory 202108 kb
Host smart-0e883195-3515-44bf-a5d7-5f9c1ac3937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283814973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1283814973
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1964110892
Short name T145
Test name
Test status
Simulation time 458120760582 ps
CPU time 1519.17 seconds
Started Aug 16 05:13:55 PM PDT 24
Finished Aug 16 05:39:14 PM PDT 24
Peak memory 210476 kb
Host smart-0fa61d21-0ec8-499f-bf5a-53595445728f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964110892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1964110892
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.467990709
Short name T289
Test name
Test status
Simulation time 6602016269 ps
CPU time 20.97 seconds
Started Aug 16 05:14:09 PM PDT 24
Finished Aug 16 05:14:30 PM PDT 24
Peak memory 210680 kb
Host smart-cf599ed3-dba5-4850-a0d3-0f277971d251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467990709 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.467990709
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.227539117
Short name T305
Test name
Test status
Simulation time 624763944838 ps
CPU time 1454.02 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:39:11 PM PDT 24
Peak memory 202072 kb
Host smart-b0169157-7247-4603-9ebd-703857dcb0dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227539117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.227539117
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2927766979
Short name T230
Test name
Test status
Simulation time 402901144627 ps
CPU time 992.51 seconds
Started Aug 16 05:15:25 PM PDT 24
Finished Aug 16 05:31:58 PM PDT 24
Peak memory 218668 kb
Host smart-6458d67a-64df-4696-a2eb-348779b774b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927766979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2927766979
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1087112789
Short name T343
Test name
Test status
Simulation time 331151602738 ps
CPU time 755.25 seconds
Started Aug 16 05:13:04 PM PDT 24
Finished Aug 16 05:25:39 PM PDT 24
Peak memory 202072 kb
Host smart-f39c0648-205b-4464-bea3-ea5cede8a1e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087112789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1087112789
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4164285411
Short name T301
Test name
Test status
Simulation time 164320688543 ps
CPU time 102.89 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:15:10 PM PDT 24
Peak memory 202072 kb
Host smart-948dd674-0698-4b89-8f47-a61f898285e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164285411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4164285411
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.991376747
Short name T311
Test name
Test status
Simulation time 560728759431 ps
CPU time 432.71 seconds
Started Aug 16 05:13:54 PM PDT 24
Finished Aug 16 05:21:07 PM PDT 24
Peak memory 202124 kb
Host smart-b45a53b1-a5a5-4d47-bfc2-6a1a560534d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991376747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.991376747
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4094026638
Short name T207
Test name
Test status
Simulation time 388068899548 ps
CPU time 925.16 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:29:43 PM PDT 24
Peak memory 202100 kb
Host smart-9f635910-80cd-4d91-b7ab-dfb32fe2de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094026638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4094026638
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1400951997
Short name T236
Test name
Test status
Simulation time 521439645139 ps
CPU time 470.23 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:22:34 PM PDT 24
Peak memory 202080 kb
Host smart-f23d2ef5-0122-46b5-9df0-e3c2a46a2dbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400951997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1400951997
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1506451587
Short name T276
Test name
Test status
Simulation time 427606749473 ps
CPU time 494.76 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:23:11 PM PDT 24
Peak memory 202116 kb
Host smart-2ffe9a68-1256-4b5b-bba6-194737789937
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506451587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1506451587
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1729248617
Short name T310
Test name
Test status
Simulation time 576344775113 ps
CPU time 1369.18 seconds
Started Aug 16 05:15:02 PM PDT 24
Finished Aug 16 05:37:52 PM PDT 24
Peak memory 202068 kb
Host smart-5cbf8072-5efb-4e31-a08a-c9b9ee448621
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729248617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1729248617
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1543318846
Short name T353
Test name
Test status
Simulation time 8262673962 ps
CPU time 20.4 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 201188 kb
Host smart-6a79c2ce-820d-4cdb-86f6-458a572e1037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543318846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1543318846
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3978612625
Short name T39
Test name
Test status
Simulation time 485985724576 ps
CPU time 1043.53 seconds
Started Aug 16 05:12:36 PM PDT 24
Finished Aug 16 05:30:00 PM PDT 24
Peak memory 202112 kb
Host smart-efd39785-8d4f-4dd2-96aa-93564d2bbd9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978612625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3978612625
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.616999422
Short name T766
Test name
Test status
Simulation time 256757941324 ps
CPU time 316.42 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:18:29 PM PDT 24
Peak memory 210524 kb
Host smart-41265fca-d9d9-458b-85d4-c5e7001c0082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616999422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
616999422
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3592162200
Short name T321
Test name
Test status
Simulation time 204261666327 ps
CPU time 214.72 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:19:05 PM PDT 24
Peak memory 202160 kb
Host smart-96c49ee6-7b4d-4669-9c06-eac836e61532
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592162200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3592162200
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.917352312
Short name T206
Test name
Test status
Simulation time 138401944233 ps
CPU time 660.11 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:24:30 PM PDT 24
Peak memory 202340 kb
Host smart-80f2a5b6-1482-408e-852a-c9e03a07a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917352312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.917352312
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.844169912
Short name T271
Test name
Test status
Simulation time 160466783199 ps
CPU time 87.22 seconds
Started Aug 16 05:13:41 PM PDT 24
Finished Aug 16 05:15:08 PM PDT 24
Peak memory 202060 kb
Host smart-9f6ccc9e-bcbe-4b34-a612-e0f77448c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844169912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.844169912
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.797647424
Short name T356
Test name
Test status
Simulation time 96107320333 ps
CPU time 441.9 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:21:27 PM PDT 24
Peak memory 202388 kb
Host smart-342cdc14-f5fe-4e32-b035-e7dd8b1e669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797647424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.797647424
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4178296933
Short name T317
Test name
Test status
Simulation time 353881184186 ps
CPU time 738.56 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:26:37 PM PDT 24
Peak memory 202068 kb
Host smart-15c9aa21-5e4a-4103-9804-4edbddc35758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178296933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4178296933
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.956405009
Short name T721
Test name
Test status
Simulation time 101167389577 ps
CPU time 360.25 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:20:18 PM PDT 24
Peak memory 202368 kb
Host smart-7d1314b2-bd0c-47ed-8848-69b4c6dd717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956405009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.956405009
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1880341164
Short name T140
Test name
Test status
Simulation time 502906524656 ps
CPU time 816.09 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:28:33 PM PDT 24
Peak memory 202072 kb
Host smart-13771d1b-50d1-4eb2-a1e1-364ead3d78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880341164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1880341164
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1597855512
Short name T295
Test name
Test status
Simulation time 338055382737 ps
CPU time 362.7 seconds
Started Aug 16 05:15:16 PM PDT 24
Finished Aug 16 05:21:18 PM PDT 24
Peak memory 202100 kb
Host smart-3f49aea8-e016-4073-b091-f21470dfeb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597855512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1597855512
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2641074653
Short name T892
Test name
Test status
Simulation time 3893305267 ps
CPU time 3.66 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 201148 kb
Host smart-e2c4f222-fbfd-429e-9132-f1480fa69254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641074653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2641074653
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3489002969
Short name T25
Test name
Test status
Simulation time 12972520269 ps
CPU time 4.28 seconds
Started Aug 16 05:12:36 PM PDT 24
Finished Aug 16 05:12:41 PM PDT 24
Peak memory 210468 kb
Host smart-fb5cde11-c4fe-4e13-8378-c2c2f5f6890c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489002969 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3489002969
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2238467444
Short name T231
Test name
Test status
Simulation time 327657700414 ps
CPU time 367.79 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:19:23 PM PDT 24
Peak memory 202052 kb
Host smart-7dc1ec4e-07bf-42db-9489-a6e1988db417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238467444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2238467444
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3500256928
Short name T617
Test name
Test status
Simulation time 312254603063 ps
CPU time 717.19 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:25:13 PM PDT 24
Peak memory 210536 kb
Host smart-48577bf4-21f2-4800-9b83-3187b849702e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500256928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3500256928
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1708460654
Short name T309
Test name
Test status
Simulation time 193664611440 ps
CPU time 118.09 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:15:18 PM PDT 24
Peak memory 202076 kb
Host smart-817c974c-ec1b-4bef-9014-93fff06c8daa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708460654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1708460654
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4023488242
Short name T304
Test name
Test status
Simulation time 255458334635 ps
CPU time 418.5 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:20:27 PM PDT 24
Peak memory 210540 kb
Host smart-5a554246-4e04-4a2a-9db3-4a2797777831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023488242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4023488242
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2273048454
Short name T338
Test name
Test status
Simulation time 171186254636 ps
CPU time 306.49 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:18:28 PM PDT 24
Peak memory 202108 kb
Host smart-8d4b8780-578f-4683-8e3b-43cd608d1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273048454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2273048454
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3965367588
Short name T203
Test name
Test status
Simulation time 113668323209 ps
CPU time 395.51 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:20:00 PM PDT 24
Peak memory 202396 kb
Host smart-9cf4c486-8ef6-4af2-be9f-eed59c1a7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965367588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3965367588
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.721506742
Short name T666
Test name
Test status
Simulation time 94493853657 ps
CPU time 545.35 seconds
Started Aug 16 05:13:41 PM PDT 24
Finished Aug 16 05:22:47 PM PDT 24
Peak memory 202376 kb
Host smart-a97b55c0-700a-4fa4-a1a3-990e05c5b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721506742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.721506742
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3922803028
Short name T296
Test name
Test status
Simulation time 526541357249 ps
CPU time 278.87 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:18:26 PM PDT 24
Peak memory 202148 kb
Host smart-3ee77ad4-21e4-49b4-a184-ec9196cd06d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922803028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3922803028
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.483894078
Short name T300
Test name
Test status
Simulation time 341779155182 ps
CPU time 199.92 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:17:36 PM PDT 24
Peak memory 202076 kb
Host smart-7b6f9c1d-cff3-421c-aff7-9ecc1bce728b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483894078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
483894078
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3165038214
Short name T263
Test name
Test status
Simulation time 358490870480 ps
CPU time 143.53 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:17:28 PM PDT 24
Peak memory 202092 kb
Host smart-032f01f0-2127-456e-a009-7005f0094548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165038214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3165038214
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1515502828
Short name T201
Test name
Test status
Simulation time 90237825841 ps
CPU time 344.33 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:20:59 PM PDT 24
Peak memory 202384 kb
Host smart-76000588-decb-4e47-8af8-8921d74adfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515502828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1515502828
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2444203261
Short name T345
Test name
Test status
Simulation time 4842227213 ps
CPU time 6.69 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:15:30 PM PDT 24
Peak memory 202272 kb
Host smart-3529a86a-db23-4386-9ec6-5f0156e8e310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444203261 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2444203261
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.300062175
Short name T242
Test name
Test status
Simulation time 176331932884 ps
CPU time 101.75 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:14:54 PM PDT 24
Peak memory 202068 kb
Host smart-b3ca7969-77fa-4059-a230-cae8d7c22dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300062175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.300062175
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2856628755
Short name T278
Test name
Test status
Simulation time 360703816698 ps
CPU time 876.89 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:27:39 PM PDT 24
Peak memory 202108 kb
Host smart-429c55d5-8f64-4f07-b305-0fb36eefc67e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856628755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2856628755
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1335800978
Short name T874
Test name
Test status
Simulation time 1145118454 ps
CPU time 4.57 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:07 PM PDT 24
Peak memory 201016 kb
Host smart-ac967934-6cd8-43ef-848d-cb18216b0e6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335800978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1335800978
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1861404423
Short name T876
Test name
Test status
Simulation time 1149342317 ps
CPU time 1.22 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 200896 kb
Host smart-32dba3b9-0487-4656-b2f3-7b36f40c2337
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861404423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1861404423
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1518786446
Short name T864
Test name
Test status
Simulation time 355150075 ps
CPU time 1.25 seconds
Started Aug 16 05:11:51 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 200884 kb
Host smart-a3c8f0c4-c11c-4eba-ae04-d9a2bb90ba7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518786446 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1518786446
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1965438901
Short name T128
Test name
Test status
Simulation time 347555487 ps
CPU time 0.86 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 200880 kb
Host smart-e8c1e6ca-d6fe-4bb1-a9ff-28059779bbad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965438901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1965438901
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3825721260
Short name T801
Test name
Test status
Simulation time 450145516 ps
CPU time 1.73 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200844 kb
Host smart-60002bfd-cb45-4c07-9ece-038df6587da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825721260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3825721260
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.535624346
Short name T821
Test name
Test status
Simulation time 2285244316 ps
CPU time 1.8 seconds
Started Aug 16 05:11:43 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 200988 kb
Host smart-2d2f39fa-1466-4dfa-9c01-6bba2b02f81e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535624346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.535624346
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2489201635
Short name T910
Test name
Test status
Simulation time 707700183 ps
CPU time 2.98 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 201336 kb
Host smart-043dc23e-5a0d-4dc1-b08e-8346fa8e63cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489201635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2489201635
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2594250601
Short name T59
Test name
Test status
Simulation time 4924379576 ps
CPU time 4.19 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:48 PM PDT 24
Peak memory 201176 kb
Host smart-65957867-d3d0-4897-9922-16f48d44ae87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594250601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2594250601
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2307158239
Short name T904
Test name
Test status
Simulation time 831340996 ps
CPU time 4.02 seconds
Started Aug 16 05:11:56 PM PDT 24
Finished Aug 16 05:12:00 PM PDT 24
Peak memory 201072 kb
Host smart-38a542aa-19d5-488a-9c56-1bda8d7eec54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307158239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2307158239
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.229955150
Short name T121
Test name
Test status
Simulation time 1177420556 ps
CPU time 5.58 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:46 PM PDT 24
Peak memory 201096 kb
Host smart-771298db-944f-4295-b976-2e82d91717ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229955150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.229955150
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1576833772
Short name T118
Test name
Test status
Simulation time 1134915116 ps
CPU time 2.15 seconds
Started Aug 16 05:11:45 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 200896 kb
Host smart-da1fbc22-e39a-446f-a12a-ff17670166c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576833772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1576833772
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4136127490
Short name T829
Test name
Test status
Simulation time 610490602 ps
CPU time 1.16 seconds
Started Aug 16 05:12:03 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 200924 kb
Host smart-bc568671-98a6-4cac-9dfe-4b8dba12265a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136127490 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4136127490
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.74892665
Short name T846
Test name
Test status
Simulation time 491647895 ps
CPU time 1.92 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 200892 kb
Host smart-38b1e4fb-5547-4306-ae5b-7ecc32451f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74892665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.74892665
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3980529523
Short name T834
Test name
Test status
Simulation time 338175664 ps
CPU time 0.82 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:01 PM PDT 24
Peak memory 200816 kb
Host smart-8926a5e6-bae5-490a-921d-e02e42c8567c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980529523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3980529523
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3117252716
Short name T869
Test name
Test status
Simulation time 2269821156 ps
CPU time 2.93 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200956 kb
Host smart-d3a079f2-64b0-42da-bf78-077fdf0c5d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117252716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3117252716
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2150507952
Short name T81
Test name
Test status
Simulation time 419614126 ps
CPU time 1.79 seconds
Started Aug 16 05:11:51 PM PDT 24
Finished Aug 16 05:11:53 PM PDT 24
Peak memory 201108 kb
Host smart-16b5448b-ac34-4a63-81ea-3f4a2ebfd11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150507952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2150507952
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3980424135
Short name T841
Test name
Test status
Simulation time 980575619 ps
CPU time 1.1 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 201012 kb
Host smart-6d30d865-b397-408a-8261-9e617fcaaf9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980424135 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3980424135
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3079638923
Short name T129
Test name
Test status
Simulation time 339969298 ps
CPU time 1.25 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200904 kb
Host smart-1c6f0ef9-a54d-4b84-96dc-3501c0c99727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079638923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3079638923
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3634639987
Short name T842
Test name
Test status
Simulation time 369403319 ps
CPU time 1.09 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 200832 kb
Host smart-b3e1b168-9415-40cf-a6fb-59e7f0297bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634639987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3634639987
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3654198781
Short name T850
Test name
Test status
Simulation time 507945216 ps
CPU time 1.79 seconds
Started Aug 16 05:12:20 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 201056 kb
Host smart-04933a9b-39b6-42de-8760-93aa5b60a681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654198781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3654198781
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1447100547
Short name T83
Test name
Test status
Simulation time 8270237754 ps
CPU time 9.86 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 201148 kb
Host smart-f07c64fc-ddb6-4b65-85bc-0a3f9aba0458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447100547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1447100547
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2546073035
Short name T82
Test name
Test status
Simulation time 382236593 ps
CPU time 1.35 seconds
Started Aug 16 05:12:15 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200976 kb
Host smart-66a133e3-204d-4eb6-832a-fc4e1924bebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546073035 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2546073035
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1877252573
Short name T906
Test name
Test status
Simulation time 522141664 ps
CPU time 1.97 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 200904 kb
Host smart-e65f5434-aafd-462c-b4e7-807b1c7c0603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877252573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1877252573
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3057102128
Short name T866
Test name
Test status
Simulation time 416920654 ps
CPU time 1.06 seconds
Started Aug 16 05:12:24 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 200808 kb
Host smart-dcbc9dbb-8da6-4f3c-b452-0383145119a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057102128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3057102128
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3481887696
Short name T894
Test name
Test status
Simulation time 2927982240 ps
CPU time 1.72 seconds
Started Aug 16 05:12:10 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 201116 kb
Host smart-cbcbb66e-50d3-4511-9e4b-efa83a49de4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481887696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3481887696
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2682329488
Short name T79
Test name
Test status
Simulation time 8602367497 ps
CPU time 7.35 seconds
Started Aug 16 05:12:03 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 201136 kb
Host smart-a7731677-b801-4e78-a3a3-85c30feb81c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682329488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2682329488
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.197344184
Short name T828
Test name
Test status
Simulation time 391131610 ps
CPU time 1.09 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 200984 kb
Host smart-a3a6b10e-170b-4f06-9ebd-1ecdf399042f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197344184 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.197344184
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.718212161
Short name T124
Test name
Test status
Simulation time 543899605 ps
CPU time 2.05 seconds
Started Aug 16 05:12:16 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 200916 kb
Host smart-05ec9179-c113-40fe-a91d-7f6abf0c8159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718212161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.718212161
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.365172075
Short name T901
Test name
Test status
Simulation time 516309037 ps
CPU time 0.79 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 200828 kb
Host smart-8385721f-517b-43d6-a800-144b5faa75d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365172075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.365172075
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1212075207
Short name T812
Test name
Test status
Simulation time 4151868466 ps
CPU time 10.46 seconds
Started Aug 16 05:12:10 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 201108 kb
Host smart-e394b44f-f41a-47f0-8af8-7c066b02d318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212075207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1212075207
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.678683397
Short name T859
Test name
Test status
Simulation time 878673006 ps
CPU time 2.23 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:06 PM PDT 24
Peak memory 201160 kb
Host smart-6ab865a7-57f5-416f-8c4e-8680d30e2d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678683397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.678683397
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2065428061
Short name T880
Test name
Test status
Simulation time 603304446 ps
CPU time 2.51 seconds
Started Aug 16 05:12:13 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 200996 kb
Host smart-bbb554e0-3bbb-4c62-9ad0-2ee6d2f9a5a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065428061 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2065428061
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2845372596
Short name T895
Test name
Test status
Simulation time 409993868 ps
CPU time 1.48 seconds
Started Aug 16 05:12:24 PM PDT 24
Finished Aug 16 05:12:26 PM PDT 24
Peak memory 200880 kb
Host smart-9b34d81a-7c1e-4d8c-917d-26b298f1c1eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845372596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2845372596
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2261663469
Short name T875
Test name
Test status
Simulation time 387830667 ps
CPU time 1.57 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:06 PM PDT 24
Peak memory 200840 kb
Host smart-fb6b5b65-0f32-48a9-ae48-e776a72c9a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261663469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2261663469
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1998779017
Short name T835
Test name
Test status
Simulation time 2336045709 ps
CPU time 5.09 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 200956 kb
Host smart-b3ede347-1370-408d-a572-91159b4a8ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998779017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1998779017
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2410687831
Short name T870
Test name
Test status
Simulation time 398276876 ps
CPU time 1.74 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 201136 kb
Host smart-bb2a2f0f-de73-43fd-9a01-c2f6f2a965f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410687831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2410687831
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3268289857
Short name T352
Test name
Test status
Simulation time 8422998979 ps
CPU time 15.77 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:26 PM PDT 24
Peak memory 201164 kb
Host smart-f18d5c22-e834-4f6b-8663-63a8f7e2f8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268289857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3268289857
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1609081354
Short name T863
Test name
Test status
Simulation time 441166002 ps
CPU time 1.5 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200988 kb
Host smart-e6dc773b-f096-490d-981a-141253684416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609081354 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1609081354
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1552397097
Short name T832
Test name
Test status
Simulation time 428876196 ps
CPU time 1.78 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:06 PM PDT 24
Peak memory 200908 kb
Host smart-90694e67-2106-4bf2-a3c4-baa8a25aaf69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552397097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1552397097
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1558336410
Short name T854
Test name
Test status
Simulation time 470099362 ps
CPU time 1.62 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:06 PM PDT 24
Peak memory 200848 kb
Host smart-0881a3fc-ca53-4459-96bc-d5f7f75126fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558336410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1558336410
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3614312826
Short name T825
Test name
Test status
Simulation time 4426978163 ps
CPU time 16.58 seconds
Started Aug 16 05:12:23 PM PDT 24
Finished Aug 16 05:12:40 PM PDT 24
Peak memory 201144 kb
Host smart-39ddd415-213a-4330-9857-f980ffe03b74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614312826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3614312826
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3316497610
Short name T920
Test name
Test status
Simulation time 4359951636 ps
CPU time 3.91 seconds
Started Aug 16 05:12:07 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 201164 kb
Host smart-ca53348f-9786-453a-8dc8-2a44e6bc731b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316497610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3316497610
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3285388508
Short name T845
Test name
Test status
Simulation time 370186645 ps
CPU time 1.44 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:21 PM PDT 24
Peak memory 200892 kb
Host smart-1cbcb5dc-b559-4b47-80e0-4a46d5096595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285388508 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3285388508
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1422350114
Short name T915
Test name
Test status
Simulation time 330147682 ps
CPU time 0.89 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 201092 kb
Host smart-a5ec7d10-ca26-4be5-87f3-581b3695fffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422350114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1422350114
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3283819164
Short name T817
Test name
Test status
Simulation time 417080605 ps
CPU time 1.11 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200800 kb
Host smart-5f5de3e1-7c37-4d98-810e-1744bee3d2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283819164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3283819164
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.379084624
Short name T126
Test name
Test status
Simulation time 2280464556 ps
CPU time 2.26 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 200968 kb
Host smart-ac920f39-ad23-42f8-92ca-55edfc744c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379084624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.379084624
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.665967996
Short name T884
Test name
Test status
Simulation time 1026165137 ps
CPU time 1.66 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:23 PM PDT 24
Peak memory 201180 kb
Host smart-c2669de1-f64a-4289-a038-f8f25eda5202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665967996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.665967996
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.514350060
Short name T78
Test name
Test status
Simulation time 10472592587 ps
CPU time 3.81 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 201124 kb
Host smart-23acdaac-396e-41f9-b565-5f1db3fe4f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514350060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.514350060
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.15991900
Short name T890
Test name
Test status
Simulation time 395451469 ps
CPU time 1.83 seconds
Started Aug 16 05:12:07 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 200984 kb
Host smart-49ea3606-899e-4918-a67e-7f8cd1991d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15991900 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.15991900
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1882387973
Short name T872
Test name
Test status
Simulation time 528450526 ps
CPU time 1.26 seconds
Started Aug 16 05:12:15 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200892 kb
Host smart-1d62ce81-706f-42c8-a921-a4e72cbcb461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882387973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1882387973
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1895785510
Short name T806
Test name
Test status
Simulation time 525688181 ps
CPU time 1.79 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 200844 kb
Host smart-0a2044f2-e9b2-4998-a249-0f4b3ec27557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895785510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1895785510
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2867710534
Short name T865
Test name
Test status
Simulation time 4107159079 ps
CPU time 16.31 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:27 PM PDT 24
Peak memory 201156 kb
Host smart-6eb938a2-3fd3-471c-b00f-740771ec1675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867710534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2867710534
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2077056881
Short name T70
Test name
Test status
Simulation time 426311811 ps
CPU time 3.3 seconds
Started Aug 16 05:12:17 PM PDT 24
Finished Aug 16 05:12:21 PM PDT 24
Peak memory 201052 kb
Host smart-2213a6b2-6d2b-4c7e-82d6-79c750a77f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077056881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2077056881
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1372866553
Short name T893
Test name
Test status
Simulation time 4636369533 ps
CPU time 3.53 seconds
Started Aug 16 05:12:20 PM PDT 24
Finished Aug 16 05:12:24 PM PDT 24
Peak memory 201116 kb
Host smart-cf6f05b7-ee35-4ba4-bd02-782a06e3e342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372866553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1372866553
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1994994034
Short name T77
Test name
Test status
Simulation time 461807979 ps
CPU time 1.27 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 201028 kb
Host smart-ce7032dd-3e17-4e95-bd9d-f02ffc10be8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994994034 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1994994034
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3034164235
Short name T123
Test name
Test status
Simulation time 359252426 ps
CPU time 0.9 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:05 PM PDT 24
Peak memory 200900 kb
Host smart-9ef52813-bda4-4238-be6d-f963aeb0c85a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034164235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3034164235
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3283156405
Short name T916
Test name
Test status
Simulation time 320993437 ps
CPU time 1.36 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200820 kb
Host smart-927453d3-2e80-48b5-a7e0-d35b6638c8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283156405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3283156405
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1258782445
Short name T905
Test name
Test status
Simulation time 3974572252 ps
CPU time 2.33 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 201132 kb
Host smart-f9db5171-19d5-43fd-ac71-e496ea4d2346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258782445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1258782445
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1589426255
Short name T882
Test name
Test status
Simulation time 403450695 ps
CPU time 2.12 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:21 PM PDT 24
Peak memory 201248 kb
Host smart-ea206eb5-fe2b-421a-8943-ec3d20fe25ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589426255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1589426255
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2225852752
Short name T63
Test name
Test status
Simulation time 4494990883 ps
CPU time 4.54 seconds
Started Aug 16 05:12:20 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 201108 kb
Host smart-9d911868-072e-4f7c-aeae-2ee14e1eb14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225852752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2225852752
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3657608890
Short name T830
Test name
Test status
Simulation time 506560685 ps
CPU time 1.22 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200972 kb
Host smart-6806651a-175e-48fa-a88c-8016d42e6df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657608890 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3657608890
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3895490039
Short name T116
Test name
Test status
Simulation time 557911833 ps
CPU time 0.99 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 200916 kb
Host smart-385aec80-cd02-4dde-b80e-b5daab7cd950
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895490039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3895490039
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2174208911
Short name T811
Test name
Test status
Simulation time 510138175 ps
CPU time 1.64 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 200800 kb
Host smart-2ec46e7a-4c98-4642-8fc7-1fa4b7cbfd2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174208911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2174208911
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2667636103
Short name T898
Test name
Test status
Simulation time 2151479415 ps
CPU time 8.45 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:18 PM PDT 24
Peak memory 200988 kb
Host smart-b33b6d36-577f-47f3-a309-eec0df0f3aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667636103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2667636103
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1143762858
Short name T849
Test name
Test status
Simulation time 706325628 ps
CPU time 1.84 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:23 PM PDT 24
Peak memory 201344 kb
Host smart-52accde3-b2ce-46e2-a2c3-8a20d9527abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143762858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1143762858
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2101169355
Short name T58
Test name
Test status
Simulation time 8058569594 ps
CPU time 20.45 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:32 PM PDT 24
Peak memory 201124 kb
Host smart-7a40c682-feb0-4359-87f9-f27432c58a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101169355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2101169355
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3981390877
Short name T879
Test name
Test status
Simulation time 551902040 ps
CPU time 1.19 seconds
Started Aug 16 05:12:10 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 200936 kb
Host smart-7b6a6391-b8df-4581-bed3-bf9cfdd66c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981390877 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3981390877
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1874487933
Short name T848
Test name
Test status
Simulation time 332272336 ps
CPU time 1.27 seconds
Started Aug 16 05:12:14 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 200988 kb
Host smart-2a0b23ce-cde9-4e1c-b6fd-3a203cc7ab81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874487933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1874487933
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1074926172
Short name T839
Test name
Test status
Simulation time 400901351 ps
CPU time 1.12 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 200880 kb
Host smart-c4f194b1-6718-4ee8-9442-3c00d535f40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074926172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1074926172
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.486625688
Short name T52
Test name
Test status
Simulation time 5142612978 ps
CPU time 7.78 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:26 PM PDT 24
Peak memory 201076 kb
Host smart-a72fedd9-bb3f-40a3-a6fc-1a5666399d3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486625688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.486625688
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3040929783
Short name T883
Test name
Test status
Simulation time 513541701 ps
CPU time 2.42 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 201140 kb
Host smart-de21055f-5b43-481d-962a-be7f105e5d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040929783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3040929783
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.872113413
Short name T907
Test name
Test status
Simulation time 8416608516 ps
CPU time 11.14 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:21 PM PDT 24
Peak memory 201084 kb
Host smart-4a6f5e93-f8df-44a8-99cd-51d1364673ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872113413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.872113413
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3863175032
Short name T903
Test name
Test status
Simulation time 1113135829 ps
CPU time 4.73 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:54 PM PDT 24
Peak memory 201060 kb
Host smart-ee39567d-1ab0-49f8-b355-a83a83e5df5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863175032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3863175032
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1541943299
Short name T53
Test name
Test status
Simulation time 45008014062 ps
CPU time 99.81 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:13:40 PM PDT 24
Peak memory 201116 kb
Host smart-930cc6eb-2f75-441b-8905-6ca27bc7a454
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541943299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1541943299
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3878366406
Short name T837
Test name
Test status
Simulation time 708477973 ps
CPU time 0.91 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 200916 kb
Host smart-e70f52a6-ad87-44d6-a4ba-e4327d162c0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878366406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3878366406
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1274544079
Short name T76
Test name
Test status
Simulation time 555627337 ps
CPU time 2.21 seconds
Started Aug 16 05:11:48 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 200988 kb
Host smart-c837a94a-5f2e-4da9-b8a1-3e59a80274ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274544079 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1274544079
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2666710095
Short name T115
Test name
Test status
Simulation time 511741200 ps
CPU time 1 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 200888 kb
Host smart-4c8c20a2-18e4-471a-87cf-fcaee55ecd33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666710095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2666710095
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2596098686
Short name T889
Test name
Test status
Simulation time 300305075 ps
CPU time 1.28 seconds
Started Aug 16 05:12:16 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200792 kb
Host smart-c921c4c2-0363-4243-a8bc-54d4caf4adfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596098686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2596098686
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3871286721
Short name T911
Test name
Test status
Simulation time 2204348208 ps
CPU time 1.68 seconds
Started Aug 16 05:11:53 PM PDT 24
Finished Aug 16 05:11:55 PM PDT 24
Peak memory 200980 kb
Host smart-4e646372-9c94-467d-9550-a64d974d8aba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871286721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3871286721
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3147722430
Short name T873
Test name
Test status
Simulation time 325873167 ps
CPU time 1.93 seconds
Started Aug 16 05:11:45 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 201068 kb
Host smart-295acc23-c595-47d9-9852-87d710068865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147722430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3147722430
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3784907935
Short name T354
Test name
Test status
Simulation time 4114611155 ps
CPU time 4.19 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 201164 kb
Host smart-14cf4996-d950-4db6-a84b-f6bd8f4c159e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784907935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3784907935
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1565384951
Short name T912
Test name
Test status
Simulation time 369686428 ps
CPU time 0.91 seconds
Started Aug 16 05:12:10 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 200824 kb
Host smart-21d00918-beeb-4a7d-b0da-0b41f7a36e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565384951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1565384951
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.352988763
Short name T824
Test name
Test status
Simulation time 492615472 ps
CPU time 1.78 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200832 kb
Host smart-a669ba92-9c60-43b7-8174-5ccd13851da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352988763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.352988763
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.35362090
Short name T855
Test name
Test status
Simulation time 344438954 ps
CPU time 1.49 seconds
Started Aug 16 05:12:07 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200780 kb
Host smart-dbb5223d-8465-4548-9ef3-83418224966a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.35362090
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4283569233
Short name T897
Test name
Test status
Simulation time 512068231 ps
CPU time 0.97 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 200800 kb
Host smart-6bb59874-31dc-4bbc-a7d1-44d5074d2582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283569233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4283569233
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2043028876
Short name T809
Test name
Test status
Simulation time 448276357 ps
CPU time 1.64 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 200840 kb
Host smart-f96d7b7f-2d03-4452-8d11-038b56f6b344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043028876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2043028876
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1728406345
Short name T888
Test name
Test status
Simulation time 394506351 ps
CPU time 1.59 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200788 kb
Host smart-a9bfeff3-833f-4817-8f0b-00a253ba0a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728406345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1728406345
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2986835242
Short name T857
Test name
Test status
Simulation time 469541825 ps
CPU time 1.1 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 200820 kb
Host smart-c50d8df1-5873-492b-ba8c-16952768884b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986835242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2986835242
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1476013952
Short name T807
Test name
Test status
Simulation time 370210181 ps
CPU time 1.5 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 200800 kb
Host smart-7009fc45-da39-4085-8182-a5d379012589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476013952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1476013952
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3808504178
Short name T816
Test name
Test status
Simulation time 483534229 ps
CPU time 0.83 seconds
Started Aug 16 05:12:03 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 200824 kb
Host smart-cfd2af39-538c-4a8e-ad45-ea9243cec17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808504178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3808504178
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1441678961
Short name T862
Test name
Test status
Simulation time 557582149 ps
CPU time 0.99 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200824 kb
Host smart-97c9fed5-122b-458e-a1ba-da38f7cd8668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441678961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1441678961
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3785441673
Short name T838
Test name
Test status
Simulation time 797788793 ps
CPU time 3.82 seconds
Started Aug 16 05:11:58 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 201032 kb
Host smart-839d605a-6aa6-4193-884f-42d0eba027e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785441673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3785441673
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3293017824
Short name T823
Test name
Test status
Simulation time 26152486663 ps
CPU time 18.56 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:24 PM PDT 24
Peak memory 201116 kb
Host smart-f49829fe-99d2-4504-8a23-038574029f68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293017824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3293017824
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3887753231
Short name T120
Test name
Test status
Simulation time 1199868790 ps
CPU time 1 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:50 PM PDT 24
Peak memory 200940 kb
Host smart-8094f60c-1510-49a9-869a-d3f3cb107d87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887753231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3887753231
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3798019378
Short name T844
Test name
Test status
Simulation time 422933647 ps
CPU time 1.31 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:07 PM PDT 24
Peak memory 200976 kb
Host smart-e873e5f0-bfc2-43ed-9241-7e2b73039564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798019378 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3798019378
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3159150362
Short name T909
Test name
Test status
Simulation time 373378395 ps
CPU time 1.59 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:07 PM PDT 24
Peak memory 200880 kb
Host smart-c1add6ba-994c-486e-9c81-3693ff7ee5be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159150362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3159150362
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2334872667
Short name T808
Test name
Test status
Simulation time 600559185 ps
CPU time 0.76 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 200856 kb
Host smart-6de4278a-6943-4314-bba4-81777868eb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334872667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2334872667
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2983763567
Short name T858
Test name
Test status
Simulation time 4383407299 ps
CPU time 10.86 seconds
Started Aug 16 05:11:59 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 201168 kb
Host smart-7a219e41-2a07-4729-85da-61dfc6dc985f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983763567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2983763567
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2663949084
Short name T75
Test name
Test status
Simulation time 541263440 ps
CPU time 2.59 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 201148 kb
Host smart-2f89367d-f969-4d60-ae73-b8082fa17ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663949084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2663949084
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.298979673
Short name T831
Test name
Test status
Simulation time 4153277874 ps
CPU time 11.63 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:18 PM PDT 24
Peak memory 201156 kb
Host smart-e89eb4f5-2427-4e8c-bf20-05112d3cc215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298979673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.298979673
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2654073760
Short name T820
Test name
Test status
Simulation time 372996315 ps
CPU time 0.77 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200800 kb
Host smart-70c765dd-9bbb-4627-94b5-61781869aa31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654073760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2654073760
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2168976052
Short name T819
Test name
Test status
Simulation time 508791887 ps
CPU time 0.93 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 201020 kb
Host smart-ce4c956a-a9b4-44cb-8889-f8a5ee50bc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168976052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2168976052
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1612367411
Short name T868
Test name
Test status
Simulation time 446357480 ps
CPU time 0.89 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200924 kb
Host smart-075b284d-c665-4dae-853b-d1cdfd36d424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612367411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1612367411
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1513233408
Short name T860
Test name
Test status
Simulation time 357899616 ps
CPU time 1.37 seconds
Started Aug 16 05:12:16 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200816 kb
Host smart-7d24cc98-ae8f-42c4-bde7-ae0ce6573290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513233408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1513233408
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2342752141
Short name T900
Test name
Test status
Simulation time 364231961 ps
CPU time 1.44 seconds
Started Aug 16 05:12:22 PM PDT 24
Finished Aug 16 05:12:24 PM PDT 24
Peak memory 200808 kb
Host smart-723b7623-dc7f-4c98-adb9-de5bec2f2825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342752141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2342752141
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2076861378
Short name T914
Test name
Test status
Simulation time 426028923 ps
CPU time 1.62 seconds
Started Aug 16 05:12:20 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 200804 kb
Host smart-73dae592-736e-43d4-8c39-e2a856a4b0d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076861378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2076861378
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3372027949
Short name T843
Test name
Test status
Simulation time 289769586 ps
CPU time 1.03 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 200840 kb
Host smart-f8e972f6-d359-4dee-81f0-5e5d68081be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372027949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3372027949
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3062202639
Short name T810
Test name
Test status
Simulation time 433425442 ps
CPU time 1.13 seconds
Started Aug 16 05:12:22 PM PDT 24
Finished Aug 16 05:12:23 PM PDT 24
Peak memory 200728 kb
Host smart-b01fe2ae-6129-4aba-ad73-586bd22fed7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062202639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3062202639
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.295375993
Short name T891
Test name
Test status
Simulation time 320877281 ps
CPU time 1.31 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200836 kb
Host smart-626b8c88-f885-49e0-9a68-50df86ee11ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295375993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.295375993
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3546418334
Short name T918
Test name
Test status
Simulation time 548261611 ps
CPU time 0.94 seconds
Started Aug 16 05:12:13 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 200856 kb
Host smart-d99031fc-58cd-46ef-b222-4314a27ad51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546418334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3546418334
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4084912191
Short name T125
Test name
Test status
Simulation time 364787913 ps
CPU time 2.25 seconds
Started Aug 16 05:11:58 PM PDT 24
Finished Aug 16 05:12:01 PM PDT 24
Peak memory 201064 kb
Host smart-30d01004-72b5-48a7-a1a3-3c821bf2c645
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084912191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4084912191
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2941586926
Short name T919
Test name
Test status
Simulation time 3952713939 ps
CPU time 7.67 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:12 PM PDT 24
Peak memory 201128 kb
Host smart-05af0a70-ed0b-4b53-a5fc-d6f6d12cf01f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941586926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2941586926
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2814150692
Short name T899
Test name
Test status
Simulation time 871788046 ps
CPU time 1.19 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 200908 kb
Host smart-997fba32-8eea-4b66-a663-cadeab5869ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814150692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2814150692
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3332776621
Short name T853
Test name
Test status
Simulation time 383798846 ps
CPU time 1.44 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 217508 kb
Host smart-9aa30697-12a5-4d1c-b8aa-0b61f90166ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332776621 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3332776621
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3969367350
Short name T55
Test name
Test status
Simulation time 536583622 ps
CPU time 1.43 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 200884 kb
Host smart-34f88563-d1c8-4fe3-800d-0d45a41471dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969367350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3969367350
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2988376298
Short name T847
Test name
Test status
Simulation time 316907624 ps
CPU time 0.73 seconds
Started Aug 16 05:11:48 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 200832 kb
Host smart-42bd9aef-2bbe-45c6-a9fd-facf3f47e0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988376298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2988376298
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2568146038
Short name T896
Test name
Test status
Simulation time 4487812649 ps
CPU time 2.64 seconds
Started Aug 16 05:12:16 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 201124 kb
Host smart-f840ca2e-b57a-4dfb-b04b-71d1d7ddbf86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568146038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2568146038
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1152096191
Short name T881
Test name
Test status
Simulation time 521329578 ps
CPU time 2.29 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 201152 kb
Host smart-9b9a118a-cd9a-4678-873e-3ed1aad0acff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152096191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1152096191
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2871940087
Short name T852
Test name
Test status
Simulation time 8703472590 ps
CPU time 8.09 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:27 PM PDT 24
Peak memory 201236 kb
Host smart-481783fb-6c63-4383-a992-764860a3efc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871940087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2871940087
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1727384668
Short name T804
Test name
Test status
Simulation time 376692338 ps
CPU time 0.85 seconds
Started Aug 16 05:12:22 PM PDT 24
Finished Aug 16 05:12:33 PM PDT 24
Peak memory 200820 kb
Host smart-741370d7-fc02-4fa8-9c17-7934ace25480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727384668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1727384668
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3945603270
Short name T815
Test name
Test status
Simulation time 418894024 ps
CPU time 1.59 seconds
Started Aug 16 05:12:20 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 200784 kb
Host smart-44f49c0e-0322-4177-a805-9f20bb307796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945603270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3945603270
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3229125552
Short name T822
Test name
Test status
Simulation time 384912546 ps
CPU time 1.42 seconds
Started Aug 16 05:12:23 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 200760 kb
Host smart-d69985b8-1017-4feb-b3e1-c89950fa23f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229125552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3229125552
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3024114816
Short name T818
Test name
Test status
Simulation time 512347348 ps
CPU time 0.93 seconds
Started Aug 16 05:12:14 PM PDT 24
Finished Aug 16 05:12:15 PM PDT 24
Peak memory 200848 kb
Host smart-43c0f2af-55fc-4bf3-b452-5a7728c663f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024114816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3024114816
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3567498971
Short name T908
Test name
Test status
Simulation time 454368179 ps
CPU time 1.55 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:23 PM PDT 24
Peak memory 200824 kb
Host smart-0189f1e3-79c1-499a-94d9-6f1f771603a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567498971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3567498971
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.535129187
Short name T800
Test name
Test status
Simulation time 469353488 ps
CPU time 1.17 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 200852 kb
Host smart-04f02a49-2ac8-4050-98a2-0dc87736f5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535129187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.535129187
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1077782941
Short name T833
Test name
Test status
Simulation time 364496662 ps
CPU time 1.51 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200844 kb
Host smart-c263fd37-5da4-4fc2-9ea8-9744210ea529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077782941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1077782941
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1743347354
Short name T802
Test name
Test status
Simulation time 469247928 ps
CPU time 1.63 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:21 PM PDT 24
Peak memory 200840 kb
Host smart-5f4026e0-4aee-4f06-bf9e-b07af1904030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743347354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1743347354
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2879426678
Short name T799
Test name
Test status
Simulation time 488454741 ps
CPU time 1.68 seconds
Started Aug 16 05:12:14 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 200844 kb
Host smart-e4b60e12-c032-4394-b1ff-acd4de597ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879426678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2879426678
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2172639076
Short name T885
Test name
Test status
Simulation time 493026013 ps
CPU time 1.19 seconds
Started Aug 16 05:12:25 PM PDT 24
Finished Aug 16 05:12:26 PM PDT 24
Peak memory 200760 kb
Host smart-be10b4ed-9c08-4d55-bc5f-232c309eeb79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172639076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2172639076
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.46115319
Short name T917
Test name
Test status
Simulation time 387205847 ps
CPU time 1.8 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 200964 kb
Host smart-e07d2015-f0f0-4c90-9084-5d42db2f7996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46115319 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.46115319
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2405408300
Short name T877
Test name
Test status
Simulation time 514998745 ps
CPU time 1.98 seconds
Started Aug 16 05:12:11 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 200932 kb
Host smart-3e849b0e-493f-4bc0-9909-871af790d9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405408300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2405408300
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.269411753
Short name T803
Test name
Test status
Simulation time 497328064 ps
CPU time 1.22 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 200788 kb
Host smart-55c928f1-7305-4ff6-a64b-6ca9062ff52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269411753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.269411753
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.556707617
Short name T836
Test name
Test status
Simulation time 2317709229 ps
CPU time 3.56 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200900 kb
Host smart-bf2e2633-0512-4655-896c-35dd9127e809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556707617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.556707617
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4000525370
Short name T887
Test name
Test status
Simulation time 366388323 ps
CPU time 2.48 seconds
Started Aug 16 05:12:08 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 201048 kb
Host smart-930b8eb0-4474-4b43-9264-8234850b2ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000525370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4000525370
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2400713017
Short name T72
Test name
Test status
Simulation time 8375784778 ps
CPU time 7.92 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:10 PM PDT 24
Peak memory 201120 kb
Host smart-8a4b5d38-58d0-4247-8df5-c4dce0b66411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400713017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2400713017
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.137714666
Short name T80
Test name
Test status
Simulation time 514409799 ps
CPU time 2 seconds
Started Aug 16 05:12:15 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200976 kb
Host smart-cf1da3e1-0bca-4797-8a6a-f2182ea3be6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137714666 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.137714666
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4205281497
Short name T813
Test name
Test status
Simulation time 337429594 ps
CPU time 1.55 seconds
Started Aug 16 05:12:02 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 200884 kb
Host smart-271b82fc-0aa7-4701-8fc9-9b773650610e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205281497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4205281497
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.381055152
Short name T814
Test name
Test status
Simulation time 444081175 ps
CPU time 1.12 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200828 kb
Host smart-abc66016-760f-48db-a246-e394bda9488f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381055152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.381055152
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.220649727
Short name T826
Test name
Test status
Simulation time 2327033978 ps
CPU time 3.18 seconds
Started Aug 16 05:12:01 PM PDT 24
Finished Aug 16 05:12:05 PM PDT 24
Peak memory 200976 kb
Host smart-5afc7051-3f6f-4b35-be2b-7e7ae9801a7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220649727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.220649727
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3759830412
Short name T861
Test name
Test status
Simulation time 584876108 ps
CPU time 2.82 seconds
Started Aug 16 05:11:49 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 217464 kb
Host smart-1237c457-2c27-49a9-afcf-bce8c02f9a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759830412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3759830412
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3052008595
Short name T71
Test name
Test status
Simulation time 8283626831 ps
CPU time 11.63 seconds
Started Aug 16 05:12:16 PM PDT 24
Finished Aug 16 05:12:28 PM PDT 24
Peak memory 201152 kb
Host smart-8726d3d4-118f-4803-9389-f3495197d95d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052008595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3052008595
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.135798415
Short name T878
Test name
Test status
Simulation time 514738351 ps
CPU time 1.69 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 200980 kb
Host smart-c8446ae6-6675-4085-b558-e6c4ec63f049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135798415 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.135798415
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.258045288
Short name T117
Test name
Test status
Simulation time 472446996 ps
CPU time 0.96 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200856 kb
Host smart-862c03b1-1cf4-42e8-b52e-3c43a23fc98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258045288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.258045288
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2927740054
Short name T840
Test name
Test status
Simulation time 472948390 ps
CPU time 1.78 seconds
Started Aug 16 05:12:01 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 200840 kb
Host smart-7749ae5a-5a68-4af2-b27f-88e0a8f7c7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927740054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2927740054
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3374465556
Short name T827
Test name
Test status
Simulation time 2194545554 ps
CPU time 5.44 seconds
Started Aug 16 05:12:19 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 200952 kb
Host smart-d558d78c-9b32-4ad8-945b-a2340e1a6f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374465556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3374465556
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.461338070
Short name T856
Test name
Test status
Simulation time 338877768 ps
CPU time 3.48 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 201136 kb
Host smart-091da632-4448-4ae0-927d-e53cfeb204af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461338070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.461338070
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1809867476
Short name T74
Test name
Test status
Simulation time 4428157493 ps
CPU time 4.06 seconds
Started Aug 16 05:11:59 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 201160 kb
Host smart-42b03d4a-50ca-4e7c-b81d-6c44b3f2bcee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809867476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1809867476
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.801182907
Short name T102
Test name
Test status
Simulation time 392783574 ps
CPU time 1.39 seconds
Started Aug 16 05:12:22 PM PDT 24
Finished Aug 16 05:12:24 PM PDT 24
Peak memory 200940 kb
Host smart-8abeef93-cced-429c-94cb-cd71ee5aff8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801182907 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.801182907
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3040553167
Short name T122
Test name
Test status
Simulation time 558238627 ps
CPU time 2.08 seconds
Started Aug 16 05:12:18 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 200924 kb
Host smart-d88e3db1-236b-4ef7-a9a4-c6be4892457d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040553167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3040553167
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3743487657
Short name T851
Test name
Test status
Simulation time 356029846 ps
CPU time 1.5 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 200836 kb
Host smart-4246e0c5-3ca5-48cd-8f66-6c6f09a0c169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743487657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3743487657
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2165045591
Short name T867
Test name
Test status
Simulation time 5418581406 ps
CPU time 4.61 seconds
Started Aug 16 05:12:03 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 201176 kb
Host smart-580fba3e-a408-4c8b-a153-85f18db744f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165045591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2165045591
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3486393028
Short name T871
Test name
Test status
Simulation time 447377872 ps
CPU time 3.3 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:09 PM PDT 24
Peak memory 217432 kb
Host smart-fc6a577f-e396-4144-abd2-e1ab4e124c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486393028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3486393028
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2990449420
Short name T67
Test name
Test status
Simulation time 417142462 ps
CPU time 1.86 seconds
Started Aug 16 05:12:09 PM PDT 24
Finished Aug 16 05:12:11 PM PDT 24
Peak memory 200968 kb
Host smart-abea9b35-5e4a-4ef1-8b61-35199942406d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990449420 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2990449420
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3231236431
Short name T119
Test name
Test status
Simulation time 617488557 ps
CPU time 0.99 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:06 PM PDT 24
Peak memory 200956 kb
Host smart-181fdc50-9bed-42ed-b63e-c365590f322e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231236431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3231236431
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1394794709
Short name T805
Test name
Test status
Simulation time 329808185 ps
CPU time 0.82 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:01 PM PDT 24
Peak memory 200832 kb
Host smart-bf94b6d3-969e-4456-9bb1-2ed42dcb1323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394794709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1394794709
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1543327490
Short name T913
Test name
Test status
Simulation time 2807634255 ps
CPU time 6.14 seconds
Started Aug 16 05:12:10 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 201000 kb
Host smart-17d02b29-cded-4216-9822-eff88f5afcda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543327490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1543327490
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2717239446
Short name T886
Test name
Test status
Simulation time 559667350 ps
CPU time 3.81 seconds
Started Aug 16 05:12:04 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 210428 kb
Host smart-e1e941d7-a6cd-4cf3-8b9b-abf995a75cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717239446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2717239446
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2067278041
Short name T902
Test name
Test status
Simulation time 8527196665 ps
CPU time 7.59 seconds
Started Aug 16 05:12:21 PM PDT 24
Finished Aug 16 05:12:29 PM PDT 24
Peak memory 201132 kb
Host smart-1c50b303-90f6-4e01-94e0-b8bcc95d697e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067278041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2067278041
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.94356794
Short name T519
Test name
Test status
Simulation time 367231527 ps
CPU time 0.84 seconds
Started Aug 16 05:12:40 PM PDT 24
Finished Aug 16 05:12:41 PM PDT 24
Peak memory 201940 kb
Host smart-91f7b74c-65fa-4821-9e83-e3ebd70bcaf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94356794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.94356794
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3241575769
Short name T762
Test name
Test status
Simulation time 352165587174 ps
CPU time 435.72 seconds
Started Aug 16 05:12:33 PM PDT 24
Finished Aug 16 05:19:48 PM PDT 24
Peak memory 202116 kb
Host smart-a2729224-e281-41c1-84ea-a12f427fcf6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241575769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3241575769
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3908830218
Short name T349
Test name
Test status
Simulation time 168570982957 ps
CPU time 374.21 seconds
Started Aug 16 05:12:44 PM PDT 24
Finished Aug 16 05:18:58 PM PDT 24
Peak memory 202204 kb
Host smart-be47d0b4-161d-4300-b08e-e40e81c91285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908830218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3908830218
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4118082293
Short name T523
Test name
Test status
Simulation time 329838825712 ps
CPU time 309.23 seconds
Started Aug 16 05:12:36 PM PDT 24
Finished Aug 16 05:17:45 PM PDT 24
Peak memory 202076 kb
Host smart-4405cc4b-777d-42e5-9c63-7af325825a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118082293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4118082293
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4230280080
Short name T543
Test name
Test status
Simulation time 488534017547 ps
CPU time 536.72 seconds
Started Aug 16 05:12:32 PM PDT 24
Finished Aug 16 05:21:29 PM PDT 24
Peak memory 202124 kb
Host smart-61d1bffc-b1a7-4494-b21c-c2f23482a6fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230280080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4230280080
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2204450356
Short name T237
Test name
Test status
Simulation time 166556842632 ps
CPU time 190.49 seconds
Started Aug 16 05:12:32 PM PDT 24
Finished Aug 16 05:15:43 PM PDT 24
Peak memory 202064 kb
Host smart-9421a5d6-8527-41cf-94d4-8f1e2d10f2f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204450356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2204450356
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3493398361
Short name T399
Test name
Test status
Simulation time 594871978745 ps
CPU time 1378.13 seconds
Started Aug 16 05:12:53 PM PDT 24
Finished Aug 16 05:35:51 PM PDT 24
Peak memory 201996 kb
Host smart-88ff92ea-0d86-4cc1-930e-ee91e5a776fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493398361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3493398361
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1865919261
Short name T194
Test name
Test status
Simulation time 127178037018 ps
CPU time 456.03 seconds
Started Aug 16 05:12:53 PM PDT 24
Finished Aug 16 05:20:29 PM PDT 24
Peak memory 202308 kb
Host smart-435e6953-422a-4bac-aabb-bfcf49ed8285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865919261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1865919261
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4260001310
Short name T365
Test name
Test status
Simulation time 26197652377 ps
CPU time 11.18 seconds
Started Aug 16 05:12:34 PM PDT 24
Finished Aug 16 05:12:46 PM PDT 24
Peak memory 201896 kb
Host smart-b1b84581-d8b8-4d2e-96a3-ad5df45291f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260001310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4260001310
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.610365816
Short name T385
Test name
Test status
Simulation time 4904236576 ps
CPU time 13.24 seconds
Started Aug 16 05:12:33 PM PDT 24
Finished Aug 16 05:12:46 PM PDT 24
Peak memory 201920 kb
Host smart-89d153c9-cb87-405f-a36f-fc6733338ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610365816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.610365816
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1880789136
Short name T462
Test name
Test status
Simulation time 5620169444 ps
CPU time 4.44 seconds
Started Aug 16 05:12:44 PM PDT 24
Finished Aug 16 05:12:49 PM PDT 24
Peak memory 201908 kb
Host smart-e8b01bc7-9dc0-47d6-b8fb-f54daf486392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880789136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1880789136
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3466712202
Short name T526
Test name
Test status
Simulation time 338259178989 ps
CPU time 200.32 seconds
Started Aug 16 05:12:28 PM PDT 24
Finished Aug 16 05:15:48 PM PDT 24
Peak memory 202096 kb
Host smart-8fbcef7b-12b8-4e0b-aa6b-933f5a427de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466712202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3466712202
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.164742493
Short name T647
Test name
Test status
Simulation time 330853988 ps
CPU time 1.33 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:12:57 PM PDT 24
Peak memory 201924 kb
Host smart-9fc19113-f106-485a-9553-c93f82ed8f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164742493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.164742493
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.914817173
Short name T328
Test name
Test status
Simulation time 491288536900 ps
CPU time 583.98 seconds
Started Aug 16 05:12:33 PM PDT 24
Finished Aug 16 05:22:22 PM PDT 24
Peak memory 202116 kb
Host smart-ab924649-6154-4973-bad8-dd8f30b0795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914817173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.914817173
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1992635810
Short name T436
Test name
Test status
Simulation time 489471372224 ps
CPU time 293.46 seconds
Started Aug 16 05:12:32 PM PDT 24
Finished Aug 16 05:17:26 PM PDT 24
Peak memory 202080 kb
Host smart-f5358840-11f9-41b9-a1c7-dc5bd61264e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992635810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1992635810
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3427596844
Short name T299
Test name
Test status
Simulation time 486512626367 ps
CPU time 515.89 seconds
Started Aug 16 05:12:33 PM PDT 24
Finished Aug 16 05:21:09 PM PDT 24
Peak memory 202132 kb
Host smart-0ac5dc56-2756-4e98-83c8-d8a9041da827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427596844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3427596844
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2622817519
Short name T112
Test name
Test status
Simulation time 323680894838 ps
CPU time 683.78 seconds
Started Aug 16 05:12:33 PM PDT 24
Finished Aug 16 05:23:57 PM PDT 24
Peak memory 202052 kb
Host smart-39f6dc99-86e8-4b1a-89a5-3eb285590518
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622817519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2622817519
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.529545809
Short name T138
Test name
Test status
Simulation time 211243097091 ps
CPU time 55.73 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:13:52 PM PDT 24
Peak memory 202020 kb
Host smart-57eeb80b-0f2c-4bb0-8f41-e6e0a2c66e60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529545809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.529545809
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.842366133
Short name T738
Test name
Test status
Simulation time 389908111731 ps
CPU time 450.82 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:20:27 PM PDT 24
Peak memory 202184 kb
Host smart-46713415-f420-4977-a16e-2bd16e7e3fd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842366133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.842366133
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2582221658
Short name T355
Test name
Test status
Simulation time 107169343819 ps
CPU time 462.3 seconds
Started Aug 16 05:12:51 PM PDT 24
Finished Aug 16 05:20:34 PM PDT 24
Peak memory 202316 kb
Host smart-8b91da91-0fd5-42de-ad13-e50e6e4507f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582221658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2582221658
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.492255475
Short name T403
Test name
Test status
Simulation time 45212694652 ps
CPU time 48.77 seconds
Started Aug 16 05:12:49 PM PDT 24
Finished Aug 16 05:13:38 PM PDT 24
Peak memory 201904 kb
Host smart-4bd729b6-7446-4c7f-9a19-d5b782ab2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492255475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.492255475
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.833156963
Short name T670
Test name
Test status
Simulation time 4676170413 ps
CPU time 12.42 seconds
Started Aug 16 05:12:45 PM PDT 24
Finished Aug 16 05:12:57 PM PDT 24
Peak memory 201896 kb
Host smart-bbb8ef7c-d700-4045-9615-ce3edc3e6185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833156963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.833156963
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1915304275
Short name T64
Test name
Test status
Simulation time 4084760079 ps
CPU time 10.06 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:13:06 PM PDT 24
Peak memory 217396 kb
Host smart-2329c594-28de-4435-8508-22d7baaf7f57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915304275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1915304275
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1020981109
Short name T91
Test name
Test status
Simulation time 5695217903 ps
CPU time 3.89 seconds
Started Aug 16 05:12:37 PM PDT 24
Finished Aug 16 05:12:41 PM PDT 24
Peak memory 201920 kb
Host smart-93866f4a-2b30-4bc8-afbb-fd86e9b5369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020981109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1020981109
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3284711771
Short name T565
Test name
Test status
Simulation time 207301931046 ps
CPU time 65.64 seconds
Started Aug 16 05:12:53 PM PDT 24
Finished Aug 16 05:13:59 PM PDT 24
Peak memory 202116 kb
Host smart-a277db70-2895-4037-a27c-d23c61224397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284711771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3284711771
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4043101677
Short name T730
Test name
Test status
Simulation time 68293140350 ps
CPU time 40.5 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 211016 kb
Host smart-15409dbb-9e28-4e98-a433-72c63ab338bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043101677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4043101677
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1327557959
Short name T664
Test name
Test status
Simulation time 388658153 ps
CPU time 1.46 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:15 PM PDT 24
Peak memory 201920 kb
Host smart-94ad445c-195f-4729-95d2-c3808bffa17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327557959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1327557959
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.707632743
Short name T726
Test name
Test status
Simulation time 179357709010 ps
CPU time 405.36 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:20:08 PM PDT 24
Peak memory 202068 kb
Host smart-2ab2fd1d-94c2-44c1-af15-8ba33d87114b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707632743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.707632743
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2792045738
Short name T287
Test name
Test status
Simulation time 161089636029 ps
CPU time 341.51 seconds
Started Aug 16 05:13:07 PM PDT 24
Finished Aug 16 05:18:54 PM PDT 24
Peak memory 202068 kb
Host smart-1df39a1c-dc16-4215-ad6a-1e7e22f544ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792045738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2792045738
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.823961284
Short name T372
Test name
Test status
Simulation time 491768429672 ps
CPU time 307 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:18:24 PM PDT 24
Peak memory 202056 kb
Host smart-51927f8a-23ec-4ca6-86c0-39ebe860cbd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=823961284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.823961284
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3022730623
Short name T540
Test name
Test status
Simulation time 323714764574 ps
CPU time 360.5 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:19:17 PM PDT 24
Peak memory 202032 kb
Host smart-0fb9f3d1-954d-4c98-a696-e36481b5e4ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022730623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3022730623
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.227851973
Short name T578
Test name
Test status
Simulation time 386426230793 ps
CPU time 950.04 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:29:05 PM PDT 24
Peak memory 202072 kb
Host smart-d69b654b-180c-4e76-9b4e-531d7a27867a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227851973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.227851973
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1419590949
Short name T685
Test name
Test status
Simulation time 606201202352 ps
CPU time 1342.42 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:35:33 PM PDT 24
Peak memory 202068 kb
Host smart-1e829659-e239-470b-bf16-5c34e03e40f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419590949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1419590949
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1914792965
Short name T200
Test name
Test status
Simulation time 115535700764 ps
CPU time 389.6 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:19:41 PM PDT 24
Peak memory 202228 kb
Host smart-bc11da66-d74f-4007-a749-6d06c36a98e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914792965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1914792965
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.771200285
Short name T598
Test name
Test status
Simulation time 29701611874 ps
CPU time 7.75 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:21 PM PDT 24
Peak memory 201904 kb
Host smart-4f7f9ae7-0c92-4175-8355-3b5ba42724ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771200285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.771200285
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2144233347
Short name T445
Test name
Test status
Simulation time 4177157715 ps
CPU time 6.13 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:25 PM PDT 24
Peak memory 201912 kb
Host smart-86472fd0-1207-4be4-8c00-bbb85df20e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144233347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2144233347
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3013747358
Short name T374
Test name
Test status
Simulation time 5834290954 ps
CPU time 14.32 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 201892 kb
Host smart-2484125f-59ce-4d2e-9229-e724df41829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013747358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3013747358
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1962770204
Short name T655
Test name
Test status
Simulation time 233149212524 ps
CPU time 125.48 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:15:22 PM PDT 24
Peak memory 202072 kb
Host smart-dadf83de-bd42-48b9-8352-94b2c38b1d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962770204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1962770204
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3592354303
Short name T23
Test name
Test status
Simulation time 4127522105 ps
CPU time 7.89 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:20 PM PDT 24
Peak memory 202052 kb
Host smart-1676a2f8-e383-4bab-91df-dfc9e94b94e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592354303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3592354303
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4030160512
Short name T652
Test name
Test status
Simulation time 380211098 ps
CPU time 1.19 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:13:21 PM PDT 24
Peak memory 201944 kb
Host smart-1dae7256-d9d9-4665-a991-14cc87f998b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030160512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4030160512
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3025933816
Short name T560
Test name
Test status
Simulation time 169944709091 ps
CPU time 391.16 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:19:44 PM PDT 24
Peak memory 202060 kb
Host smart-a6b6a227-1fa1-42c1-a53e-e530ce3a2dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025933816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3025933816
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2609367886
Short name T496
Test name
Test status
Simulation time 318430698642 ps
CPU time 785.5 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:26:18 PM PDT 24
Peak memory 202084 kb
Host smart-f009c9e4-5489-4913-b045-a0dd36c209d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609367886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2609367886
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4045143099
Short name T179
Test name
Test status
Simulation time 490521612497 ps
CPU time 196.46 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:16:32 PM PDT 24
Peak memory 202032 kb
Host smart-82bb6712-6ad7-4fa9-a2f3-2dd23d4cd3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045143099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4045143099
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2302367501
Short name T398
Test name
Test status
Simulation time 328704270164 ps
CPU time 88.46 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:14:40 PM PDT 24
Peak memory 202076 kb
Host smart-70624672-c8ed-45d9-b94e-bb7187425fdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302367501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2302367501
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1272800558
Short name T211
Test name
Test status
Simulation time 171243219563 ps
CPU time 127.5 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:15:22 PM PDT 24
Peak memory 202080 kb
Host smart-ce32451a-5473-43d5-a3e1-247e0fbd025c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272800558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1272800558
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.789053152
Short name T177
Test name
Test status
Simulation time 397691454672 ps
CPU time 155.3 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:15:47 PM PDT 24
Peak memory 202076 kb
Host smart-302f727e-608d-48ea-89f9-095f630aad6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789053152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.789053152
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3301682092
Short name T444
Test name
Test status
Simulation time 40713750777 ps
CPU time 6.88 seconds
Started Aug 16 05:13:08 PM PDT 24
Finished Aug 16 05:13:15 PM PDT 24
Peak memory 201916 kb
Host smart-4fbb0f30-dc10-4704-9d30-e11e86060b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301682092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3301682092
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3951760011
Short name T508
Test name
Test status
Simulation time 4585668016 ps
CPU time 2.99 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 201896 kb
Host smart-1cb24e9f-d375-4459-b0c7-14ad46fe69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951760011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3951760011
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3456204959
Short name T624
Test name
Test status
Simulation time 5697223785 ps
CPU time 4.05 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:17 PM PDT 24
Peak memory 201892 kb
Host smart-c5a7cb3b-2a6b-48d8-9227-3ea85ffe9415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456204959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3456204959
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1405756864
Short name T344
Test name
Test status
Simulation time 368137536182 ps
CPU time 1147.08 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 212652 kb
Host smart-3f2d33e7-7272-4cc8-b99b-f04e0bc3d29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405756864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1405756864
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2644296545
Short name T715
Test name
Test status
Simulation time 24470307959 ps
CPU time 45.02 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:14:00 PM PDT 24
Peak memory 210688 kb
Host smart-2391c2a3-afc0-418e-a262-c55d81692d77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644296545 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2644296545
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1810626404
Short name T376
Test name
Test status
Simulation time 365641363 ps
CPU time 0.82 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:24 PM PDT 24
Peak memory 201928 kb
Host smart-ad3ac32d-fd08-4ef6-867c-53f862664f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810626404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1810626404
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3019472535
Short name T546
Test name
Test status
Simulation time 321402464330 ps
CPU time 753.65 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:25:46 PM PDT 24
Peak memory 202076 kb
Host smart-eba2342f-0199-499d-9ace-0f7bb21f5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019472535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3019472535
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3984566352
Short name T459
Test name
Test status
Simulation time 166551935742 ps
CPU time 368.92 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:19:18 PM PDT 24
Peak memory 202028 kb
Host smart-0045d8b0-893f-44ea-8613-b74e64b9f714
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984566352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3984566352
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.914717775
Short name T765
Test name
Test status
Simulation time 164290814511 ps
CPU time 71.88 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:14:25 PM PDT 24
Peak memory 202064 kb
Host smart-0853f4b7-720f-47dd-88e2-a16f98a64b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914717775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.914717775
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3667416875
Short name T400
Test name
Test status
Simulation time 167190377785 ps
CPU time 35.62 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:54 PM PDT 24
Peak memory 202032 kb
Host smart-cf4b252c-9989-4f53-83d6-f1cfa1f6dc82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667416875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3667416875
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3142002492
Short name T152
Test name
Test status
Simulation time 340290071034 ps
CPU time 84.2 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:14:36 PM PDT 24
Peak memory 202004 kb
Host smart-d0b078d8-b711-4d9c-bb2d-749025f81cee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142002492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3142002492
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1644942303
Short name T774
Test name
Test status
Simulation time 392860161676 ps
CPU time 926.33 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:28:41 PM PDT 24
Peak memory 202092 kb
Host smart-3bc96d88-a456-476d-8e8a-6bb514bf0f82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644942303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1644942303
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3862011262
Short name T602
Test name
Test status
Simulation time 69467316133 ps
CPU time 235.59 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:17:16 PM PDT 24
Peak memory 202328 kb
Host smart-56b67059-bc95-43c9-83f7-63e1beb31749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862011262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3862011262
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3448234401
Short name T507
Test name
Test status
Simulation time 42322760928 ps
CPU time 25.65 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:44 PM PDT 24
Peak memory 201908 kb
Host smart-2d8e538f-39a2-42ef-bf28-720d23f30801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448234401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3448234401
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.250371600
Short name T370
Test name
Test status
Simulation time 4643396532 ps
CPU time 3.56 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:13:15 PM PDT 24
Peak memory 201900 kb
Host smart-f7a8bd94-0a1a-410f-bce4-9ce7a0d7b083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250371600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.250371600
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.473242273
Short name T368
Test name
Test status
Simulation time 5724625700 ps
CPU time 4.2 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201908 kb
Host smart-8dba695e-d257-42af-b902-9fca29805fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473242273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.473242273
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3772920626
Short name T423
Test name
Test status
Simulation time 36954874701 ps
CPU time 20.41 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:34 PM PDT 24
Peak memory 201932 kb
Host smart-8727906e-5c91-4e4d-9724-4c17f25289ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772920626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3772920626
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3659450084
Short name T330
Test name
Test status
Simulation time 3012021207 ps
CPU time 8.61 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 210408 kb
Host smart-d01964cb-288b-4fa4-9689-bc80fe957041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659450084 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3659450084
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.581742567
Short name T707
Test name
Test status
Simulation time 382848900 ps
CPU time 1.5 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:13:18 PM PDT 24
Peak memory 201900 kb
Host smart-014cab08-c543-4f02-b0fc-a1f2901a1b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581742567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.581742567
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3897914420
Short name T746
Test name
Test status
Simulation time 397756051200 ps
CPU time 666.94 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:24:12 PM PDT 24
Peak memory 202164 kb
Host smart-9aaa2fa7-4125-4566-9821-04cd41583101
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897914420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3897914420
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.383253773
Short name T711
Test name
Test status
Simulation time 173887671643 ps
CPU time 51.13 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:14:06 PM PDT 24
Peak memory 202012 kb
Host smart-6eff4a33-6c07-4582-b0f9-94faeb5ac220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383253773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.383253773
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1657546404
Short name T213
Test name
Test status
Simulation time 166012658063 ps
CPU time 362.47 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:19:16 PM PDT 24
Peak memory 202052 kb
Host smart-d20e1a93-b255-4cc2-a5cb-9ba21339beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657546404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1657546404
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2369004463
Short name T460
Test name
Test status
Simulation time 500276090656 ps
CPU time 1151.38 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 202104 kb
Host smart-cc00ab00-0174-4046-81e2-d1ccf86e6dbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369004463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2369004463
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1005923766
Short name T243
Test name
Test status
Simulation time 319548667633 ps
CPU time 349.58 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:19:08 PM PDT 24
Peak memory 202076 kb
Host smart-01320a30-8cc0-486b-915b-79e4275ab5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005923766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1005923766
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1756028566
Short name T477
Test name
Test status
Simulation time 330216287495 ps
CPU time 69.25 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:14:28 PM PDT 24
Peak memory 202084 kb
Host smart-86457f15-37b9-4f77-bb62-66c5730e9cf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756028566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1756028566
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4091187926
Short name T611
Test name
Test status
Simulation time 607270886519 ps
CPU time 686.15 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:24:38 PM PDT 24
Peak memory 202100 kb
Host smart-7a67cb45-431a-4287-ae79-c073975211e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091187926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4091187926
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1123780680
Short name T706
Test name
Test status
Simulation time 409940488136 ps
CPU time 103.2 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:15:03 PM PDT 24
Peak memory 202044 kb
Host smart-a01f3d9f-a941-4dd4-bcbc-376b98bd18df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123780680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1123780680
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.850997294
Short name T10
Test name
Test status
Simulation time 94297368744 ps
CPU time 464.53 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:21:05 PM PDT 24
Peak memory 202328 kb
Host smart-404a6a44-4f7b-4781-a9b6-8e89f5345bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850997294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.850997294
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3264139148
Short name T791
Test name
Test status
Simulation time 43644085510 ps
CPU time 25.86 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:13:48 PM PDT 24
Peak memory 201896 kb
Host smart-f1b2c164-696c-4753-8403-34cf88538950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264139148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3264139148
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2989802524
Short name T522
Test name
Test status
Simulation time 5587823955 ps
CPU time 2.57 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:13:08 PM PDT 24
Peak memory 201876 kb
Host smart-68bf7acf-495d-489c-9f67-b616a9e74fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989802524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2989802524
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2543731465
Short name T471
Test name
Test status
Simulation time 6029886423 ps
CPU time 4.32 seconds
Started Aug 16 05:13:07 PM PDT 24
Finished Aug 16 05:13:12 PM PDT 24
Peak memory 201912 kb
Host smart-abf991f9-fc65-4505-b08b-daa7732a9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543731465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2543731465
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.814101010
Short name T390
Test name
Test status
Simulation time 450973096 ps
CPU time 0.74 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 201932 kb
Host smart-b4f1c209-9e5d-410b-aa97-dc30b54da3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814101010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.814101010
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.383923561
Short name T332
Test name
Test status
Simulation time 155541589749 ps
CPU time 77.01 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:14:35 PM PDT 24
Peak memory 202108 kb
Host smart-04e5efdc-dc9a-42d8-90da-739941ed9c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383923561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.383923561
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4278604602
Short name T796
Test name
Test status
Simulation time 329074369945 ps
CPU time 762.37 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:25:57 PM PDT 24
Peak memory 202080 kb
Host smart-eb74d3c9-7a0d-4b81-9998-1013c879f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278604602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4278604602
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2693325601
Short name T424
Test name
Test status
Simulation time 492134340726 ps
CPU time 1023.79 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:30:15 PM PDT 24
Peak memory 202132 kb
Host smart-f1b4856e-bb3b-40d2-9a0f-173e7251492d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693325601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2693325601
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1973457221
Short name T137
Test name
Test status
Simulation time 325577330896 ps
CPU time 390.86 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:19:45 PM PDT 24
Peak memory 202076 kb
Host smart-0a7f6ea5-dbc7-4e04-aa70-9034fd9c0284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973457221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1973457221
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2064728454
Short name T554
Test name
Test status
Simulation time 328034337208 ps
CPU time 761.94 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:25:56 PM PDT 24
Peak memory 202096 kb
Host smart-1cff858e-4f2b-47fa-b600-8d60c6456854
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064728454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2064728454
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1818626276
Short name T351
Test name
Test status
Simulation time 230871639128 ps
CPU time 557.32 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:22:38 PM PDT 24
Peak memory 202036 kb
Host smart-2e95d3c1-2f84-499c-8a51-6dfb73498b04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818626276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1818626276
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3787092767
Short name T34
Test name
Test status
Simulation time 195665206771 ps
CPU time 446.14 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:20:33 PM PDT 24
Peak memory 202116 kb
Host smart-1d91c72d-d09f-41a3-b7cf-6dc6dd0c8931
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787092767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3787092767
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3429371027
Short name T476
Test name
Test status
Simulation time 88558401152 ps
CPU time 374.1 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:19:29 PM PDT 24
Peak memory 202288 kb
Host smart-28667122-347a-43e7-bd8f-04038f5b8a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429371027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3429371027
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.358224802
Short name T492
Test name
Test status
Simulation time 45325985626 ps
CPU time 103.15 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:15:07 PM PDT 24
Peak memory 201964 kb
Host smart-0b0b11b1-0a1b-44a6-a0cc-a974d3388ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358224802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.358224802
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1278802579
Short name T483
Test name
Test status
Simulation time 5526982449 ps
CPU time 3.69 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 202036 kb
Host smart-c2730917-6879-450c-a89b-c3226ecb0425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278802579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1278802579
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3421504043
Short name T406
Test name
Test status
Simulation time 5603660668 ps
CPU time 4.22 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 201928 kb
Host smart-a0c34ea1-4738-4e99-8a07-d8700a6cca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421504043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3421504043
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.571170376
Short name T95
Test name
Test status
Simulation time 10453569956 ps
CPU time 11.92 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 210688 kb
Host smart-615140bd-a1bb-4b5b-a7ef-e51ec97fcbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571170376 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.571170376
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2500371522
Short name T417
Test name
Test status
Simulation time 409918540 ps
CPU time 0.84 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:13:20 PM PDT 24
Peak memory 201936 kb
Host smart-f8d00a6e-6a67-45a4-af0b-01bd5995ea72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500371522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2500371522
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2056142314
Short name T280
Test name
Test status
Simulation time 184198440618 ps
CPU time 57.76 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:14:28 PM PDT 24
Peak memory 202028 kb
Host smart-64dc31ec-68f4-4432-a6e9-f4e518480761
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056142314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2056142314
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2552668065
Short name T667
Test name
Test status
Simulation time 166897167873 ps
CPU time 28.23 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:46 PM PDT 24
Peak memory 202120 kb
Host smart-5b1852fb-8fbc-4fbc-8dba-128816c5d297
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552668065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2552668065
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1739709429
Short name T218
Test name
Test status
Simulation time 165231716479 ps
CPU time 98.36 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:14:52 PM PDT 24
Peak memory 202096 kb
Host smart-4efee994-1d85-42b7-9591-228535f39b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739709429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1739709429
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.657183462
Short name T574
Test name
Test status
Simulation time 164188910322 ps
CPU time 72.67 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:14:33 PM PDT 24
Peak memory 202068 kb
Host smart-ce3356d4-6211-4320-a527-c1828c420930
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657183462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.657183462
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1824969125
Short name T397
Test name
Test status
Simulation time 197447729913 ps
CPU time 474.73 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:21:08 PM PDT 24
Peak memory 202092 kb
Host smart-867a2f7c-ced0-40bb-bd08-ad25b1dcdb19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824969125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1824969125
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.26813117
Short name T88
Test name
Test status
Simulation time 129769146800 ps
CPU time 409.57 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:20:08 PM PDT 24
Peak memory 202292 kb
Host smart-b31b830f-3f4f-4e6c-8b69-c850768dfc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26813117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.26813117
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3596864814
Short name T97
Test name
Test status
Simulation time 24775827644 ps
CPU time 14.66 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:30 PM PDT 24
Peak memory 201908 kb
Host smart-107ab53a-a050-4ae5-93fc-a3093cc66ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596864814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3596864814
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2221789233
Short name T542
Test name
Test status
Simulation time 2742217228 ps
CPU time 3.54 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:19 PM PDT 24
Peak memory 201880 kb
Host smart-9879cff6-0bc0-4efc-907d-4a884cc1a865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221789233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2221789233
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.407150587
Short name T616
Test name
Test status
Simulation time 5899558511 ps
CPU time 13.65 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:29 PM PDT 24
Peak memory 201892 kb
Host smart-8595b3c8-73e7-497d-b2cb-86c6443826f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407150587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.407150587
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3400904045
Short name T22
Test name
Test status
Simulation time 14621692089 ps
CPU time 20.37 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:33 PM PDT 24
Peak memory 210692 kb
Host smart-7399390c-e0a1-4b92-9283-2a8a67877067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400904045 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3400904045
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4109564272
Short name T367
Test name
Test status
Simulation time 342603595 ps
CPU time 1.37 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:17 PM PDT 24
Peak memory 201868 kb
Host smart-8546724d-e4d9-476d-9f63-ef8a1c1d7602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109564272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4109564272
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1376363687
Short name T283
Test name
Test status
Simulation time 356719280189 ps
CPU time 673.5 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:24:31 PM PDT 24
Peak memory 202172 kb
Host smart-26187edb-86a6-43ac-8e14-c3512fe2cdbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376363687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1376363687
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.113023805
Short name T648
Test name
Test status
Simulation time 163359752596 ps
CPU time 368.26 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:19:56 PM PDT 24
Peak memory 202076 kb
Host smart-4fa0353c-2028-4f52-9f3c-3466e540c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113023805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.113023805
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2747389913
Short name T710
Test name
Test status
Simulation time 163267889260 ps
CPU time 355.05 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:19:11 PM PDT 24
Peak memory 202152 kb
Host smart-8ae1b533-8c90-43b3-a172-212788d2336e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747389913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2747389913
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1977318668
Short name T712
Test name
Test status
Simulation time 336142298028 ps
CPU time 170.54 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:16:06 PM PDT 24
Peak memory 202044 kb
Host smart-1ce7fa28-d513-4f9d-8618-10858cd6d5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977318668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1977318668
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.327692504
Short name T708
Test name
Test status
Simulation time 332332474284 ps
CPU time 718.06 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:25:22 PM PDT 24
Peak memory 202060 kb
Host smart-9eaea299-b9c5-4f93-ba8f-ad125088e3ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=327692504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.327692504
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3473854484
Short name T238
Test name
Test status
Simulation time 177877575458 ps
CPU time 186.32 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:16:25 PM PDT 24
Peak memory 202096 kb
Host smart-8db11b5f-672e-4843-9041-f52d1708b525
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473854484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3473854484
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2402018534
Short name T434
Test name
Test status
Simulation time 404559208413 ps
CPU time 239.16 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:17:22 PM PDT 24
Peak memory 202080 kb
Host smart-b48c80af-5782-4473-8218-e41e8dba5bf1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402018534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2402018534
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.274239869
Short name T197
Test name
Test status
Simulation time 82270943073 ps
CPU time 403.82 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:19:57 PM PDT 24
Peak memory 202328 kb
Host smart-830c0656-882a-45b8-ad63-9aac227026c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274239869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.274239869
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1579714430
Short name T586
Test name
Test status
Simulation time 42238462253 ps
CPU time 5.54 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:13:27 PM PDT 24
Peak memory 201900 kb
Host smart-0edee995-a45f-4601-b549-386e86958a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579714430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1579714430
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4203486922
Short name T661
Test name
Test status
Simulation time 5128546474 ps
CPU time 1.87 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:13:25 PM PDT 24
Peak memory 201920 kb
Host smart-edde3d6e-04be-4fe8-8c13-25cd95abdfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203486922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4203486922
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1309919251
Short name T107
Test name
Test status
Simulation time 5927001328 ps
CPU time 7.17 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:13:18 PM PDT 24
Peak memory 202032 kb
Host smart-f43139b4-92b9-45c2-8fa7-285da7b25e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309919251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1309919251
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.4211871654
Short name T717
Test name
Test status
Simulation time 238928368976 ps
CPU time 461.5 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:20:53 PM PDT 24
Peak memory 202028 kb
Host smart-3e8cb542-bd60-42af-ba34-d63b6c9000c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211871654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.4211871654
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4105183343
Short name T40
Test name
Test status
Simulation time 8843938726 ps
CPU time 14.87 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 210640 kb
Host smart-1d8b412d-7544-4118-96a5-0bd5e9efd0ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105183343 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4105183343
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2591147392
Short name T384
Test name
Test status
Simulation time 459102247 ps
CPU time 1.15 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 201992 kb
Host smart-b1c92e45-d0c5-4c7a-be6a-0fbe8caf69b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591147392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2591147392
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3711229237
Short name T747
Test name
Test status
Simulation time 332387319143 ps
CPU time 390.04 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:19:43 PM PDT 24
Peak memory 202152 kb
Host smart-bb564099-b4f1-4ea1-8957-ca4a083a8eea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711229237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3711229237
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1213159095
Short name T262
Test name
Test status
Simulation time 345835084260 ps
CPU time 737.46 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:25:42 PM PDT 24
Peak memory 202092 kb
Host smart-007b288c-47e0-4235-ba63-66ac6eb60040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213159095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1213159095
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.502786333
Short name T258
Test name
Test status
Simulation time 164427000737 ps
CPU time 32.91 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:52 PM PDT 24
Peak memory 202128 kb
Host smart-33eca4fb-a385-437d-8821-362e9abcda25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502786333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.502786333
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.951508038
Short name T760
Test name
Test status
Simulation time 160451967294 ps
CPU time 185.46 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:16:20 PM PDT 24
Peak memory 202016 kb
Host smart-7fc39f9e-da60-401f-9e36-2abb30b8e292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=951508038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.951508038
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1757553511
Short name T131
Test name
Test status
Simulation time 324058033706 ps
CPU time 739.33 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:25:41 PM PDT 24
Peak memory 202016 kb
Host smart-00068cb2-5932-464c-bc7c-bff234e0592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757553511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1757553511
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.126080717
Short name T770
Test name
Test status
Simulation time 160946222936 ps
CPU time 341.48 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:18:57 PM PDT 24
Peak memory 201996 kb
Host smart-3139adec-2444-43c1-9fa2-fbfdb5d20e29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=126080717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.126080717
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.890553054
Short name T290
Test name
Test status
Simulation time 412629504599 ps
CPU time 119.67 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:15:15 PM PDT 24
Peak memory 202028 kb
Host smart-fcc39821-b2fb-42fc-a52d-f67b0cf92192
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890553054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.890553054
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3111576376
Short name T733
Test name
Test status
Simulation time 203442142950 ps
CPU time 52.89 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:14:04 PM PDT 24
Peak memory 202072 kb
Host smart-3b607774-5452-4d63-b89e-8dc30e511035
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111576376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3111576376
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.203431526
Short name T48
Test name
Test status
Simulation time 78316109362 ps
CPU time 280.87 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:17:53 PM PDT 24
Peak memory 202368 kb
Host smart-5a3e546a-2e2c-4b7b-8077-2567c692e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203431526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.203431526
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1934202274
Short name T701
Test name
Test status
Simulation time 29624065955 ps
CPU time 17.91 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:33 PM PDT 24
Peak memory 202048 kb
Host smart-8081d95b-bccd-4bdd-b05e-b1bdeb676e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934202274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1934202274
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2721751186
Short name T521
Test name
Test status
Simulation time 4372026834 ps
CPU time 4.08 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201844 kb
Host smart-689c1873-e056-495a-bb81-d1c34649b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721751186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2721751186
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2079686948
Short name T381
Test name
Test status
Simulation time 5859512520 ps
CPU time 7.6 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:22 PM PDT 24
Peak memory 201936 kb
Host smart-6bc248f6-dddf-4a39-adf1-ea8e1bcbeb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079686948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2079686948
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3858128627
Short name T37
Test name
Test status
Simulation time 165476938623 ps
CPU time 203.18 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:16:37 PM PDT 24
Peak memory 200544 kb
Host smart-e8f021fc-f40f-41e3-874a-e600e19adfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858128627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3858128627
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1084740586
Short name T8
Test name
Test status
Simulation time 6352269696 ps
CPU time 13.97 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:13:32 PM PDT 24
Peak memory 211520 kb
Host smart-8162ee84-1c16-44c2-a943-1abb0252bf5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084740586 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1084740586
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4027545729
Short name T487
Test name
Test status
Simulation time 532993152 ps
CPU time 1.86 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:17 PM PDT 24
Peak memory 201924 kb
Host smart-5eff056b-dda3-4b30-9c55-1071e9907f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027545729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4027545729
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2477104222
Short name T771
Test name
Test status
Simulation time 157736895033 ps
CPU time 20.96 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:13:50 PM PDT 24
Peak memory 202100 kb
Host smart-370271ad-f4ac-4920-9df1-a47495c9ca5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477104222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2477104222
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1630438907
Short name T234
Test name
Test status
Simulation time 328716887578 ps
CPU time 750.93 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:25:47 PM PDT 24
Peak memory 201860 kb
Host smart-a382d4b9-be9d-4cba-a66a-12a81a3102fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630438907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1630438907
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2151045142
Short name T173
Test name
Test status
Simulation time 491692177822 ps
CPU time 545.18 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:22:22 PM PDT 24
Peak memory 202120 kb
Host smart-48c54a23-9c53-47e3-9826-30965b095206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151045142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2151045142
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.193828312
Short name T790
Test name
Test status
Simulation time 157058310625 ps
CPU time 52.31 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:14:16 PM PDT 24
Peak memory 202096 kb
Host smart-175fa0de-d976-4d5e-8967-9fde11303270
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=193828312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.193828312
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4025890514
Short name T257
Test name
Test status
Simulation time 328295311008 ps
CPU time 400.25 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:20:00 PM PDT 24
Peak memory 202072 kb
Host smart-9e1403de-a46e-4b82-81f1-4c10b621ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025890514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4025890514
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1190813907
Short name T536
Test name
Test status
Simulation time 323026686698 ps
CPU time 685.18 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:24:39 PM PDT 24
Peak memory 202088 kb
Host smart-c023c094-d3e8-4275-af6f-430c48468875
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190813907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1190813907
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1468159914
Short name T241
Test name
Test status
Simulation time 367591808037 ps
CPU time 857.38 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:27:32 PM PDT 24
Peak memory 202032 kb
Host smart-0f266d3e-6df9-4d44-92e6-a6532e502891
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468159914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1468159914
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4227703090
Short name T493
Test name
Test status
Simulation time 408157243794 ps
CPU time 863.75 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:27:40 PM PDT 24
Peak memory 202112 kb
Host smart-860aa5a5-643b-4520-ab55-35262ab96386
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227703090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4227703090
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3197787576
Short name T195
Test name
Test status
Simulation time 148360257773 ps
CPU time 436.18 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:20:38 PM PDT 24
Peak memory 202328 kb
Host smart-bc1d4cc6-1470-475f-8729-00aa7266a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197787576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3197787576
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3304965464
Short name T4
Test name
Test status
Simulation time 37014776731 ps
CPU time 13.64 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 201880 kb
Host smart-512265a4-3123-4b08-8a32-71777777b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304965464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3304965464
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3679871133
Short name T108
Test name
Test status
Simulation time 4518515300 ps
CPU time 5.53 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:13:31 PM PDT 24
Peak memory 201916 kb
Host smart-291b7f1e-1717-459f-ad3c-8a05df2be737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679871133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3679871133
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.932188263
Short name T672
Test name
Test status
Simulation time 5634198170 ps
CPU time 12.19 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:13:36 PM PDT 24
Peak memory 201912 kb
Host smart-228a81ea-db41-44e3-982f-aaa6de16dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932188263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.932188263
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3745759978
Short name T5
Test name
Test status
Simulation time 6434787633 ps
CPU time 14.96 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:13:31 PM PDT 24
Peak memory 201840 kb
Host smart-edd95908-826e-4a00-95cd-c0b5cfa0ff25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745759978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3745759978
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2682512551
Short name T42
Test name
Test status
Simulation time 1574871087 ps
CPU time 4.54 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:13:21 PM PDT 24
Peak memory 201876 kb
Host smart-51acc68b-ee9a-420c-9b28-61c560a5e5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682512551 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2682512551
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1679497531
Short name T15
Test name
Test status
Simulation time 358585719 ps
CPU time 0.78 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:13:18 PM PDT 24
Peak memory 201920 kb
Host smart-06ce71e1-e6ff-4ebf-b06a-db91b2c229cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679497531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1679497531
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.484363893
Short name T319
Test name
Test status
Simulation time 377043138637 ps
CPU time 115.59 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:15:10 PM PDT 24
Peak memory 202192 kb
Host smart-09b8655d-aaf8-40e8-b07a-ae8ac6cb7b6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484363893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.484363893
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.937858881
Short name T261
Test name
Test status
Simulation time 166718231301 ps
CPU time 175.25 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:16:12 PM PDT 24
Peak memory 202068 kb
Host smart-c615d4cb-8afd-40b2-b87d-a39e218224d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937858881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.937858881
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.235808380
Short name T699
Test name
Test status
Simulation time 169021389843 ps
CPU time 94.7 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:14:49 PM PDT 24
Peak memory 202000 kb
Host smart-f919e36c-98d0-4d8d-9e3d-aad095b2bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235808380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.235808380
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1502413614
Short name T474
Test name
Test status
Simulation time 490962403965 ps
CPU time 569.1 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:22:59 PM PDT 24
Peak memory 202140 kb
Host smart-4dfdf8c3-65ce-421f-a075-4863559729cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502413614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1502413614
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3164974669
Short name T322
Test name
Test status
Simulation time 493489676122 ps
CPU time 1121.08 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:31:53 PM PDT 24
Peak memory 202088 kb
Host smart-38de382d-7669-4f9f-a3c9-d59e89919955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164974669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3164974669
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3256825490
Short name T484
Test name
Test status
Simulation time 334922661810 ps
CPU time 737.51 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:25:33 PM PDT 24
Peak memory 202012 kb
Host smart-fc36e15b-59a0-4659-83c9-46b89b736a55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256825490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3256825490
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.614426905
Short name T240
Test name
Test status
Simulation time 185500818413 ps
CPU time 154.48 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:15:53 PM PDT 24
Peak memory 202156 kb
Host smart-48fc0848-8079-484e-9e6a-af134004beb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614426905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.614426905
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3909208108
Short name T106
Test name
Test status
Simulation time 411563306129 ps
CPU time 494.57 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:21:38 PM PDT 24
Peak memory 202092 kb
Host smart-ee9ac5b1-913e-4f51-864a-79e3075cf931
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909208108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3909208108
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4112136522
Short name T643
Test name
Test status
Simulation time 99970547459 ps
CPU time 385.57 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:19:37 PM PDT 24
Peak memory 202328 kb
Host smart-2dc4864c-a313-4fe9-84bc-8e344e17ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112136522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4112136522
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4112822112
Short name T405
Test name
Test status
Simulation time 28995760132 ps
CPU time 14.61 seconds
Started Aug 16 05:13:20 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 201860 kb
Host smart-e0b9e3d7-a6d0-498c-9a11-c330712c8deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112822112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4112822112
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3240197236
Short name T535
Test name
Test status
Simulation time 3774038558 ps
CPU time 9.31 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:13:32 PM PDT 24
Peak memory 201900 kb
Host smart-fbf1bd03-37eb-4156-8140-3d681fccc694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240197236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3240197236
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1615789302
Short name T681
Test name
Test status
Simulation time 5836307762 ps
CPU time 13.44 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:13:29 PM PDT 24
Peak memory 201904 kb
Host smart-95625b1b-8f62-4dc7-bb31-8b36ad29efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615789302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1615789302
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1417353220
Short name T136
Test name
Test status
Simulation time 320009179531 ps
CPU time 203.37 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:16:43 PM PDT 24
Peak memory 202000 kb
Host smart-f680f876-6db1-4fa2-8910-7a9c34324b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417353220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1417353220
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4197889289
Short name T674
Test name
Test status
Simulation time 4247546291 ps
CPU time 5.22 seconds
Started Aug 16 05:13:28 PM PDT 24
Finished Aug 16 05:13:33 PM PDT 24
Peak memory 202228 kb
Host smart-d913edc3-2a0f-4683-8266-a32a790636c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197889289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4197889289
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2450624487
Short name T402
Test name
Test status
Simulation time 445895726 ps
CPU time 1.59 seconds
Started Aug 16 05:12:54 PM PDT 24
Finished Aug 16 05:12:56 PM PDT 24
Peak memory 201956 kb
Host smart-b5e02768-e356-4d44-94d5-21c61597e458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450624487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2450624487
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.527234034
Short name T741
Test name
Test status
Simulation time 165054015276 ps
CPU time 100.86 seconds
Started Aug 16 05:12:51 PM PDT 24
Finished Aug 16 05:14:32 PM PDT 24
Peak memory 202084 kb
Host smart-17fec1a1-2327-487f-a192-7cee171b6ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527234034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.527234034
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2400411644
Short name T220
Test name
Test status
Simulation time 481120056953 ps
CPU time 315.23 seconds
Started Aug 16 05:12:52 PM PDT 24
Finished Aug 16 05:18:07 PM PDT 24
Peak memory 202052 kb
Host smart-753e629f-1918-4460-8c4f-36bf58a11446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400411644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2400411644
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2605324118
Short name T798
Test name
Test status
Simulation time 489724951684 ps
CPU time 257.02 seconds
Started Aug 16 05:12:54 PM PDT 24
Finished Aug 16 05:17:11 PM PDT 24
Peak memory 202060 kb
Host smart-83f1322f-ad51-4263-acb4-b41a257deecb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605324118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2605324118
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3071634322
Short name T763
Test name
Test status
Simulation time 163849575173 ps
CPU time 206.39 seconds
Started Aug 16 05:12:48 PM PDT 24
Finished Aug 16 05:16:15 PM PDT 24
Peak memory 202128 kb
Host smart-ce17b8c8-663d-4714-b8e9-f3a893e81105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071634322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3071634322
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2758872603
Short name T722
Test name
Test status
Simulation time 161229443362 ps
CPU time 276.04 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:17:33 PM PDT 24
Peak memory 201988 kb
Host smart-f3119fce-bfb0-4c01-801d-7dbaff9d1e47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758872603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2758872603
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3849682325
Short name T558
Test name
Test status
Simulation time 170901006994 ps
CPU time 85.99 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:14:26 PM PDT 24
Peak memory 201968 kb
Host smart-014222d6-0814-4e09-93bc-a7a1b6e11da2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849682325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3849682325
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3491430311
Short name T570
Test name
Test status
Simulation time 397421076806 ps
CPU time 940.9 seconds
Started Aug 16 05:12:49 PM PDT 24
Finished Aug 16 05:28:30 PM PDT 24
Peak memory 202092 kb
Host smart-36039b99-bd3b-478a-9e34-b16941906047
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491430311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3491430311
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3257872272
Short name T31
Test name
Test status
Simulation time 115508180892 ps
CPU time 670.2 seconds
Started Aug 16 05:12:37 PM PDT 24
Finished Aug 16 05:23:47 PM PDT 24
Peak memory 202384 kb
Host smart-c6916963-7d72-490f-bc36-6ea831755d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257872272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3257872272
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.835459747
Short name T495
Test name
Test status
Simulation time 32746833909 ps
CPU time 40.67 seconds
Started Aug 16 05:12:44 PM PDT 24
Finished Aug 16 05:13:25 PM PDT 24
Peak memory 201996 kb
Host smart-af81259c-1a71-4a36-b849-23ff5975dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835459747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.835459747
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2277625013
Short name T491
Test name
Test status
Simulation time 4913177501 ps
CPU time 3.41 seconds
Started Aug 16 05:12:37 PM PDT 24
Finished Aug 16 05:12:41 PM PDT 24
Peak memory 201900 kb
Host smart-12940a26-bda5-44e9-a8aa-ec432d47889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277625013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2277625013
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3920530613
Short name T84
Test name
Test status
Simulation time 4333390143 ps
CPU time 11.21 seconds
Started Aug 16 05:12:36 PM PDT 24
Finished Aug 16 05:12:48 PM PDT 24
Peak memory 217412 kb
Host smart-3e6d2ff5-f76a-4bd1-a757-0c05cdda40d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920530613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3920530613
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2202800205
Short name T475
Test name
Test status
Simulation time 5952557493 ps
CPU time 4.37 seconds
Started Aug 16 05:13:00 PM PDT 24
Finished Aug 16 05:13:05 PM PDT 24
Peak memory 201984 kb
Host smart-baa52211-ae51-4e5d-9a8f-973f902de055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202800205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2202800205
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.436246431
Short name T626
Test name
Test status
Simulation time 205751516522 ps
CPU time 465.9 seconds
Started Aug 16 05:12:54 PM PDT 24
Finished Aug 16 05:20:40 PM PDT 24
Peak memory 202108 kb
Host smart-66d550f9-bf23-4e81-9835-bcb8c6b33b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436246431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.436246431
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3692317028
Short name T719
Test name
Test status
Simulation time 4953628238 ps
CPU time 14.41 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:13:12 PM PDT 24
Peak memory 210480 kb
Host smart-2e265757-b25d-4a6e-a9e8-9f55ec4f72b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692317028 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3692317028
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1730872143
Short name T756
Test name
Test status
Simulation time 487979566 ps
CPU time 0.96 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201920 kb
Host smart-a391a746-bd8c-40cf-aeb5-c0d2ce720aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730872143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1730872143
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3038881334
Short name T169
Test name
Test status
Simulation time 165130094360 ps
CPU time 84.79 seconds
Started Aug 16 05:13:39 PM PDT 24
Finished Aug 16 05:15:04 PM PDT 24
Peak memory 202052 kb
Host smart-e7f5f823-5d37-40d2-a59f-94b48ba1cf7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038881334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3038881334
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2393023004
Short name T608
Test name
Test status
Simulation time 161716933108 ps
CPU time 133.85 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:15:35 PM PDT 24
Peak memory 202156 kb
Host smart-36553196-ab56-4628-842d-439372c68298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393023004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2393023004
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1779471629
Short name T266
Test name
Test status
Simulation time 332469547661 ps
CPU time 780.06 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:26:22 PM PDT 24
Peak memory 202108 kb
Host smart-07082b93-05c8-4153-81e3-26b25b430195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779471629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1779471629
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2916639455
Short name T43
Test name
Test status
Simulation time 491905755418 ps
CPU time 1170.35 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:32:52 PM PDT 24
Peak memory 202092 kb
Host smart-90014995-44c0-424b-8f27-f2a61e667a8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916639455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2916639455
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.530769649
Short name T788
Test name
Test status
Simulation time 339743372578 ps
CPU time 723.59 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:25:26 PM PDT 24
Peak memory 202128 kb
Host smart-da8c19f7-b3ee-492c-bc95-f0b6c3e59f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530769649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.530769649
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2430243994
Short name T779
Test name
Test status
Simulation time 492272533783 ps
CPU time 302.2 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:18:16 PM PDT 24
Peak memory 202136 kb
Host smart-ad646f4c-ae2c-4297-8069-fcd9b491e44d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430243994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2430243994
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2392333804
Short name T340
Test name
Test status
Simulation time 549162007224 ps
CPU time 1255.57 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:34:21 PM PDT 24
Peak memory 202096 kb
Host smart-9fbaa0ba-267f-4613-ab94-e210a4bf176f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392333804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2392333804
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2382083623
Short name T698
Test name
Test status
Simulation time 595599881692 ps
CPU time 1458.44 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:37:48 PM PDT 24
Peak memory 202052 kb
Host smart-ba5aa193-89ec-48b3-9658-7a0fcb7eaf07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382083623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2382083623
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3488407252
Short name T472
Test name
Test status
Simulation time 32128741307 ps
CPU time 11.31 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:13:34 PM PDT 24
Peak memory 201916 kb
Host smart-5615f0b3-415d-4d0e-9ca5-3bfd1e9719c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488407252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3488407252
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2388542852
Short name T603
Test name
Test status
Simulation time 2999057180 ps
CPU time 4.21 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201932 kb
Host smart-3a5789fc-badc-451e-a9db-8e9ec02e69dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388542852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2388542852
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1760497956
Short name T420
Test name
Test status
Simulation time 5722226311 ps
CPU time 13.14 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:13:37 PM PDT 24
Peak memory 201904 kb
Host smart-ae85d6b3-6f89-47c3-b594-579e3687370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760497956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1760497956
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3815189907
Short name T274
Test name
Test status
Simulation time 503701421488 ps
CPU time 287.64 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:18:00 PM PDT 24
Peak memory 202100 kb
Host smart-a338fdbb-640a-4936-855d-7ba40ccf5f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815189907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3815189907
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1862339774
Short name T188
Test name
Test status
Simulation time 21046449783 ps
CPU time 19.95 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:34 PM PDT 24
Peak memory 210752 kb
Host smart-f4bbf05b-5057-434d-9ecf-fbd2b0d7b549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862339774 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1862339774
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2554866522
Short name T697
Test name
Test status
Simulation time 373646095 ps
CPU time 1.01 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 201912 kb
Host smart-0c1db16c-fa23-44c5-a33f-9697c9b9f0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554866522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2554866522
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4139095132
Short name T217
Test name
Test status
Simulation time 160750615143 ps
CPU time 94.44 seconds
Started Aug 16 05:13:18 PM PDT 24
Finished Aug 16 05:14:53 PM PDT 24
Peak memory 202160 kb
Host smart-2a50897c-78f6-4283-9f97-58c5ea184751
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139095132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4139095132
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4017016877
Short name T103
Test name
Test status
Simulation time 165418420571 ps
CPU time 86.6 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:14:50 PM PDT 24
Peak memory 202064 kb
Host smart-0bda8475-bb03-4c42-9e87-36a904a99729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017016877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4017016877
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.88850721
Short name T448
Test name
Test status
Simulation time 494942914877 ps
CPU time 542.01 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:22:24 PM PDT 24
Peak memory 202084 kb
Host smart-e7a5abe9-db89-4427-9784-12e158999d98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=88850721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt
_fixed.88850721
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2018087200
Short name T216
Test name
Test status
Simulation time 321280213997 ps
CPU time 238.29 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:17:21 PM PDT 24
Peak memory 202124 kb
Host smart-792ad294-343d-4c6a-b329-edfdfb4abfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018087200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2018087200
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2859537192
Short name T656
Test name
Test status
Simulation time 485846318259 ps
CPU time 276.76 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:17:54 PM PDT 24
Peak memory 202108 kb
Host smart-661a927f-5548-49c2-8dd1-043aa628a8c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859537192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2859537192
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.242647202
Short name T634
Test name
Test status
Simulation time 181056589033 ps
CPU time 426.82 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:20:32 PM PDT 24
Peak memory 202068 kb
Host smart-3729e441-7b9d-4007-a92e-95e3a3d59f24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242647202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.242647202
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4238856954
Short name T653
Test name
Test status
Simulation time 608700869660 ps
CPU time 186.98 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:16:29 PM PDT 24
Peak memory 202108 kb
Host smart-5c19a486-4333-4bf7-8258-a7b587822700
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238856954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4238856954
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.963967538
Short name T196
Test name
Test status
Simulation time 80496225745 ps
CPU time 420.47 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:20:23 PM PDT 24
Peak memory 202392 kb
Host smart-7e7ef76b-6c19-4a72-b29f-6dca10068fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963967538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.963967538
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2788407933
Short name T419
Test name
Test status
Simulation time 36158225778 ps
CPU time 11.47 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 201908 kb
Host smart-9691522f-fa3b-47b1-913e-d307e0eb1ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788407933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2788407933
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3201499483
Short name T610
Test name
Test status
Simulation time 4355958771 ps
CPU time 2.39 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:13:46 PM PDT 24
Peak memory 201896 kb
Host smart-12da75a9-4d96-4291-9a99-4d0102f37d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201499483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3201499483
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.774312956
Short name T703
Test name
Test status
Simulation time 5828832592 ps
CPU time 4.32 seconds
Started Aug 16 05:13:19 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 201896 kb
Host smart-251c9dfb-50d5-4588-8deb-8d3c63c0ec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774312956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.774312956
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.956454090
Short name T35
Test name
Test status
Simulation time 1190154779 ps
CPU time 3.69 seconds
Started Aug 16 05:13:28 PM PDT 24
Finished Aug 16 05:13:32 PM PDT 24
Peak memory 201992 kb
Host smart-42bf48bb-5e66-41f8-b77a-f6bd45505444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956454090 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.956454090
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2868094798
Short name T469
Test name
Test status
Simulation time 484810812 ps
CPU time 1.59 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 201936 kb
Host smart-04858407-e56e-4c13-a538-3b95ab95f969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868094798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2868094798
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4048838826
Short name T252
Test name
Test status
Simulation time 164029069079 ps
CPU time 383.93 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:19:50 PM PDT 24
Peak memory 202084 kb
Host smart-be4329c4-613b-452c-965d-fa3cf355a48e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048838826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4048838826
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3557190185
Short name T163
Test name
Test status
Simulation time 332739569958 ps
CPU time 205.52 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:16:52 PM PDT 24
Peak memory 202144 kb
Host smart-82cd6ad4-7cd2-4d03-bf43-e37fe097ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557190185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3557190185
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2023898438
Short name T426
Test name
Test status
Simulation time 329039645741 ps
CPU time 194.35 seconds
Started Aug 16 05:13:36 PM PDT 24
Finished Aug 16 05:16:50 PM PDT 24
Peak memory 202084 kb
Host smart-6ae141b3-849f-4cbf-b5ef-9f31f3d391d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023898438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2023898438
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1441960029
Short name T573
Test name
Test status
Simulation time 162348110166 ps
CPU time 60.17 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:14:26 PM PDT 24
Peak memory 202068 kb
Host smart-782a2169-f579-4b34-93e1-48545a5059e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441960029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1441960029
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2492894206
Short name T158
Test name
Test status
Simulation time 493244755235 ps
CPU time 223.4 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:17:10 PM PDT 24
Peak memory 201936 kb
Host smart-f352a9b0-3e80-4ddf-96df-5ce6e4d7e67c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492894206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2492894206
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3812962432
Short name T209
Test name
Test status
Simulation time 197916758556 ps
CPU time 443.67 seconds
Started Aug 16 05:13:32 PM PDT 24
Finished Aug 16 05:20:56 PM PDT 24
Peak memory 202068 kb
Host smart-8af8ddaa-ab68-483d-8bfd-15a4f0382ce2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812962432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3812962432
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1363927336
Short name T408
Test name
Test status
Simulation time 396862879150 ps
CPU time 188.15 seconds
Started Aug 16 05:13:32 PM PDT 24
Finished Aug 16 05:16:41 PM PDT 24
Peak memory 202064 kb
Host smart-861992ef-d90e-41d6-8178-8c33dbce7d33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363927336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1363927336
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1168060562
Short name T757
Test name
Test status
Simulation time 23990947945 ps
CPU time 26.15 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:13:55 PM PDT 24
Peak memory 201928 kb
Host smart-8f325495-07d6-448a-a4a6-74c9ae81c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168060562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1168060562
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2643619616
Short name T609
Test name
Test status
Simulation time 3731764159 ps
CPU time 8.56 seconds
Started Aug 16 05:13:31 PM PDT 24
Finished Aug 16 05:13:40 PM PDT 24
Peak memory 201888 kb
Host smart-372b21d5-7fba-4436-8298-c13cc57172cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643619616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2643619616
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3815745008
Short name T646
Test name
Test status
Simulation time 5920014438 ps
CPU time 5.69 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 201892 kb
Host smart-351e5de6-8c87-4d2c-9f37-876c99d52fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815745008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3815745008
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1935424764
Short name T313
Test name
Test status
Simulation time 344240536598 ps
CPU time 208.29 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:17:12 PM PDT 24
Peak memory 202132 kb
Host smart-634f7770-44d9-4817-afb4-30e2b5efee67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935424764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1935424764
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.628940724
Short name T684
Test name
Test status
Simulation time 1780352890 ps
CPU time 14.08 seconds
Started Aug 16 05:13:27 PM PDT 24
Finished Aug 16 05:13:41 PM PDT 24
Peak memory 210620 kb
Host smart-e5ec56a7-fc0d-40c7-9e9c-aa09fb746c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628940724 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.628940724
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2915088370
Short name T794
Test name
Test status
Simulation time 531519146 ps
CPU time 0.93 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201924 kb
Host smart-ef97a92b-e1fe-4fb2-938a-cbaaf8b0d383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915088370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2915088370
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1451011582
Short name T614
Test name
Test status
Simulation time 162019559208 ps
CPU time 357.5 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:19:22 PM PDT 24
Peak memory 202068 kb
Host smart-fbe73586-bec3-4716-ab67-92fd4b32b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451011582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1451011582
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.81006673
Short name T430
Test name
Test status
Simulation time 164627895186 ps
CPU time 90.71 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:14:57 PM PDT 24
Peak memory 202040 kb
Host smart-923cc9d8-3874-4887-a3e7-9f41a17b00c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=81006673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt
_fixed.81006673
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2106188302
Short name T780
Test name
Test status
Simulation time 165231078898 ps
CPU time 59.41 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:14:23 PM PDT 24
Peak memory 202060 kb
Host smart-c2059b30-9385-4c38-bf0e-0fa34b576e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106188302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2106188302
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2521486715
Short name T714
Test name
Test status
Simulation time 166736886593 ps
CPU time 390.79 seconds
Started Aug 16 05:13:21 PM PDT 24
Finished Aug 16 05:19:52 PM PDT 24
Peak memory 202096 kb
Host smart-5761da98-843e-4489-bf5d-e6e4d2a9296e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521486715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2521486715
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2093649777
Short name T267
Test name
Test status
Simulation time 350964185537 ps
CPU time 713.8 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:25:41 PM PDT 24
Peak memory 202104 kb
Host smart-0518e077-f880-430b-aa71-b4b070bff1fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093649777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2093649777
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.657385693
Short name T618
Test name
Test status
Simulation time 619326465295 ps
CPU time 1450.89 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:37:35 PM PDT 24
Peak memory 202116 kb
Host smart-fdb90a93-ca43-4d1e-824c-232de44c29d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657385693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.657385693
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1311583028
Short name T694
Test name
Test status
Simulation time 83590628015 ps
CPU time 314.28 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:18:58 PM PDT 24
Peak memory 202364 kb
Host smart-1bc83ce5-5a47-4b14-ac67-c9f08741a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311583028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1311583028
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2102887536
Short name T735
Test name
Test status
Simulation time 44068545940 ps
CPU time 26.4 seconds
Started Aug 16 05:13:25 PM PDT 24
Finished Aug 16 05:13:52 PM PDT 24
Peak memory 201892 kb
Host smart-af3fe49d-f2df-4508-b8dd-376d5de64c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102887536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2102887536
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1923561915
Short name T619
Test name
Test status
Simulation time 5408488152 ps
CPU time 5.29 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:13:30 PM PDT 24
Peak memory 201836 kb
Host smart-28cebb06-890f-44cb-8bc5-f14c3dc81247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923561915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1923561915
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3206789417
Short name T411
Test name
Test status
Simulation time 5767101801 ps
CPU time 14.15 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:13:38 PM PDT 24
Peak memory 201908 kb
Host smart-776aecaa-a78d-431a-ad62-d898bd7f13c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206789417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3206789417
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2055223276
Short name T272
Test name
Test status
Simulation time 187302226118 ps
CPU time 112.69 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:15:17 PM PDT 24
Peak memory 202060 kb
Host smart-7025a6fc-dc30-4a5f-adf8-aed530b3d33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055223276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2055223276
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1741414558
Short name T518
Test name
Test status
Simulation time 6080291212 ps
CPU time 11.3 seconds
Started Aug 16 05:13:22 PM PDT 24
Finished Aug 16 05:13:33 PM PDT 24
Peak memory 210604 kb
Host smart-202b4f3e-4cc1-46d3-8cfc-5a35158ea3bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741414558 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1741414558
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.615052331
Short name T499
Test name
Test status
Simulation time 307685632 ps
CPU time 1.3 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:13:26 PM PDT 24
Peak memory 201884 kb
Host smart-21026dbc-9caa-41b9-9b48-fd13866771ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615052331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.615052331
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3972055193
Short name T246
Test name
Test status
Simulation time 167063501877 ps
CPU time 89.74 seconds
Started Aug 16 05:13:36 PM PDT 24
Finished Aug 16 05:15:06 PM PDT 24
Peak memory 202056 kb
Host smart-5d7fff4f-6a6c-458b-b444-9428440f064b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972055193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3972055193
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3643824260
Short name T161
Test name
Test status
Simulation time 327921232869 ps
CPU time 263.34 seconds
Started Aug 16 05:13:27 PM PDT 24
Finished Aug 16 05:17:51 PM PDT 24
Peak memory 202128 kb
Host smart-9bbc8d4a-ad8f-48ce-a561-23b5a1ace26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643824260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3643824260
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4076665023
Short name T320
Test name
Test status
Simulation time 487254335259 ps
CPU time 1131.53 seconds
Started Aug 16 05:13:27 PM PDT 24
Finished Aug 16 05:32:18 PM PDT 24
Peak memory 202052 kb
Host smart-4033260e-e73d-41c5-a144-cd85686ebc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076665023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4076665023
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.54438546
Short name T585
Test name
Test status
Simulation time 160799548190 ps
CPU time 167.36 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:16:17 PM PDT 24
Peak memory 202040 kb
Host smart-a7832d25-7f05-408f-b5f0-132f1ff9f16d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=54438546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt
_fixed.54438546
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1320125120
Short name T141
Test name
Test status
Simulation time 336466552676 ps
CPU time 137.77 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:15:44 PM PDT 24
Peak memory 201928 kb
Host smart-7bdc370c-f98c-4890-8b1c-a6b61e7b2363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320125120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1320125120
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4239513908
Short name T689
Test name
Test status
Simulation time 494163899011 ps
CPU time 274.67 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:18:01 PM PDT 24
Peak memory 202080 kb
Host smart-3e23aa9d-78f3-4d6e-a43d-12e9afdae03b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239513908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4239513908
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3622833067
Short name T331
Test name
Test status
Simulation time 629937700103 ps
CPU time 775.27 seconds
Started Aug 16 05:13:23 PM PDT 24
Finished Aug 16 05:26:19 PM PDT 24
Peak memory 202108 kb
Host smart-e54850f0-62cf-4e27-881e-cd5a31b29332
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622833067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3622833067
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4076339674
Short name T105
Test name
Test status
Simulation time 609002926516 ps
CPU time 335.62 seconds
Started Aug 16 05:13:24 PM PDT 24
Finished Aug 16 05:19:00 PM PDT 24
Peak memory 202092 kb
Host smart-c59ee97d-1702-4abd-ae82-836df746327b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076339674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4076339674
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3760112058
Short name T636
Test name
Test status
Simulation time 24686324571 ps
CPU time 29.72 seconds
Started Aug 16 05:13:33 PM PDT 24
Finished Aug 16 05:14:03 PM PDT 24
Peak memory 201840 kb
Host smart-59e7647d-83a9-438c-adeb-35802a2eec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760112058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3760112058
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4216869119
Short name T551
Test name
Test status
Simulation time 4072718518 ps
CPU time 3.05 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:13:46 PM PDT 24
Peak memory 201904 kb
Host smart-7d77a153-69d7-413e-830e-9655e8202300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216869119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4216869119
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.486952065
Short name T510
Test name
Test status
Simulation time 5547784095 ps
CPU time 2.01 seconds
Started Aug 16 05:13:45 PM PDT 24
Finished Aug 16 05:13:47 PM PDT 24
Peak memory 201848 kb
Host smart-ac6d97cb-0c5a-4efd-96a1-6922b40fc3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486952065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.486952065
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3757263154
Short name T192
Test name
Test status
Simulation time 1121187377420 ps
CPU time 881.61 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:28:25 PM PDT 24
Peak memory 210564 kb
Host smart-09c884fd-163c-4a10-b6cb-347317da14f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757263154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3757263154
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.906567545
Short name T111
Test name
Test status
Simulation time 8327268968 ps
CPU time 14.64 seconds
Started Aug 16 05:13:48 PM PDT 24
Finished Aug 16 05:14:03 PM PDT 24
Peak memory 210440 kb
Host smart-afbbffce-5714-4eb8-838e-273dd47051d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906567545 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.906567545
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1847266853
Short name T361
Test name
Test status
Simulation time 382661963 ps
CPU time 1.32 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:13:41 PM PDT 24
Peak memory 201916 kb
Host smart-3ccaccd1-a6bb-401c-9d6a-debee9c15031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847266853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1847266853
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.525439706
Short name T325
Test name
Test status
Simulation time 164992559092 ps
CPU time 105.73 seconds
Started Aug 16 05:13:36 PM PDT 24
Finished Aug 16 05:15:22 PM PDT 24
Peak memory 202104 kb
Host smart-1b3fefb6-7838-4b2e-83d2-2dfcbeec21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525439706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.525439706
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1888281445
Short name T533
Test name
Test status
Simulation time 328830925089 ps
CPU time 98.74 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:15:19 PM PDT 24
Peak memory 202032 kb
Host smart-6aed3367-b658-4f27-bdae-179f849a32f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888281445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1888281445
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3345720047
Short name T734
Test name
Test status
Simulation time 333017442495 ps
CPU time 737.62 seconds
Started Aug 16 05:13:44 PM PDT 24
Finished Aug 16 05:26:02 PM PDT 24
Peak memory 202024 kb
Host smart-b241df4d-07fe-4e98-bc80-f54f265d592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345720047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3345720047
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.6465688
Short name T537
Test name
Test status
Simulation time 329254696757 ps
CPU time 185.72 seconds
Started Aug 16 05:13:32 PM PDT 24
Finished Aug 16 05:16:38 PM PDT 24
Peak memory 202076 kb
Host smart-15d4a69b-3b76-4ada-a0f0-4f7dc63ad8cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=6465688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.6465688
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1424501453
Short name T324
Test name
Test status
Simulation time 528768519921 ps
CPU time 164.78 seconds
Started Aug 16 05:13:35 PM PDT 24
Finished Aug 16 05:16:20 PM PDT 24
Peak memory 202044 kb
Host smart-4326a461-9c9f-4f2f-89a8-d79e20fae50f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424501453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1424501453
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.580780925
Short name T544
Test name
Test status
Simulation time 208336865057 ps
CPU time 40.66 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:14:12 PM PDT 24
Peak memory 202064 kb
Host smart-09d3ccde-d092-4044-ac0c-08e655a0f680
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580780925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.580780925
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2517478135
Short name T362
Test name
Test status
Simulation time 37692821021 ps
CPU time 85.08 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:14:55 PM PDT 24
Peak memory 201916 kb
Host smart-50611abf-0b8c-496e-9403-de02d114ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517478135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2517478135
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.500663110
Short name T473
Test name
Test status
Simulation time 4120904151 ps
CPU time 6.25 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:13:36 PM PDT 24
Peak memory 201892 kb
Host smart-28f8aacb-ff62-4850-b500-617eac37d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500663110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.500663110
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1674707739
Short name T489
Test name
Test status
Simulation time 6231152824 ps
CPU time 5.53 seconds
Started Aug 16 05:13:26 PM PDT 24
Finished Aug 16 05:13:32 PM PDT 24
Peak memory 201892 kb
Host smart-8f22b147-03db-4153-80ff-a06c04236e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674707739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1674707739
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3551191420
Short name T245
Test name
Test status
Simulation time 363282530789 ps
CPU time 551.96 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:22:58 PM PDT 24
Peak memory 202092 kb
Host smart-9e53a7f0-49e8-4825-8cf9-4d3e94f4aba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551191420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3551191420
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1608837409
Short name T277
Test name
Test status
Simulation time 2354065647 ps
CPU time 6.47 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:13:47 PM PDT 24
Peak memory 202048 kb
Host smart-2b1ed48a-51a0-4928-aedc-0fcaead2b307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608837409 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1608837409
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2931014101
Short name T428
Test name
Test status
Simulation time 316636425 ps
CPU time 0.97 seconds
Started Aug 16 05:13:28 PM PDT 24
Finished Aug 16 05:13:29 PM PDT 24
Peak memory 201904 kb
Host smart-34a356f8-8b83-4d32-9f7c-1f8f313400c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931014101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2931014101
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.685035913
Short name T89
Test name
Test status
Simulation time 535687101085 ps
CPU time 413.08 seconds
Started Aug 16 05:13:29 PM PDT 24
Finished Aug 16 05:20:23 PM PDT 24
Peak memory 202076 kb
Host smart-bde60d3d-1f9b-4477-a390-4140b1b22042
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685035913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.685035913
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3942733116
Short name T622
Test name
Test status
Simulation time 169448527928 ps
CPU time 80.08 seconds
Started Aug 16 05:13:38 PM PDT 24
Finished Aug 16 05:14:58 PM PDT 24
Peak memory 202120 kb
Host smart-28b62148-7589-42d3-8572-7a8d922d59e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942733116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3942733116
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2605805240
Short name T481
Test name
Test status
Simulation time 162160777478 ps
CPU time 95.5 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:15:15 PM PDT 24
Peak memory 202164 kb
Host smart-f8301e80-01f5-4966-ad0b-816635e928da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605805240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2605805240
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1825141458
Short name T675
Test name
Test status
Simulation time 170802138302 ps
CPU time 376.53 seconds
Started Aug 16 05:13:35 PM PDT 24
Finished Aug 16 05:19:52 PM PDT 24
Peak memory 200548 kb
Host smart-44c2d37b-f932-4ca2-b0c1-7baa932376fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825141458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1825141458
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1431007133
Short name T580
Test name
Test status
Simulation time 326872134419 ps
CPU time 176.22 seconds
Started Aug 16 05:13:35 PM PDT 24
Finished Aug 16 05:16:31 PM PDT 24
Peak memory 202048 kb
Host smart-8337f5fb-9bac-4e0d-be76-08a0e380f610
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431007133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1431007133
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3992756930
Short name T658
Test name
Test status
Simulation time 368940549771 ps
CPU time 434.53 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:21:01 PM PDT 24
Peak memory 202116 kb
Host smart-53d348b7-f99b-47ba-afd1-b46a6e8d5370
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992756930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3992756930
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3098570738
Short name T528
Test name
Test status
Simulation time 600819305404 ps
CPU time 1341.87 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:36:02 PM PDT 24
Peak memory 202052 kb
Host smart-90d21986-ecfe-4bd4-8c50-a798574daf0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098570738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3098570738
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.512300430
Short name T557
Test name
Test status
Simulation time 111688164310 ps
CPU time 632.04 seconds
Started Aug 16 05:13:45 PM PDT 24
Finished Aug 16 05:24:18 PM PDT 24
Peak memory 202324 kb
Host smart-cb111b6a-9ca6-424c-9d8c-67da50c37aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512300430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.512300430
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.228971586
Short name T593
Test name
Test status
Simulation time 23813517079 ps
CPU time 53.14 seconds
Started Aug 16 05:13:39 PM PDT 24
Finished Aug 16 05:14:32 PM PDT 24
Peak memory 201900 kb
Host smart-2085bcf8-aabd-4c16-94b4-e96d54664013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228971586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.228971586
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1395179216
Short name T466
Test name
Test status
Simulation time 5578478762 ps
CPU time 4.11 seconds
Started Aug 16 05:13:30 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 201932 kb
Host smart-0dd3d561-6333-425a-879a-1207e6c09d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395179216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1395179216
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.392862335
Short name T588
Test name
Test status
Simulation time 5832531959 ps
CPU time 4.23 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:13:50 PM PDT 24
Peak memory 201912 kb
Host smart-d982c12d-1ae6-49fc-97ba-e6f830d814e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392862335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.392862335
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3939975107
Short name T227
Test name
Test status
Simulation time 205324158724 ps
CPU time 453.25 seconds
Started Aug 16 05:13:35 PM PDT 24
Finished Aug 16 05:21:09 PM PDT 24
Peak memory 202092 kb
Host smart-6d2a71ef-6a83-4235-898f-98a2b7d859b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939975107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3939975107
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2440954451
Short name T315
Test name
Test status
Simulation time 6942829214 ps
CPU time 5.65 seconds
Started Aug 16 05:13:42 PM PDT 24
Finished Aug 16 05:13:47 PM PDT 24
Peak memory 210556 kb
Host smart-61aad9b9-8634-4da6-9f98-19c0dd862a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440954451 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2440954451
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3275438786
Short name T383
Test name
Test status
Simulation time 464180854 ps
CPU time 1.11 seconds
Started Aug 16 05:13:49 PM PDT 24
Finished Aug 16 05:13:50 PM PDT 24
Peak memory 201900 kb
Host smart-48936fa7-52e4-4239-ac57-9fb1d892a710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275438786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3275438786
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1833592454
Short name T225
Test name
Test status
Simulation time 655771941071 ps
CPU time 1317.19 seconds
Started Aug 16 05:13:39 PM PDT 24
Finished Aug 16 05:35:36 PM PDT 24
Peak memory 202072 kb
Host smart-0b73cf8f-5958-4e9a-81b1-17b576542b16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833592454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1833592454
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1122141541
Short name T303
Test name
Test status
Simulation time 496145304836 ps
CPU time 1146.61 seconds
Started Aug 16 05:13:43 PM PDT 24
Finished Aug 16 05:32:50 PM PDT 24
Peak memory 202124 kb
Host smart-34eb2ba5-a4ec-434c-b8c3-f18a7f420197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122141541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1122141541
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4021461277
Short name T92
Test name
Test status
Simulation time 166715072522 ps
CPU time 412.5 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:20:33 PM PDT 24
Peak memory 202044 kb
Host smart-8298d93a-b655-4854-8986-90732c7525b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021461277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4021461277
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2385836311
Short name T260
Test name
Test status
Simulation time 490756321758 ps
CPU time 260.2 seconds
Started Aug 16 05:13:32 PM PDT 24
Finished Aug 16 05:17:52 PM PDT 24
Peak memory 202084 kb
Host smart-ff2df4e5-baf1-40ea-93fd-f0aee05c460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385836311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2385836311
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2377804442
Short name T601
Test name
Test status
Simulation time 491394008953 ps
CPU time 926.22 seconds
Started Aug 16 05:13:31 PM PDT 24
Finished Aug 16 05:28:58 PM PDT 24
Peak memory 202056 kb
Host smart-07f2d35e-b6e9-4800-9de3-e9a14b66a702
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377804442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2377804442
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3938581242
Short name T620
Test name
Test status
Simulation time 554083197344 ps
CPU time 1256.65 seconds
Started Aug 16 05:13:39 PM PDT 24
Finished Aug 16 05:34:36 PM PDT 24
Peak memory 202088 kb
Host smart-1db03fc0-3d11-4123-8f98-46acdfd45475
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938581242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3938581242
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.459909702
Short name T46
Test name
Test status
Simulation time 194059854237 ps
CPU time 449.63 seconds
Started Aug 16 05:13:31 PM PDT 24
Finished Aug 16 05:21:01 PM PDT 24
Peak memory 202024 kb
Host smart-23f24b4c-8748-4101-bfd4-3026280d7965
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459909702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.459909702
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4083764533
Short name T186
Test name
Test status
Simulation time 84884519521 ps
CPU time 365.46 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:19:52 PM PDT 24
Peak memory 202316 kb
Host smart-4a1a363d-f051-4048-ad97-35423fe8fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083764533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4083764533
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2672532929
Short name T395
Test name
Test status
Simulation time 26803992939 ps
CPU time 16.04 seconds
Started Aug 16 05:13:40 PM PDT 24
Finished Aug 16 05:13:56 PM PDT 24
Peak memory 201880 kb
Host smart-5dc7828f-7a15-4791-977e-439304634a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672532929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2672532929
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3742847323
Short name T755
Test name
Test status
Simulation time 3363877277 ps
CPU time 8.57 seconds
Started Aug 16 05:13:39 PM PDT 24
Finished Aug 16 05:13:48 PM PDT 24
Peak memory 201904 kb
Host smart-c6f1d20c-2791-4ced-a85f-ef6056b68221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742847323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3742847323
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3185599912
Short name T378
Test name
Test status
Simulation time 5814019085 ps
CPU time 5.5 seconds
Started Aug 16 05:13:35 PM PDT 24
Finished Aug 16 05:13:41 PM PDT 24
Peak memory 200316 kb
Host smart-b4d79a54-7e1c-45c9-ac48-0c907ef77422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185599912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3185599912
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1565099127
Short name T149
Test name
Test status
Simulation time 364920195488 ps
CPU time 245.98 seconds
Started Aug 16 05:13:48 PM PDT 24
Finished Aug 16 05:17:54 PM PDT 24
Peak memory 202072 kb
Host smart-e8fb7376-109e-4b01-9c60-a7997fb6efb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565099127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1565099127
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2299618192
Short name T577
Test name
Test status
Simulation time 2664029797 ps
CPU time 7.5 seconds
Started Aug 16 05:13:49 PM PDT 24
Finished Aug 16 05:13:56 PM PDT 24
Peak memory 210440 kb
Host smart-4d8c8981-cbd4-4a7e-81fa-d0dc41c05fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299618192 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2299618192
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.15755930
Short name T592
Test name
Test status
Simulation time 317482927 ps
CPU time 1.26 seconds
Started Aug 16 05:13:50 PM PDT 24
Finished Aug 16 05:13:52 PM PDT 24
Peak memory 201972 kb
Host smart-56ebed60-0e96-4f02-b0ac-94b3e02df48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.15755930
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3830504695
Short name T154
Test name
Test status
Simulation time 338725789007 ps
CPU time 178.09 seconds
Started Aug 16 05:13:37 PM PDT 24
Finished Aug 16 05:16:35 PM PDT 24
Peak memory 202080 kb
Host smart-1ef2aafb-b5d1-4423-9388-31914bed850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830504695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3830504695
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3656711816
Short name T90
Test name
Test status
Simulation time 330222398991 ps
CPU time 118.52 seconds
Started Aug 16 05:13:41 PM PDT 24
Finished Aug 16 05:15:40 PM PDT 24
Peak memory 202068 kb
Host smart-ca6ae313-cb05-4d3d-8bca-4091ca1e17e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656711816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3656711816
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.432344403
Short name T751
Test name
Test status
Simulation time 494879166691 ps
CPU time 600.58 seconds
Started Aug 16 05:13:50 PM PDT 24
Finished Aug 16 05:23:51 PM PDT 24
Peak memory 202068 kb
Host smart-72933826-2bf7-4768-8eee-50cbbe9662bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432344403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.432344403
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1168135704
Short name T166
Test name
Test status
Simulation time 183346713615 ps
CPU time 103.55 seconds
Started Aug 16 05:13:56 PM PDT 24
Finished Aug 16 05:15:40 PM PDT 24
Peak memory 202116 kb
Host smart-f014353d-5af5-4806-b830-e93fe84640a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168135704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1168135704
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.311800339
Short name T584
Test name
Test status
Simulation time 197782795783 ps
CPU time 414.66 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:20:41 PM PDT 24
Peak memory 202092 kb
Host smart-e946cc71-c94f-4093-be21-d3f9448ac92c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311800339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.311800339
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2469995023
Short name T758
Test name
Test status
Simulation time 116139082028 ps
CPU time 410.62 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:20:38 PM PDT 24
Peak memory 202368 kb
Host smart-ad69908e-a657-419f-a58b-38a66dd31cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469995023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2469995023
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.164118179
Short name T583
Test name
Test status
Simulation time 35475352662 ps
CPU time 20.1 seconds
Started Aug 16 05:13:48 PM PDT 24
Finished Aug 16 05:14:08 PM PDT 24
Peak memory 201896 kb
Host smart-080deee6-b9ff-49f1-ba9a-fe1d4c6d7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164118179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.164118179
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1514839298
Short name T764
Test name
Test status
Simulation time 5200765212 ps
CPU time 2.02 seconds
Started Aug 16 05:13:41 PM PDT 24
Finished Aug 16 05:13:43 PM PDT 24
Peak memory 201892 kb
Host smart-3de94198-423e-4a41-a9cb-86ebf52ae320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514839298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1514839298
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2138722930
Short name T692
Test name
Test status
Simulation time 5784837781 ps
CPU time 4.21 seconds
Started Aug 16 05:13:41 PM PDT 24
Finished Aug 16 05:13:46 PM PDT 24
Peak memory 201888 kb
Host smart-899d9b64-a720-4392-9d9f-e0fb19a810b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138722930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2138722930
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1098124303
Short name T147
Test name
Test status
Simulation time 2987977139 ps
CPU time 14.18 seconds
Started Aug 16 05:13:37 PM PDT 24
Finished Aug 16 05:13:51 PM PDT 24
Peak memory 210484 kb
Host smart-2f37a055-89a8-4dc3-a5c4-1c09832e32d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098124303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1098124303
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3734870599
Short name T379
Test name
Test status
Simulation time 498347424 ps
CPU time 0.86 seconds
Started Aug 16 05:13:55 PM PDT 24
Finished Aug 16 05:13:56 PM PDT 24
Peak memory 201948 kb
Host smart-b78b84df-4c62-4b6b-88d9-0fd2bd1d1745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734870599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3734870599
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1198947808
Short name T777
Test name
Test status
Simulation time 512091735678 ps
CPU time 1243.44 seconds
Started Aug 16 05:13:59 PM PDT 24
Finished Aug 16 05:34:43 PM PDT 24
Peak memory 202104 kb
Host smart-033a0e82-81b8-49e7-b493-c89a220f1af3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198947808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1198947808
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.951589749
Short name T783
Test name
Test status
Simulation time 362078222469 ps
CPU time 208.03 seconds
Started Aug 16 05:13:58 PM PDT 24
Finished Aug 16 05:17:26 PM PDT 24
Peak memory 202152 kb
Host smart-c7bc6246-4489-4584-8ff4-9ec045d64dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951589749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.951589749
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1756029491
Short name T669
Test name
Test status
Simulation time 323425151412 ps
CPU time 788.03 seconds
Started Aug 16 05:13:45 PM PDT 24
Finished Aug 16 05:26:53 PM PDT 24
Peak memory 202072 kb
Host smart-d428fd48-ae24-4ae6-98ef-1c986bd7ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756029491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1756029491
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.4006096241
Short name T572
Test name
Test status
Simulation time 326754738698 ps
CPU time 183.42 seconds
Started Aug 16 05:13:58 PM PDT 24
Finished Aug 16 05:17:02 PM PDT 24
Peak memory 202120 kb
Host smart-59eccde8-90fe-4b9f-a805-c2c1d3158bc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006096241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.4006096241
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1922174448
Short name T113
Test name
Test status
Simulation time 169275997478 ps
CPU time 381.45 seconds
Started Aug 16 05:13:47 PM PDT 24
Finished Aug 16 05:20:09 PM PDT 24
Peak memory 202068 kb
Host smart-da24abc3-10b8-43e1-bc54-afe1c51963fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922174448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1922174448
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2175034050
Short name T454
Test name
Test status
Simulation time 498714420339 ps
CPU time 1153.3 seconds
Started Aug 16 05:13:45 PM PDT 24
Finished Aug 16 05:32:59 PM PDT 24
Peak memory 202072 kb
Host smart-cd88c832-851d-42ed-924f-90593e38336a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175034050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2175034050
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1544176290
Short name T268
Test name
Test status
Simulation time 521601557022 ps
CPU time 1182.63 seconds
Started Aug 16 05:13:49 PM PDT 24
Finished Aug 16 05:33:32 PM PDT 24
Peak memory 202112 kb
Host smart-7d4b7469-f1ba-421f-8538-60893b377e40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544176290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1544176290
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.788907267
Short name T373
Test name
Test status
Simulation time 594843919587 ps
CPU time 1311.15 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:35:38 PM PDT 24
Peak memory 202044 kb
Host smart-b63b451b-40d3-4f88-a6e1-eb0966b0868d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788907267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.788907267
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3521480406
Short name T50
Test name
Test status
Simulation time 127839115068 ps
CPU time 437.77 seconds
Started Aug 16 05:13:51 PM PDT 24
Finished Aug 16 05:21:09 PM PDT 24
Peak memory 202328 kb
Host smart-d0755b55-16f6-4d23-85c1-9247d70b5fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521480406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3521480406
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2040194540
Short name T695
Test name
Test status
Simulation time 34366022156 ps
CPU time 75.62 seconds
Started Aug 16 05:13:55 PM PDT 24
Finished Aug 16 05:15:11 PM PDT 24
Peak memory 201912 kb
Host smart-327e74c0-865b-4443-8301-79851fe490ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040194540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2040194540
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2562340522
Short name T576
Test name
Test status
Simulation time 4128638240 ps
CPU time 11.02 seconds
Started Aug 16 05:13:46 PM PDT 24
Finished Aug 16 05:13:57 PM PDT 24
Peak memory 201880 kb
Host smart-2c1c9844-1a91-4269-94bc-12d34668b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562340522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2562340522
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.155823604
Short name T547
Test name
Test status
Simulation time 5689872565 ps
CPU time 3.82 seconds
Started Aug 16 05:13:50 PM PDT 24
Finished Aug 16 05:13:54 PM PDT 24
Peak memory 201896 kb
Host smart-d60afea4-2c69-434f-8dfa-87da1efc7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155823604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.155823604
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4054667237
Short name T156
Test name
Test status
Simulation time 193459857449 ps
CPU time 231.76 seconds
Started Aug 16 05:13:51 PM PDT 24
Finished Aug 16 05:17:43 PM PDT 24
Peak memory 202136 kb
Host smart-781e32f8-dfd0-459d-abde-a793ffa4958e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054667237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4054667237
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3448478728
Short name T512
Test name
Test status
Simulation time 2369392206 ps
CPU time 6.6 seconds
Started Aug 16 05:13:51 PM PDT 24
Finished Aug 16 05:13:58 PM PDT 24
Peak memory 202056 kb
Host smart-bad97c74-e4b0-40a7-8fec-ce6c7ea1b45c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448478728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3448478728
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3873172479
Short name T559
Test name
Test status
Simulation time 552757783 ps
CPU time 0.94 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:12:58 PM PDT 24
Peak memory 201904 kb
Host smart-45ff7b91-b995-4b2e-8ecb-5a8f9b298e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873172479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3873172479
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.511543218
Short name T744
Test name
Test status
Simulation time 335664601594 ps
CPU time 746.96 seconds
Started Aug 16 05:13:08 PM PDT 24
Finished Aug 16 05:25:35 PM PDT 24
Peak memory 202064 kb
Host smart-806fe8eb-eafc-4787-9aef-08f448f9650b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511543218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.511543218
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1634688146
Short name T339
Test name
Test status
Simulation time 168248703507 ps
CPU time 367.62 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:19:03 PM PDT 24
Peak memory 202064 kb
Host smart-97d31af3-6c03-4e73-8caf-f75505273731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634688146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1634688146
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.508598888
Short name T337
Test name
Test status
Simulation time 509586046017 ps
CPU time 1123.27 seconds
Started Aug 16 05:12:44 PM PDT 24
Finished Aug 16 05:31:27 PM PDT 24
Peak memory 202088 kb
Host smart-2138146a-4d17-435b-b957-908a8c3b9262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508598888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.508598888
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4242497848
Short name T446
Test name
Test status
Simulation time 164491001957 ps
CPU time 363.87 seconds
Started Aug 16 05:12:44 PM PDT 24
Finished Aug 16 05:18:48 PM PDT 24
Peak memory 202180 kb
Host smart-2b2e5479-b533-4fd2-9b6c-c06979f54f5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242497848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4242497848
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.344970413
Short name T498
Test name
Test status
Simulation time 329607040569 ps
CPU time 399.68 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:19:46 PM PDT 24
Peak memory 202040 kb
Host smart-80c2d483-3511-408f-9a22-19aa5f01885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344970413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.344970413
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3985477036
Short name T435
Test name
Test status
Simulation time 487715434432 ps
CPU time 296.55 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:18:10 PM PDT 24
Peak memory 202048 kb
Host smart-a4e2f67c-d141-4518-a316-4c1814caa994
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985477036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3985477036
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2504406020
Short name T346
Test name
Test status
Simulation time 364291603622 ps
CPU time 231.31 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:16:48 PM PDT 24
Peak memory 202080 kb
Host smart-732d06bd-2166-485c-a6c2-9f060cbf93f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504406020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2504406020
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2900206301
Short name T520
Test name
Test status
Simulation time 402351411976 ps
CPU time 874.82 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:27:32 PM PDT 24
Peak memory 202076 kb
Host smart-7ac7fb4a-3832-4677-b87a-deb3c39fb96d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900206301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2900206301
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4085981140
Short name T199
Test name
Test status
Simulation time 84543146726 ps
CPU time 309.24 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:18:05 PM PDT 24
Peak memory 202332 kb
Host smart-15436ae8-e427-4cfd-8557-40adb64ae18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085981140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4085981140
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1616304346
Short name T389
Test name
Test status
Simulation time 41580066050 ps
CPU time 24.9 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:13:20 PM PDT 24
Peak memory 201904 kb
Host smart-7e7177b6-e923-439f-9b6c-116dfe73a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616304346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1616304346
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3730704583
Short name T534
Test name
Test status
Simulation time 4209568501 ps
CPU time 3.47 seconds
Started Aug 16 05:12:53 PM PDT 24
Finished Aug 16 05:12:57 PM PDT 24
Peak memory 201900 kb
Host smart-4e4d4f22-ddf6-4c28-a0ba-c5d21b713378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730704583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3730704583
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1956631222
Short name T65
Test name
Test status
Simulation time 4064864821 ps
CPU time 10.4 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 217384 kb
Host smart-39be8cd7-333e-4ea8-a6ff-414129023140
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956631222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1956631222
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4009496935
Short name T568
Test name
Test status
Simulation time 6143473530 ps
CPU time 14.93 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:13:20 PM PDT 24
Peak memory 201912 kb
Host smart-78be829d-2349-4c9f-8d0f-d1aff0d745ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009496935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4009496935
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1851009647
Short name T36
Test name
Test status
Simulation time 92104257774 ps
CPU time 250.53 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:17:09 PM PDT 24
Peak memory 210504 kb
Host smart-d541a7f1-c4fa-43a1-a24e-e4f6da5d2704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851009647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1851009647
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2759938422
Short name T288
Test name
Test status
Simulation time 98011745803 ps
CPU time 12.3 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:13:09 PM PDT 24
Peak memory 210428 kb
Host smart-d18598fe-7a5c-40ed-bbed-e3a3d1a85fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759938422 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2759938422
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1531867757
Short name T581
Test name
Test status
Simulation time 283009821 ps
CPU time 1.23 seconds
Started Aug 16 05:13:53 PM PDT 24
Finished Aug 16 05:13:55 PM PDT 24
Peak memory 201928 kb
Host smart-50eb3bb3-5340-44ed-8faf-4cda4ee6ef05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531867757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1531867757
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3257526444
Short name T170
Test name
Test status
Simulation time 341685540803 ps
CPU time 179.13 seconds
Started Aug 16 05:13:53 PM PDT 24
Finished Aug 16 05:16:53 PM PDT 24
Peak memory 202072 kb
Host smart-a46650a4-6b7e-4fbc-84e2-ad26e2ebcf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257526444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3257526444
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.219304917
Short name T244
Test name
Test status
Simulation time 163741414040 ps
CPU time 284.24 seconds
Started Aug 16 05:13:54 PM PDT 24
Finished Aug 16 05:18:38 PM PDT 24
Peak memory 202120 kb
Host smart-fb825f30-54d6-477a-ba05-60a320bafd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219304917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.219304917
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1025912388
Short name T644
Test name
Test status
Simulation time 161043665568 ps
CPU time 385.02 seconds
Started Aug 16 05:13:53 PM PDT 24
Finished Aug 16 05:20:18 PM PDT 24
Peak memory 202088 kb
Host smart-5320fccb-4e99-409b-b9d0-042a8c917bcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025912388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1025912388
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3677779932
Short name T104
Test name
Test status
Simulation time 167791522156 ps
CPU time 95.93 seconds
Started Aug 16 05:13:59 PM PDT 24
Finished Aug 16 05:15:35 PM PDT 24
Peak memory 202056 kb
Host smart-38da8666-42be-4223-8fe3-c4391a1578a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677779932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3677779932
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3737994660
Short name T159
Test name
Test status
Simulation time 496121815602 ps
CPU time 219.56 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:17:44 PM PDT 24
Peak memory 202084 kb
Host smart-810794a2-8805-4844-b057-0faf0b1cfa35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737994660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3737994660
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2514626440
Short name T333
Test name
Test status
Simulation time 345538965234 ps
CPU time 830.27 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:27:55 PM PDT 24
Peak memory 202060 kb
Host smart-032f865c-5301-4430-8507-25721104e452
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514626440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2514626440
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1403554879
Short name T414
Test name
Test status
Simulation time 400258393017 ps
CPU time 842.15 seconds
Started Aug 16 05:13:53 PM PDT 24
Finished Aug 16 05:27:55 PM PDT 24
Peak memory 202048 kb
Host smart-d6508f62-4058-4853-8130-2b162a37ad77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403554879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1403554879
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2694937615
Short name T479
Test name
Test status
Simulation time 33520354736 ps
CPU time 77.31 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:15:21 PM PDT 24
Peak memory 201912 kb
Host smart-2ef5cff6-e85f-4a18-9f41-8d2e223a27bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694937615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2694937615
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2405634085
Short name T693
Test name
Test status
Simulation time 5302943822 ps
CPU time 3.76 seconds
Started Aug 16 05:13:56 PM PDT 24
Finished Aug 16 05:14:00 PM PDT 24
Peak memory 201956 kb
Host smart-6ce0af31-bfec-4bc5-b400-61be5ec0dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405634085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2405634085
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.180040758
Short name T33
Test name
Test status
Simulation time 5680834633 ps
CPU time 7.44 seconds
Started Aug 16 05:13:57 PM PDT 24
Finished Aug 16 05:14:05 PM PDT 24
Peak memory 201872 kb
Host smart-e76557b4-204e-4f37-833b-a9ffb855f866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180040758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.180040758
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3531435601
Short name T146
Test name
Test status
Simulation time 613185372771 ps
CPU time 1027.15 seconds
Started Aug 16 05:13:52 PM PDT 24
Finished Aug 16 05:30:59 PM PDT 24
Peak memory 210504 kb
Host smart-d9876a70-b512-4f99-af49-43e7d89d8276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531435601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3531435601
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.555670461
Short name T660
Test name
Test status
Simulation time 33509420909 ps
CPU time 47.42 seconds
Started Aug 16 05:13:57 PM PDT 24
Finished Aug 16 05:14:44 PM PDT 24
Peak memory 210712 kb
Host smart-6dadb12d-d470-42de-9b2c-7e6487359a0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555670461 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.555670461
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1181003662
Short name T490
Test name
Test status
Simulation time 314715282 ps
CPU time 0.93 seconds
Started Aug 16 05:13:59 PM PDT 24
Finished Aug 16 05:14:00 PM PDT 24
Peak memory 201928 kb
Host smart-2c67ec9c-4d81-4a70-afdf-2d73f2391294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181003662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1181003662
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1856224018
Short name T571
Test name
Test status
Simulation time 164673881121 ps
CPU time 358.48 seconds
Started Aug 16 05:13:52 PM PDT 24
Finished Aug 16 05:19:51 PM PDT 24
Peak memory 202060 kb
Host smart-0d11af42-8cbd-4f89-93c1-bf7a00a82c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856224018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1856224018
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1369417349
Short name T443
Test name
Test status
Simulation time 330167249109 ps
CPU time 216.67 seconds
Started Aug 16 05:13:53 PM PDT 24
Finished Aug 16 05:17:30 PM PDT 24
Peak memory 202144 kb
Host smart-4d01ea9d-2132-4929-807b-29e88cc0b234
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369417349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1369417349
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4280098339
Short name T326
Test name
Test status
Simulation time 500540987901 ps
CPU time 1064.16 seconds
Started Aug 16 05:13:54 PM PDT 24
Finished Aug 16 05:31:38 PM PDT 24
Peak memory 202080 kb
Host smart-712ab276-6669-4625-8c4a-129fd1bc04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280098339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4280098339
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.396738662
Short name T514
Test name
Test status
Simulation time 321604802200 ps
CPU time 693.49 seconds
Started Aug 16 05:13:55 PM PDT 24
Finished Aug 16 05:25:28 PM PDT 24
Peak memory 202080 kb
Host smart-33a93d1d-4f92-4e81-b413-5d6f7fc40087
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=396738662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.396738662
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3555316285
Short name T232
Test name
Test status
Simulation time 179406103117 ps
CPU time 420.9 seconds
Started Aug 16 05:13:56 PM PDT 24
Finished Aug 16 05:20:57 PM PDT 24
Peak memory 202204 kb
Host smart-48340eb9-494d-45ae-aac8-ca27fd5c38c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555316285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3555316285
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4022052629
Short name T564
Test name
Test status
Simulation time 396638552658 ps
CPU time 123.35 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:16:06 PM PDT 24
Peak memory 202080 kb
Host smart-e38ca8c2-15db-42e5-b98b-3d25d687f6cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022052629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4022052629
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1758016833
Short name T174
Test name
Test status
Simulation time 130561163362 ps
CPU time 688.79 seconds
Started Aug 16 05:14:00 PM PDT 24
Finished Aug 16 05:25:29 PM PDT 24
Peak memory 202368 kb
Host smart-d9898823-8a2d-497f-9fc2-bd0d055d3d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758016833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1758016833
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3254329875
Short name T650
Test name
Test status
Simulation time 44651970921 ps
CPU time 93.91 seconds
Started Aug 16 05:13:54 PM PDT 24
Finished Aug 16 05:15:28 PM PDT 24
Peak memory 201924 kb
Host smart-9f5335ec-13aa-492f-9c0a-da6c81a84ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254329875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3254329875
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4090095550
Short name T676
Test name
Test status
Simulation time 4070823766 ps
CPU time 10.06 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:14:13 PM PDT 24
Peak memory 201908 kb
Host smart-8b957cd3-bfb1-4b46-930b-6b286b0808ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090095550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4090095550
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2728832531
Short name T110
Test name
Test status
Simulation time 5851813626 ps
CPU time 3.97 seconds
Started Aug 16 05:13:55 PM PDT 24
Finished Aug 16 05:14:00 PM PDT 24
Peak memory 201896 kb
Host smart-a1ac6c30-0978-4b78-82b0-23eb2915fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728832531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2728832531
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4189722341
Short name T49
Test name
Test status
Simulation time 395471303152 ps
CPU time 547.97 seconds
Started Aug 16 05:13:57 PM PDT 24
Finished Aug 16 05:23:06 PM PDT 24
Peak memory 202360 kb
Host smart-c40444b0-52e6-46a0-bb61-54aa8591a197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189722341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4189722341
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3164173508
Short name T32
Test name
Test status
Simulation time 5167409342 ps
CPU time 15.51 seconds
Started Aug 16 05:13:54 PM PDT 24
Finished Aug 16 05:14:09 PM PDT 24
Peak memory 210644 kb
Host smart-0ebb7214-095d-48d4-9bb3-3cfc63732804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164173508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3164173508
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2988435573
Short name T621
Test name
Test status
Simulation time 411659055 ps
CPU time 1.14 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:14:05 PM PDT 24
Peak memory 201924 kb
Host smart-b8346d22-80a2-414d-858b-e4bc8988d1ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988435573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2988435573
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.193857289
Short name T323
Test name
Test status
Simulation time 532197141589 ps
CPU time 656.53 seconds
Started Aug 16 05:14:05 PM PDT 24
Finished Aug 16 05:25:02 PM PDT 24
Peak memory 202060 kb
Host smart-505bcc69-7743-4895-9ab3-e67a939d3d4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193857289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.193857289
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1235636328
Short name T292
Test name
Test status
Simulation time 532691496916 ps
CPU time 670.28 seconds
Started Aug 16 05:14:01 PM PDT 24
Finished Aug 16 05:25:12 PM PDT 24
Peak memory 202192 kb
Host smart-1010f58c-e657-42bf-a199-8181e0fa1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235636328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1235636328
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.965956714
Short name T754
Test name
Test status
Simulation time 164111804530 ps
CPU time 107.54 seconds
Started Aug 16 05:14:01 PM PDT 24
Finished Aug 16 05:15:49 PM PDT 24
Peak memory 202132 kb
Host smart-450f11b0-62e0-4e96-83ba-d9391fef11fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965956714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.965956714
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1331406540
Short name T14
Test name
Test status
Simulation time 485309562642 ps
CPU time 1049.52 seconds
Started Aug 16 05:14:01 PM PDT 24
Finished Aug 16 05:31:30 PM PDT 24
Peak memory 202128 kb
Host smart-8927078a-2c93-4c2f-9fbc-87e895d1059f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331406540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1331406540
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4116015067
Short name T178
Test name
Test status
Simulation time 161331512451 ps
CPU time 37.75 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:14:40 PM PDT 24
Peak memory 201996 kb
Host smart-680420f5-58aa-408c-afba-72ed8459aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116015067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4116015067
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.628072803
Short name T404
Test name
Test status
Simulation time 492087212828 ps
CPU time 542.97 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:23:05 PM PDT 24
Peak memory 202052 kb
Host smart-46b1b030-5f79-40e4-b690-ca323e908781
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=628072803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.628072803
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.57224291
Short name T239
Test name
Test status
Simulation time 559045277685 ps
CPU time 352.02 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:19:56 PM PDT 24
Peak memory 202080 kb
Host smart-b3c3a7f6-2f75-452f-bfa9-e9edf9850ea1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57224291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_w
akeup.57224291
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4262160505
Short name T662
Test name
Test status
Simulation time 601720616701 ps
CPU time 767.19 seconds
Started Aug 16 05:14:05 PM PDT 24
Finished Aug 16 05:26:53 PM PDT 24
Peak memory 202032 kb
Host smart-89824aa0-4b7c-452a-a90f-383d8728eedf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262160505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4262160505
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.903307389
Short name T494
Test name
Test status
Simulation time 80003693550 ps
CPU time 456.8 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:21:41 PM PDT 24
Peak memory 202324 kb
Host smart-e09edba5-a67a-43d5-bc34-2d4479333756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903307389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.903307389
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3829381580
Short name T96
Test name
Test status
Simulation time 46745545256 ps
CPU time 21.51 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:14:24 PM PDT 24
Peak memory 201880 kb
Host smart-63f989e8-1ad0-49bb-806e-44ebe40b3fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829381580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3829381580
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2683643011
Short name T359
Test name
Test status
Simulation time 3329844387 ps
CPU time 2.1 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:14:05 PM PDT 24
Peak memory 201836 kb
Host smart-af93a6f0-c82c-4557-9640-49822010db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683643011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2683643011
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3188561349
Short name T425
Test name
Test status
Simulation time 5672412763 ps
CPU time 12.26 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:14:15 PM PDT 24
Peak memory 201964 kb
Host smart-5fe320a9-f68c-4d0d-9318-ae3cb5baebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188561349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3188561349
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3272264370
Short name T596
Test name
Test status
Simulation time 404257680053 ps
CPU time 236.62 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:18:01 PM PDT 24
Peak memory 202100 kb
Host smart-21a51379-44df-4e51-bc4e-eef0c51f5183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272264370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3272264370
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3515843695
Short name T728
Test name
Test status
Simulation time 3497860838 ps
CPU time 8.93 seconds
Started Aug 16 05:14:05 PM PDT 24
Finished Aug 16 05:14:14 PM PDT 24
Peak memory 210388 kb
Host smart-b2b4e3c4-a7c0-4fbb-8f92-3e098ef96f84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515843695 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3515843695
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4193847449
Short name T87
Test name
Test status
Simulation time 365220658 ps
CPU time 0.67 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:14:04 PM PDT 24
Peak memory 201920 kb
Host smart-8fcb5abd-dacf-4f81-a531-68c487e9e7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193847449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4193847449
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1624913892
Short name T297
Test name
Test status
Simulation time 166636520565 ps
CPU time 105.29 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:15:48 PM PDT 24
Peak memory 202072 kb
Host smart-b56e8a6e-4930-46f6-8fa1-e5cb2a0a1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624913892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1624913892
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2248284210
Short name T792
Test name
Test status
Simulation time 162667540591 ps
CPU time 105.96 seconds
Started Aug 16 05:14:07 PM PDT 24
Finished Aug 16 05:15:53 PM PDT 24
Peak memory 202052 kb
Host smart-0f4e1fcf-1687-413c-80fe-bae79d548cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248284210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2248284210
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1111639405
Short name T530
Test name
Test status
Simulation time 168277215782 ps
CPU time 98.86 seconds
Started Aug 16 05:14:05 PM PDT 24
Finished Aug 16 05:15:44 PM PDT 24
Peak memory 202072 kb
Host smart-f9ddd072-dfa5-47de-bee8-1b566f43388b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111639405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1111639405
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1418436773
Short name T165
Test name
Test status
Simulation time 512922990387 ps
CPU time 299.58 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:19:03 PM PDT 24
Peak memory 202096 kb
Host smart-8d0c7335-5df4-42e7-8563-34dd255ec197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418436773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1418436773
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2500700716
Short name T467
Test name
Test status
Simulation time 159508654761 ps
CPU time 335.79 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:19:38 PM PDT 24
Peak memory 202024 kb
Host smart-85e25db6-895b-41f0-b1d6-a314aec0c2ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500700716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2500700716
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1840474795
Short name T594
Test name
Test status
Simulation time 397365027664 ps
CPU time 212.9 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:17:35 PM PDT 24
Peak memory 202116 kb
Host smart-e824d91c-a828-4b74-adcc-fb47dff93f43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840474795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1840474795
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1202049044
Short name T51
Test name
Test status
Simulation time 128003412890 ps
CPU time 451.74 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:21:35 PM PDT 24
Peak memory 202404 kb
Host smart-41b83830-7022-4c8f-a344-d586d7fd4779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202049044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1202049044
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.544709334
Short name T600
Test name
Test status
Simulation time 38979777987 ps
CPU time 21.97 seconds
Started Aug 16 05:14:00 PM PDT 24
Finished Aug 16 05:14:22 PM PDT 24
Peak memory 201880 kb
Host smart-55cf0695-9b9d-4313-9858-6e6d9e2e0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544709334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.544709334
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1368119684
Short name T654
Test name
Test status
Simulation time 4839128747 ps
CPU time 3.37 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:14:07 PM PDT 24
Peak memory 201904 kb
Host smart-1519ad65-64cf-4412-8333-c0b100531c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368119684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1368119684
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.907334156
Short name T461
Test name
Test status
Simulation time 5790439310 ps
CPU time 13.01 seconds
Started Aug 16 05:14:04 PM PDT 24
Finished Aug 16 05:14:18 PM PDT 24
Peak memory 201904 kb
Host smart-78957d08-17a7-4917-9388-9dbdf342150e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907334156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.907334156
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.856014807
Short name T221
Test name
Test status
Simulation time 532019789923 ps
CPU time 1157.71 seconds
Started Aug 16 05:14:03 PM PDT 24
Finished Aug 16 05:33:21 PM PDT 24
Peak memory 202124 kb
Host smart-156ae293-a2e2-4a07-9ea0-2da36de91785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856014807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
856014807
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.630299707
Short name T62
Test name
Test status
Simulation time 1120323696288 ps
CPU time 108.83 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:15:50 PM PDT 24
Peak memory 210424 kb
Host smart-5b3503a1-9022-413e-8d74-01f5fb97e37c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630299707 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.630299707
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2870121113
Short name T458
Test name
Test status
Simulation time 330764399 ps
CPU time 1.01 seconds
Started Aug 16 05:14:13 PM PDT 24
Finished Aug 16 05:14:14 PM PDT 24
Peak memory 201944 kb
Host smart-6f06ffa0-7054-4f22-ada2-9d896821bb8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870121113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2870121113
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.812064884
Short name T524
Test name
Test status
Simulation time 178668603898 ps
CPU time 103.95 seconds
Started Aug 16 05:14:11 PM PDT 24
Finished Aug 16 05:15:55 PM PDT 24
Peak memory 202068 kb
Host smart-8e8450d6-e5a0-4164-9693-88ededecc1c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812064884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.812064884
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3073483262
Short name T651
Test name
Test status
Simulation time 530002706267 ps
CPU time 214.35 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:17:44 PM PDT 24
Peak memory 202136 kb
Host smart-d0a58c0c-ecef-4c4b-b365-b5de5b03d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073483262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3073483262
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2565914416
Short name T772
Test name
Test status
Simulation time 334593749938 ps
CPU time 189.99 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:17:20 PM PDT 24
Peak memory 202076 kb
Host smart-7d5ca2ec-b87e-4335-b309-249646783151
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565914416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2565914416
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.402821810
Short name T709
Test name
Test status
Simulation time 330939774355 ps
CPU time 208.06 seconds
Started Aug 16 05:14:02 PM PDT 24
Finished Aug 16 05:17:30 PM PDT 24
Peak memory 202088 kb
Host smart-0880eebc-3b2d-4771-9477-9e0369e1257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402821810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.402821810
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4242161382
Short name T690
Test name
Test status
Simulation time 164968520754 ps
CPU time 264.07 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:18:34 PM PDT 24
Peak memory 202076 kb
Host smart-1e509ca8-974b-4780-865f-71e241eaddd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242161382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4242161382
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.4029580567
Short name T556
Test name
Test status
Simulation time 174557444134 ps
CPU time 36.44 seconds
Started Aug 16 05:14:09 PM PDT 24
Finished Aug 16 05:14:46 PM PDT 24
Peak memory 202080 kb
Host smart-c9d58294-63c5-40fe-8e9a-1f301f7de76c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029580567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.4029580567
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3523166499
Short name T386
Test name
Test status
Simulation time 407049562182 ps
CPU time 945.69 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:29:58 PM PDT 24
Peak memory 202100 kb
Host smart-1b480f10-a76f-4fa9-ae52-dd68ccec4253
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523166499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3523166499
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3913554679
Short name T632
Test name
Test status
Simulation time 122619194877 ps
CPU time 432.05 seconds
Started Aug 16 05:14:11 PM PDT 24
Finished Aug 16 05:21:23 PM PDT 24
Peak memory 202348 kb
Host smart-b89a4b55-66c4-463c-a9a5-e92db72a2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913554679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3913554679
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1248135912
Short name T605
Test name
Test status
Simulation time 46171913709 ps
CPU time 24.99 seconds
Started Aug 16 05:14:13 PM PDT 24
Finished Aug 16 05:14:38 PM PDT 24
Peak memory 201892 kb
Host smart-85f1a700-19ee-43d6-9261-34516aa01ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248135912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1248135912
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1293557076
Short name T488
Test name
Test status
Simulation time 4801601923 ps
CPU time 11.9 seconds
Started Aug 16 05:14:08 PM PDT 24
Finished Aug 16 05:14:20 PM PDT 24
Peak memory 201912 kb
Host smart-70756c0d-fb62-42c2-a001-c3989f9c7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293557076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1293557076
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3799095803
Short name T625
Test name
Test status
Simulation time 5887063063 ps
CPU time 4.33 seconds
Started Aug 16 05:14:07 PM PDT 24
Finished Aug 16 05:14:11 PM PDT 24
Peak memory 201908 kb
Host smart-a218117a-3910-4987-bffa-5479e9a30505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799095803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3799095803
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.342528522
Short name T224
Test name
Test status
Simulation time 337815070330 ps
CPU time 301.34 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:19:12 PM PDT 24
Peak memory 202088 kb
Host smart-caf82b86-cc6f-48cc-b211-b530410a27be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342528522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
342528522
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.749799796
Short name T687
Test name
Test status
Simulation time 190119714144 ps
CPU time 224.25 seconds
Started Aug 16 05:14:11 PM PDT 24
Finished Aug 16 05:17:55 PM PDT 24
Peak memory 202124 kb
Host smart-e7a3a026-44d4-4f5d-a76b-077e9d4051eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749799796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.749799796
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2615862820
Short name T318
Test name
Test status
Simulation time 328945467141 ps
CPU time 184.92 seconds
Started Aug 16 05:14:11 PM PDT 24
Finished Aug 16 05:17:16 PM PDT 24
Peak memory 202012 kb
Host smart-317573d9-f93f-43dc-b435-1cad8ad8e5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615862820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2615862820
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3581242155
Short name T640
Test name
Test status
Simulation time 330853685516 ps
CPU time 218.63 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:17:49 PM PDT 24
Peak memory 202080 kb
Host smart-c81e86e0-f1e2-47e1-ab95-45380a1ec5d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581242155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3581242155
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.633879841
Short name T312
Test name
Test status
Simulation time 495872572168 ps
CPU time 1189.79 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:34:00 PM PDT 24
Peak memory 202076 kb
Host smart-95035723-9c11-4999-862c-5f2099f65951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633879841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.633879841
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.686693690
Short name T630
Test name
Test status
Simulation time 160002159163 ps
CPU time 86.72 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:15:37 PM PDT 24
Peak memory 202008 kb
Host smart-e2ed47c5-0339-4b67-8e40-6ca9953f088b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=686693690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.686693690
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.536869515
Short name T590
Test name
Test status
Simulation time 611471526860 ps
CPU time 742.78 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:26:35 PM PDT 24
Peak memory 202100 kb
Host smart-d15f465b-6597-46d5-bcc4-7ec6ea9cbbd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536869515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.536869515
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2971566053
Short name T198
Test name
Test status
Simulation time 102703498151 ps
CPU time 434.58 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:21:27 PM PDT 24
Peak memory 202308 kb
Host smart-049d27b4-d5de-4f99-a306-0b0431e66632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971566053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2971566053
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3550990961
Short name T388
Test name
Test status
Simulation time 35889251933 ps
CPU time 78.43 seconds
Started Aug 16 05:14:09 PM PDT 24
Finished Aug 16 05:15:27 PM PDT 24
Peak memory 201876 kb
Host smart-5674fe9b-4e48-47de-b7ae-21ee55b61eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550990961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3550990961
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1503284873
Short name T700
Test name
Test status
Simulation time 3193158325 ps
CPU time 2.52 seconds
Started Aug 16 05:14:09 PM PDT 24
Finished Aug 16 05:14:12 PM PDT 24
Peak memory 201908 kb
Host smart-bc47d76a-083a-4462-8c08-014c1bca6229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503284873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1503284873
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2413869864
Short name T599
Test name
Test status
Simulation time 5827189975 ps
CPU time 3.99 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:14:16 PM PDT 24
Peak memory 201896 kb
Host smart-98b9b277-5203-4d1d-b1e6-4cc1d4452935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413869864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2413869864
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.785424894
Short name T745
Test name
Test status
Simulation time 173260384249 ps
CPU time 411.16 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:21:01 PM PDT 24
Peak memory 202108 kb
Host smart-eca15536-343a-4a2c-ad9a-b30b28961b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785424894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
785424894
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1890274298
Short name T21
Test name
Test status
Simulation time 166083250426 ps
CPU time 57.72 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:15:10 PM PDT 24
Peak memory 202220 kb
Host smart-2cd675b8-3926-4a93-9b04-4b47d460926b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890274298 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1890274298
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2142187674
Short name T776
Test name
Test status
Simulation time 344058105 ps
CPU time 1.41 seconds
Started Aug 16 05:14:19 PM PDT 24
Finished Aug 16 05:14:21 PM PDT 24
Peak memory 201796 kb
Host smart-dff5a554-a149-492b-af16-13e9f497aae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142187674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2142187674
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.551072566
Short name T270
Test name
Test status
Simulation time 488096221043 ps
CPU time 360.09 seconds
Started Aug 16 05:14:13 PM PDT 24
Finished Aug 16 05:20:13 PM PDT 24
Peak memory 202128 kb
Host smart-c237ce7e-9443-4293-b0f2-cb907567322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551072566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.551072566
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.522586162
Short name T725
Test name
Test status
Simulation time 329689885212 ps
CPU time 776.61 seconds
Started Aug 16 05:14:12 PM PDT 24
Finished Aug 16 05:27:09 PM PDT 24
Peak memory 202084 kb
Host smart-3e905c95-cf2a-4d8e-b9eb-ab4d3706574b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=522586162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.522586162
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3132321323
Short name T316
Test name
Test status
Simulation time 326228301678 ps
CPU time 80.9 seconds
Started Aug 16 05:14:15 PM PDT 24
Finished Aug 16 05:15:36 PM PDT 24
Peak memory 202128 kb
Host smart-0cf2cfbf-3625-482d-bec1-e05db58aadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132321323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3132321323
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.604273225
Short name T785
Test name
Test status
Simulation time 166357453440 ps
CPU time 100.78 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:15:51 PM PDT 24
Peak memory 202068 kb
Host smart-2a3a7c64-9c36-45dc-9b2c-b39e101c8448
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=604273225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.604273225
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2178346389
Short name T215
Test name
Test status
Simulation time 169346759507 ps
CPU time 332.08 seconds
Started Aug 16 05:14:14 PM PDT 24
Finished Aug 16 05:19:46 PM PDT 24
Peak memory 202088 kb
Host smart-a9f82f7c-3223-4871-937a-cd7cd78c5516
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178346389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2178346389
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4038852824
Short name T375
Test name
Test status
Simulation time 613781891296 ps
CPU time 681.24 seconds
Started Aug 16 05:14:19 PM PDT 24
Finished Aug 16 05:25:40 PM PDT 24
Peak memory 202040 kb
Host smart-12c33075-2304-4600-9aa8-4aa72467c69c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038852824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4038852824
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.794863132
Short name T202
Test name
Test status
Simulation time 129635508735 ps
CPU time 478.03 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:22:17 PM PDT 24
Peak memory 202272 kb
Host smart-01d79283-e0ec-478a-96f1-17dab8d5d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794863132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.794863132
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.4187805207
Short name T649
Test name
Test status
Simulation time 28816801088 ps
CPU time 70.21 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:15:28 PM PDT 24
Peak memory 201964 kb
Host smart-72b1a503-fe82-4f63-89d7-fefe3c87c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187805207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4187805207
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.442837994
Short name T485
Test name
Test status
Simulation time 4150305566 ps
CPU time 9.33 seconds
Started Aug 16 05:14:19 PM PDT 24
Finished Aug 16 05:14:29 PM PDT 24
Peak memory 201872 kb
Host smart-a4254c10-fb52-43c7-b5ea-c5bebfc71e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442837994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.442837994
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.390952904
Short name T431
Test name
Test status
Simulation time 5958091703 ps
CPU time 7.63 seconds
Started Aug 16 05:14:10 PM PDT 24
Finished Aug 16 05:14:17 PM PDT 24
Peak memory 201896 kb
Host smart-29adb099-6eaa-4125-b9cd-7fe91456ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390952904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.390952904
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3178397371
Short name T742
Test name
Test status
Simulation time 591695780298 ps
CPU time 628.94 seconds
Started Aug 16 05:14:20 PM PDT 24
Finished Aug 16 05:24:49 PM PDT 24
Peak memory 210592 kb
Host smart-d4af89db-afc7-4eef-b1c9-075b56601bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178397371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3178397371
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.690638064
Short name T334
Test name
Test status
Simulation time 175680428491 ps
CPU time 12.36 seconds
Started Aug 16 05:14:20 PM PDT 24
Finished Aug 16 05:14:32 PM PDT 24
Peak memory 210440 kb
Host smart-278d3516-ab9c-4b58-98e5-c661e6c521b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690638064 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.690638064
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2668656254
Short name T645
Test name
Test status
Simulation time 307001729 ps
CPU time 1.3 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:14:17 PM PDT 24
Peak memory 201836 kb
Host smart-10e56456-4c4d-496c-bcc8-5cb876060f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668656254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2668656254
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1483228599
Short name T314
Test name
Test status
Simulation time 175415050306 ps
CPU time 33.33 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:14:50 PM PDT 24
Peak memory 202084 kb
Host smart-8ac81810-164c-4b02-843c-cb6ab07c7ad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483228599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1483228599
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2551781587
Short name T144
Test name
Test status
Simulation time 165189140679 ps
CPU time 108.94 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:16:06 PM PDT 24
Peak memory 202128 kb
Host smart-a2fe6342-bc7b-4a7f-b8b6-0df185e09857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551781587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2551781587
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3306869456
Short name T413
Test name
Test status
Simulation time 331440477755 ps
CPU time 194.88 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:17:31 PM PDT 24
Peak memory 202084 kb
Host smart-1d1c60a5-d9e4-4adb-95b4-76374ddb6aa6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306869456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3306869456
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3904055954
Short name T775
Test name
Test status
Simulation time 324543874379 ps
CPU time 208.21 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:17:46 PM PDT 24
Peak memory 202096 kb
Host smart-217436a6-5c4b-4c37-9fc6-8d6219e89b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904055954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3904055954
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2860797259
Short name T168
Test name
Test status
Simulation time 328073319784 ps
CPU time 179.17 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:17:16 PM PDT 24
Peak memory 202088 kb
Host smart-71d3d3c6-de9a-47ec-ae50-3dd4c5ee5eb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860797259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2860797259
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.792326055
Short name T513
Test name
Test status
Simulation time 406540270292 ps
CPU time 220.96 seconds
Started Aug 16 05:14:16 PM PDT 24
Finished Aug 16 05:17:57 PM PDT 24
Peak memory 202072 kb
Host smart-48d134bc-147b-4004-917b-bb10d70abd26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792326055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.792326055
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2364821634
Short name T548
Test name
Test status
Simulation time 33938252793 ps
CPU time 16.89 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:14:35 PM PDT 24
Peak memory 201844 kb
Host smart-e0094a89-3bc0-47b7-97e6-8e566c6b5639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364821634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2364821634
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2882314641
Short name T633
Test name
Test status
Simulation time 4142453149 ps
CPU time 5.62 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:14:23 PM PDT 24
Peak memory 201952 kb
Host smart-1a8ef934-1443-4e38-9bca-0418847b1f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882314641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2882314641
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3844299332
Short name T680
Test name
Test status
Simulation time 6001565092 ps
CPU time 4.83 seconds
Started Aug 16 05:14:19 PM PDT 24
Finished Aug 16 05:14:24 PM PDT 24
Peak memory 201892 kb
Host smart-c1a58afd-bb49-4620-b6ab-a8fc3ce13d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844299332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3844299332
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2657901031
Short name T143
Test name
Test status
Simulation time 9809727190 ps
CPU time 6.39 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:14:24 PM PDT 24
Peak memory 202188 kb
Host smart-3b5526cd-8955-481f-9acd-11bbef9b2133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657901031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2657901031
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1613525362
Short name T478
Test name
Test status
Simulation time 326331274 ps
CPU time 0.88 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:14:26 PM PDT 24
Peak memory 201940 kb
Host smart-76261221-adcc-4491-a62a-a023753f1b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613525362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1613525362
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.288093409
Short name T696
Test name
Test status
Simulation time 196559786076 ps
CPU time 413.08 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:21:18 PM PDT 24
Peak memory 202012 kb
Host smart-978da3ce-26fb-41da-9326-1df01cd7754e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288093409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.288093409
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2659286001
Short name T184
Test name
Test status
Simulation time 550054104585 ps
CPU time 1009.74 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:31:15 PM PDT 24
Peak memory 202124 kb
Host smart-48ffeb54-4d83-4df3-bebd-869ccb6353e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659286001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2659286001
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1433543821
Short name T377
Test name
Test status
Simulation time 493855301725 ps
CPU time 270.62 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:18:56 PM PDT 24
Peak memory 202080 kb
Host smart-1ab483ee-24b9-4c68-958e-ab9fb4edebd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433543821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1433543821
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1069223816
Short name T187
Test name
Test status
Simulation time 488212975763 ps
CPU time 1061.8 seconds
Started Aug 16 05:14:18 PM PDT 24
Finished Aug 16 05:32:00 PM PDT 24
Peak memory 202076 kb
Host smart-7f28ded1-e743-449d-9a09-d24aeee7b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069223816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1069223816
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2436988256
Short name T563
Test name
Test status
Simulation time 166087121697 ps
CPU time 98.52 seconds
Started Aug 16 05:14:19 PM PDT 24
Finished Aug 16 05:15:57 PM PDT 24
Peak memory 202084 kb
Host smart-738b3dd0-6377-402b-9f39-43f6c83ba98b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436988256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2436988256
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1176482904
Short name T641
Test name
Test status
Simulation time 348526702782 ps
CPU time 830.01 seconds
Started Aug 16 05:14:29 PM PDT 24
Finished Aug 16 05:28:19 PM PDT 24
Peak memory 202056 kb
Host smart-d96742e0-b34f-4c5c-9f50-fb0337b1f908
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176482904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1176482904
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2976319047
Short name T787
Test name
Test status
Simulation time 412184207896 ps
CPU time 888.9 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:29:14 PM PDT 24
Peak memory 202128 kb
Host smart-1b6d8302-d45c-411d-8719-135872defd40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976319047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2976319047
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3853469633
Short name T539
Test name
Test status
Simulation time 128759657731 ps
CPU time 501.46 seconds
Started Aug 16 05:14:26 PM PDT 24
Finished Aug 16 05:22:47 PM PDT 24
Peak memory 202396 kb
Host smart-f10a640c-b0b1-4098-973e-07fa4686211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853469633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3853469633
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1874523113
Short name T482
Test name
Test status
Simulation time 25881960806 ps
CPU time 60.59 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:15:26 PM PDT 24
Peak memory 201900 kb
Host smart-7b7e1e96-3bb9-4165-99a6-f569622f14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874523113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1874523113
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.732945490
Short name T427
Test name
Test status
Simulation time 5468779526 ps
CPU time 2.66 seconds
Started Aug 16 05:14:29 PM PDT 24
Finished Aug 16 05:14:31 PM PDT 24
Peak memory 201892 kb
Host smart-29066fd4-1d51-45ae-aa21-fbcb4abe3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732945490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.732945490
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1600162774
Short name T380
Test name
Test status
Simulation time 5800317146 ps
CPU time 12.55 seconds
Started Aug 16 05:14:17 PM PDT 24
Finished Aug 16 05:14:30 PM PDT 24
Peak memory 201872 kb
Host smart-ca143206-211c-43c4-a9cc-e178f939fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600162774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1600162774
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2812574176
Short name T38
Test name
Test status
Simulation time 255644322017 ps
CPU time 730.54 seconds
Started Aug 16 05:14:27 PM PDT 24
Finished Aug 16 05:26:37 PM PDT 24
Peak memory 202392 kb
Host smart-c507f590-4647-46c9-9f40-705873309f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812574176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2812574176
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4023710188
Short name T41
Test name
Test status
Simulation time 3531438266 ps
CPU time 10.03 seconds
Started Aug 16 05:14:28 PM PDT 24
Finished Aug 16 05:14:38 PM PDT 24
Peak memory 202036 kb
Host smart-96c98da5-6d72-4581-8286-7db1c4504ae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023710188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4023710188
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3218000650
Short name T761
Test name
Test status
Simulation time 513769458 ps
CPU time 0.78 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:14:34 PM PDT 24
Peak memory 201928 kb
Host smart-3d1ad8e0-ca9f-4433-b689-0e452c36fe16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218000650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3218000650
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2169444420
Short name T212
Test name
Test status
Simulation time 565676737136 ps
CPU time 1386.49 seconds
Started Aug 16 05:14:29 PM PDT 24
Finished Aug 16 05:37:36 PM PDT 24
Peak memory 202092 kb
Host smart-85e9b674-9d0f-45e5-ae9f-41c7d8303726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169444420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2169444420
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4105447670
Short name T153
Test name
Test status
Simulation time 162489010759 ps
CPU time 149.59 seconds
Started Aug 16 05:14:24 PM PDT 24
Finished Aug 16 05:16:54 PM PDT 24
Peak memory 202028 kb
Host smart-ff6a66eb-ad9d-47e7-9349-cd476bd87cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105447670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4105447670
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.354874018
Short name T366
Test name
Test status
Simulation time 164338709599 ps
CPU time 353.41 seconds
Started Aug 16 05:14:27 PM PDT 24
Finished Aug 16 05:20:21 PM PDT 24
Peak memory 202132 kb
Host smart-b82bfac8-8330-46ae-a60f-3debc23a3809
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=354874018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.354874018
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2280522318
Short name T595
Test name
Test status
Simulation time 159440392036 ps
CPU time 175.56 seconds
Started Aug 16 05:14:27 PM PDT 24
Finished Aug 16 05:17:23 PM PDT 24
Peak memory 202072 kb
Host smart-85e12ddc-3dea-45eb-b30e-5bf4d4d321fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280522318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2280522318
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2055377911
Short name T555
Test name
Test status
Simulation time 494551013412 ps
CPU time 297.68 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:19:23 PM PDT 24
Peak memory 202100 kb
Host smart-b0907f5a-c955-4ffa-b550-0c97c37ffdb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055377911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2055377911
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2692421011
Short name T155
Test name
Test status
Simulation time 414555679645 ps
CPU time 499.15 seconds
Started Aug 16 05:14:28 PM PDT 24
Finished Aug 16 05:22:47 PM PDT 24
Peak memory 202100 kb
Host smart-a4b0765a-95b4-4b39-8a9a-78fc40e1fa3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692421011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2692421011
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4213246948
Short name T569
Test name
Test status
Simulation time 597157674599 ps
CPU time 94.71 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:15:59 PM PDT 24
Peak memory 202120 kb
Host smart-3170f998-de7e-4072-8dfa-ec8793cd1118
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213246948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4213246948
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3969362735
Short name T470
Test name
Test status
Simulation time 113687948178 ps
CPU time 414.71 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:21:28 PM PDT 24
Peak memory 202328 kb
Host smart-1d2eef74-4ee6-4649-bdc5-9771bb15f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969362735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3969362735
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3743755274
Short name T566
Test name
Test status
Simulation time 41646813189 ps
CPU time 82.01 seconds
Started Aug 16 05:14:34 PM PDT 24
Finished Aug 16 05:15:56 PM PDT 24
Peak memory 202044 kb
Host smart-eea1ea69-690e-4192-808b-0b58dbd2e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743755274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3743755274
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.586741971
Short name T786
Test name
Test status
Simulation time 4741745464 ps
CPU time 10.68 seconds
Started Aug 16 05:14:25 PM PDT 24
Finished Aug 16 05:14:36 PM PDT 24
Peak memory 201948 kb
Host smart-d168dbef-a411-4028-9d32-e92b68e37234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586741971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.586741971
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3621247260
Short name T455
Test name
Test status
Simulation time 5564426766 ps
CPU time 5.86 seconds
Started Aug 16 05:14:29 PM PDT 24
Finished Aug 16 05:14:35 PM PDT 24
Peak memory 201884 kb
Host smart-7ac06df9-12ce-43a3-a3bd-76fd2549434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621247260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3621247260
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1217099312
Short name T579
Test name
Test status
Simulation time 206924228834 ps
CPU time 499.71 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:22:53 PM PDT 24
Peak memory 202144 kb
Host smart-33d0d9ee-819f-4f82-8f48-f400eb1e9776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217099312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1217099312
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1591759799
Short name T45
Test name
Test status
Simulation time 12564448805 ps
CPU time 10.49 seconds
Started Aug 16 05:14:35 PM PDT 24
Finished Aug 16 05:14:45 PM PDT 24
Peak memory 217552 kb
Host smart-c1a82fca-be0a-42af-bd26-64e12f2fa850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591759799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1591759799
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2955287116
Short name T369
Test name
Test status
Simulation time 444446304 ps
CPU time 0.91 seconds
Started Aug 16 05:12:58 PM PDT 24
Finished Aug 16 05:12:59 PM PDT 24
Peak memory 201944 kb
Host smart-6454cf5f-475f-4add-9cf6-431527f4e07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955287116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2955287116
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3045307272
Short name T142
Test name
Test status
Simulation time 184894467990 ps
CPU time 202.2 seconds
Started Aug 16 05:12:43 PM PDT 24
Finished Aug 16 05:16:05 PM PDT 24
Peak memory 202116 kb
Host smart-ff8381f4-460d-4ce5-81d5-b93a46dd42fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045307272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3045307272
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3008007428
Short name T732
Test name
Test status
Simulation time 361792645266 ps
CPU time 182.44 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:16:16 PM PDT 24
Peak memory 202076 kb
Host smart-2be818ec-2554-4936-bde4-b08a8815d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008007428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3008007428
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1446333816
Short name T737
Test name
Test status
Simulation time 500766068433 ps
CPU time 596.32 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:22:53 PM PDT 24
Peak memory 202076 kb
Host smart-de9a2b98-7dd5-42ad-b94b-a791313dc1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446333816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1446333816
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2591592076
Short name T748
Test name
Test status
Simulation time 493782244973 ps
CPU time 276.83 seconds
Started Aug 16 05:13:08 PM PDT 24
Finished Aug 16 05:17:45 PM PDT 24
Peak memory 202120 kb
Host smart-b53779d9-09c2-4854-ae97-79cc02f5f65d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591592076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2591592076
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1867135758
Short name T157
Test name
Test status
Simulation time 165024078971 ps
CPU time 91.41 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:14:29 PM PDT 24
Peak memory 202160 kb
Host smart-21f4ab0b-f81a-4e14-b368-3871f1ba6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867135758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1867135758
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3731179217
Short name T550
Test name
Test status
Simulation time 163222122751 ps
CPU time 67.58 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:14:22 PM PDT 24
Peak memory 202084 kb
Host smart-c6ec36c1-b067-403c-b4fd-0aece532fb95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731179217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3731179217
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.158344934
Short name T615
Test name
Test status
Simulation time 200856330377 ps
CPU time 485.08 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:21:17 PM PDT 24
Peak memory 202052 kb
Host smart-93fc104a-6634-449e-93f5-460a16528ef6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158344934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.158344934
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3288126660
Short name T480
Test name
Test status
Simulation time 112698116671 ps
CPU time 653.94 seconds
Started Aug 16 05:12:43 PM PDT 24
Finished Aug 16 05:23:37 PM PDT 24
Peak memory 202328 kb
Host smart-0f0efd0d-8dae-4a8c-beda-fe970fee6a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288126660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3288126660
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2494477629
Short name T452
Test name
Test status
Simulation time 46758395513 ps
CPU time 25.46 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:46 PM PDT 24
Peak memory 201912 kb
Host smart-5d705cef-21b5-4661-bcd3-eb72b09841bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494477629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2494477629
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1616329648
Short name T86
Test name
Test status
Simulation time 2992048014 ps
CPU time 7.02 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 201932 kb
Host smart-f397a298-ebb2-4f81-9d98-c475fc3881df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616329648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1616329648
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1228383522
Short name T66
Test name
Test status
Simulation time 4354736424 ps
CPU time 9.52 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:13:19 PM PDT 24
Peak memory 217388 kb
Host smart-831f8b02-4e43-4f63-aa53-c9a95523188d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228383522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1228383522
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1659020973
Short name T752
Test name
Test status
Simulation time 5947516369 ps
CPU time 4.45 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 201868 kb
Host smart-7a0bc2c4-d1d5-43f2-9b84-f85829c375d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659020973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1659020973
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.662633516
Short name T16
Test name
Test status
Simulation time 4659809571 ps
CPU time 15.92 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:31 PM PDT 24
Peak memory 202456 kb
Host smart-1fde2caf-4239-47a8-b08e-ff87fc802cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662633516 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.662633516
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4124948829
Short name T98
Test name
Test status
Simulation time 334362085 ps
CPU time 1.38 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:14:46 PM PDT 24
Peak memory 201932 kb
Host smart-4f5c5371-6229-41f4-8cb4-939c3d76a83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124948829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4124948829
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2544474396
Short name T718
Test name
Test status
Simulation time 489000980768 ps
CPU time 1040.56 seconds
Started Aug 16 05:14:32 PM PDT 24
Finished Aug 16 05:31:52 PM PDT 24
Peak memory 202108 kb
Host smart-4411aeeb-bc65-4270-ae58-49e09bd35895
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544474396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2544474396
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2124127827
Short name T740
Test name
Test status
Simulation time 355691558629 ps
CPU time 198.9 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:17:52 PM PDT 24
Peak memory 202080 kb
Host smart-bcde9f86-4b4c-4147-a1fb-6b0969238c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124127827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2124127827
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2122057652
Short name T642
Test name
Test status
Simulation time 325797822036 ps
CPU time 199.71 seconds
Started Aug 16 05:14:31 PM PDT 24
Finished Aug 16 05:17:50 PM PDT 24
Peak memory 202092 kb
Host smart-e5ed8ba2-13c6-40b4-8c57-a41637703db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122057652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2122057652
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.629976442
Short name T713
Test name
Test status
Simulation time 487642294956 ps
CPU time 1191.42 seconds
Started Aug 16 05:14:32 PM PDT 24
Finished Aug 16 05:34:24 PM PDT 24
Peak memory 202088 kb
Host smart-b61fa3d9-cafc-41ae-8490-8b6f714e5f23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=629976442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.629976442
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1192284242
Short name T749
Test name
Test status
Simulation time 330325536071 ps
CPU time 700.2 seconds
Started Aug 16 05:14:32 PM PDT 24
Finished Aug 16 05:26:13 PM PDT 24
Peak memory 202104 kb
Host smart-2e7d6e6a-65b2-4181-859b-ef0cec5940e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192284242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1192284242
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.371419200
Short name T421
Test name
Test status
Simulation time 330723778658 ps
CPU time 328.84 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:20:02 PM PDT 24
Peak memory 201996 kb
Host smart-fa2e986d-616b-4d8f-8b4e-8beb806de532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371419200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.371419200
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.715179578
Short name T782
Test name
Test status
Simulation time 403788969320 ps
CPU time 985.6 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:30:59 PM PDT 24
Peak memory 202088 kb
Host smart-f394acae-7450-45e9-b943-ab31cea5c3ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715179578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.715179578
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.420531633
Short name T422
Test name
Test status
Simulation time 599895749186 ps
CPU time 355.52 seconds
Started Aug 16 05:14:32 PM PDT 24
Finished Aug 16 05:20:28 PM PDT 24
Peak memory 202092 kb
Host smart-fb589a98-f723-45d9-b55c-f4ee5f3c8c85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420531633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.420531633
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3858093927
Short name T702
Test name
Test status
Simulation time 100670325830 ps
CPU time 273.38 seconds
Started Aug 16 05:14:32 PM PDT 24
Finished Aug 16 05:19:06 PM PDT 24
Peak memory 202348 kb
Host smart-4f925197-a4c6-4bad-958c-286642051410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858093927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3858093927
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4122409510
Short name T767
Test name
Test status
Simulation time 38707548239 ps
CPU time 42.26 seconds
Started Aug 16 05:14:34 PM PDT 24
Finished Aug 16 05:15:16 PM PDT 24
Peak memory 202044 kb
Host smart-44ffa722-2168-4f5b-9dbf-849fc8fe069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122409510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4122409510
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.447680532
Short name T450
Test name
Test status
Simulation time 5035526356 ps
CPU time 12.8 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:14:46 PM PDT 24
Peak memory 201908 kb
Host smart-ca2d5347-7454-4828-9778-bed043ee9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447680532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.447680532
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3272178088
Short name T505
Test name
Test status
Simulation time 5931268944 ps
CPU time 4.41 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:14:37 PM PDT 24
Peak memory 201872 kb
Host smart-6d21bf67-e25f-48cb-a0e0-7952646c0075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272178088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3272178088
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.267566129
Short name T720
Test name
Test status
Simulation time 181566481020 ps
CPU time 421.24 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:21:35 PM PDT 24
Peak memory 202112 kb
Host smart-d848d90f-a34d-4d2d-a60f-75d1cd24c9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267566129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
267566129
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.879266225
Short name T9
Test name
Test status
Simulation time 7206487557 ps
CPU time 11.27 seconds
Started Aug 16 05:14:33 PM PDT 24
Finished Aug 16 05:14:44 PM PDT 24
Peak memory 202348 kb
Host smart-a394d60c-520d-4e37-96ee-ae9cc9aa9bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879266225 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.879266225
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1259244287
Short name T627
Test name
Test status
Simulation time 328463480 ps
CPU time 1.39 seconds
Started Aug 16 05:14:43 PM PDT 24
Finished Aug 16 05:14:45 PM PDT 24
Peak memory 201924 kb
Host smart-82482a9f-7e2a-4d48-91bd-7a0240688a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259244287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1259244287
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3170967337
Short name T567
Test name
Test status
Simulation time 380770703571 ps
CPU time 360.69 seconds
Started Aug 16 05:14:45 PM PDT 24
Finished Aug 16 05:20:45 PM PDT 24
Peak memory 202108 kb
Host smart-49a46b92-bd0f-4eef-90aa-aa9d55389c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170967337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3170967337
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1758907424
Short name T229
Test name
Test status
Simulation time 482889910092 ps
CPU time 1183.21 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:34:28 PM PDT 24
Peak memory 202124 kb
Host smart-cfdc8574-f097-4a10-8e2e-65c1a666c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758907424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1758907424
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2447664252
Short name T181
Test name
Test status
Simulation time 326578489506 ps
CPU time 196.01 seconds
Started Aug 16 05:14:43 PM PDT 24
Finished Aug 16 05:17:59 PM PDT 24
Peak memory 202124 kb
Host smart-e8cccc0b-6040-4ac1-903a-ab16382a509d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447664252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2447664252
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3076052720
Short name T532
Test name
Test status
Simulation time 167701889910 ps
CPU time 31.47 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:15:15 PM PDT 24
Peak memory 202072 kb
Host smart-5b234bc8-4db2-41f9-97e3-75ba0b675998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076052720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3076052720
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3574784730
Short name T501
Test name
Test status
Simulation time 496819267667 ps
CPU time 1054.86 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 202056 kb
Host smart-d8071094-9a7a-4df7-ac45-9bb22b58abf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574784730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3574784730
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1501020763
Short name T172
Test name
Test status
Simulation time 384909208579 ps
CPU time 258.01 seconds
Started Aug 16 05:14:43 PM PDT 24
Finished Aug 16 05:19:01 PM PDT 24
Peak memory 202072 kb
Host smart-b1b389f1-4619-47fd-8db6-89075fcf4152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501020763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1501020763
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2886786232
Short name T668
Test name
Test status
Simulation time 402636667313 ps
CPU time 887.73 seconds
Started Aug 16 05:14:43 PM PDT 24
Finished Aug 16 05:29:31 PM PDT 24
Peak memory 202056 kb
Host smart-413926eb-5aee-4efe-9925-ecb2fd54623a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886786232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2886786232
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2286924572
Short name T705
Test name
Test status
Simulation time 74965295736 ps
CPU time 375.3 seconds
Started Aug 16 05:14:45 PM PDT 24
Finished Aug 16 05:21:00 PM PDT 24
Peak memory 202340 kb
Host smart-a78f9178-6bf1-45d2-8a8d-3f465b73b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286924572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2286924572
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2372326858
Short name T549
Test name
Test status
Simulation time 30776131805 ps
CPU time 72.12 seconds
Started Aug 16 05:14:46 PM PDT 24
Finished Aug 16 05:15:58 PM PDT 24
Peak memory 201872 kb
Host smart-dd81e31e-2191-4f45-bf26-b54155ef9776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372326858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2372326858
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1284936460
Short name T515
Test name
Test status
Simulation time 4391250664 ps
CPU time 3.17 seconds
Started Aug 16 05:14:45 PM PDT 24
Finished Aug 16 05:14:48 PM PDT 24
Peak memory 201904 kb
Host smart-53e7fc2f-61bc-4d2d-a4c9-6d78953e578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284936460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1284936460
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3588366438
Short name T727
Test name
Test status
Simulation time 5989382473 ps
CPU time 3.35 seconds
Started Aug 16 05:14:44 PM PDT 24
Finished Aug 16 05:14:48 PM PDT 24
Peak memory 201988 kb
Host smart-9881d54c-95b1-44af-ad8e-49a9b1a464b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588366438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3588366438
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4103226614
Short name T682
Test name
Test status
Simulation time 146861628696 ps
CPU time 478.99 seconds
Started Aug 16 05:14:48 PM PDT 24
Finished Aug 16 05:22:47 PM PDT 24
Peak memory 202320 kb
Host smart-32d22509-cacc-4dd2-b250-876037b4489e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103226614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4103226614
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2532279939
Short name T613
Test name
Test status
Simulation time 19114311389 ps
CPU time 39.37 seconds
Started Aug 16 05:14:48 PM PDT 24
Finished Aug 16 05:15:28 PM PDT 24
Peak memory 210680 kb
Host smart-27fa80ab-90a5-4837-88b3-b076b7e22e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532279939 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2532279939
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2885565141
Short name T429
Test name
Test status
Simulation time 463785790 ps
CPU time 1.15 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:14:58 PM PDT 24
Peak memory 201952 kb
Host smart-9e371c8a-3d4a-47de-a24b-ccfe92fff3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885565141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2885565141
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.272712594
Short name T109
Test name
Test status
Simulation time 392929237140 ps
CPU time 33.93 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:15:31 PM PDT 24
Peak memory 202096 kb
Host smart-47e63c55-e95b-480d-a553-5e00dd003d5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272712594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.272712594
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.520905789
Short name T438
Test name
Test status
Simulation time 166469777414 ps
CPU time 203.22 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:18:20 PM PDT 24
Peak memory 202072 kb
Host smart-becd2d72-f4db-4f94-a957-f1733c98a85d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=520905789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.520905789
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.859310097
Short name T659
Test name
Test status
Simulation time 339668822939 ps
CPU time 794.8 seconds
Started Aug 16 05:14:55 PM PDT 24
Finished Aug 16 05:28:10 PM PDT 24
Peak memory 202112 kb
Host smart-5fd455e6-94d8-4e36-8578-6d5751b9f644
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859310097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.859310097
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2259259447
Short name T628
Test name
Test status
Simulation time 602255498391 ps
CPU time 318.29 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:20:14 PM PDT 24
Peak memory 202048 kb
Host smart-3489df26-31f2-454a-9ea5-7a17a6f3ee90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259259447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2259259447
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.560920896
Short name T191
Test name
Test status
Simulation time 117988971177 ps
CPU time 399.4 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:21:36 PM PDT 24
Peak memory 202396 kb
Host smart-a0b150e9-41b4-42fa-828d-dddfd4c67680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560920896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.560920896
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3442039319
Short name T418
Test name
Test status
Simulation time 42112187737 ps
CPU time 87.71 seconds
Started Aug 16 05:14:55 PM PDT 24
Finished Aug 16 05:16:23 PM PDT 24
Peak memory 201896 kb
Host smart-cd154455-5c8e-4912-9bcf-0e43462c517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442039319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3442039319
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.541308150
Short name T392
Test name
Test status
Simulation time 4771377584 ps
CPU time 6.34 seconds
Started Aug 16 05:14:58 PM PDT 24
Finished Aug 16 05:15:04 PM PDT 24
Peak memory 201952 kb
Host smart-f73b0de9-961c-45c3-bec4-ca7da3940e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541308150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.541308150
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3611804210
Short name T768
Test name
Test status
Simulation time 5823019231 ps
CPU time 14.03 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:15:11 PM PDT 24
Peak memory 201896 kb
Host smart-19e707b1-62e4-4a58-b95b-fd7f9bb178fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611804210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3611804210
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3393029099
Short name T606
Test name
Test status
Simulation time 418361165026 ps
CPU time 133.45 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:17:10 PM PDT 24
Peak memory 202136 kb
Host smart-635900d9-833a-43e6-a0e0-a31b05e0df5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393029099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3393029099
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2328961617
Short name T19
Test name
Test status
Simulation time 3338624686 ps
CPU time 8.65 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:15:05 PM PDT 24
Peak memory 210696 kb
Host smart-d50bdd7e-4ff0-40a6-9079-8c1f2264d321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328961617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2328961617
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1979503746
Short name T465
Test name
Test status
Simulation time 485781749 ps
CPU time 0.87 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:15:01 PM PDT 24
Peak memory 201856 kb
Host smart-bc9ae338-a95b-4f45-81c7-620abd5d491f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979503746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1979503746
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3862883563
Short name T57
Test name
Test status
Simulation time 180426390064 ps
CPU time 420.93 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:22:00 PM PDT 24
Peak memory 202008 kb
Host smart-a26cb06c-12d6-4c5f-ba9e-c6f4e26fe39b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862883563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3862883563
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.336588569
Short name T1
Test name
Test status
Simulation time 160664522009 ps
CPU time 346.88 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:20:47 PM PDT 24
Peak memory 202216 kb
Host smart-09120f11-f429-47c9-92ac-d9b5bc7c7cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336588569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.336588569
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2873245146
Short name T265
Test name
Test status
Simulation time 485875916843 ps
CPU time 516.29 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:23:36 PM PDT 24
Peak memory 202044 kb
Host smart-bea608e9-f29f-4540-bf78-6600982c1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873245146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2873245146
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3795067498
Short name T410
Test name
Test status
Simulation time 500166166287 ps
CPU time 1118.08 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:33:37 PM PDT 24
Peak memory 201896 kb
Host smart-9979a7f8-be9f-4344-90f0-4b296d0525d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795067498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3795067498
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3555908303
Short name T795
Test name
Test status
Simulation time 323114175490 ps
CPU time 177.5 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:17:57 PM PDT 24
Peak memory 201908 kb
Host smart-e8a59261-cd7c-4566-9530-8ccb0bb69803
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555908303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3555908303
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2658858013
Short name T671
Test name
Test status
Simulation time 193574823694 ps
CPU time 412.16 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:21:52 PM PDT 24
Peak memory 202040 kb
Host smart-7e0411a4-1c3e-40f6-b744-30dcb887ec30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658858013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2658858013
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.335581051
Short name T190
Test name
Test status
Simulation time 96972665707 ps
CPU time 413.47 seconds
Started Aug 16 05:15:02 PM PDT 24
Finished Aug 16 05:21:56 PM PDT 24
Peak memory 202324 kb
Host smart-09aedf54-de9d-4582-aaa9-0ad9516b2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335581051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.335581051
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.352947042
Short name T456
Test name
Test status
Simulation time 31725831459 ps
CPU time 65.07 seconds
Started Aug 16 05:15:09 PM PDT 24
Finished Aug 16 05:16:14 PM PDT 24
Peak memory 201912 kb
Host smart-d84abf6d-2ebd-4a99-9f81-edd2473cd44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352947042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.352947042
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3627054222
Short name T382
Test name
Test status
Simulation time 4793732334 ps
CPU time 1.3 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:14:59 PM PDT 24
Peak memory 200316 kb
Host smart-bb85fca4-c0d3-4717-a5de-7a83c5aaf80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627054222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3627054222
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2110651866
Short name T176
Test name
Test status
Simulation time 5947008857 ps
CPU time 7.84 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:15:05 PM PDT 24
Peak memory 201892 kb
Host smart-23e0f4e9-0382-49a3-a826-527b17661e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110651866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2110651866
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1346193335
Short name T778
Test name
Test status
Simulation time 1353055562 ps
CPU time 4.03 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:15:09 PM PDT 24
Peak memory 201992 kb
Host smart-02eacce1-a73b-4ba4-a0a7-e35d84017218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346193335 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1346193335
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.515376270
Short name T26
Test name
Test status
Simulation time 443909004 ps
CPU time 1.66 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:15:08 PM PDT 24
Peak memory 201972 kb
Host smart-19c8cb21-ac0f-4b5d-9faa-059be4a48872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515376270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.515376270
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.790496582
Short name T189
Test name
Test status
Simulation time 323856723677 ps
CPU time 371.49 seconds
Started Aug 16 05:14:57 PM PDT 24
Finished Aug 16 05:21:09 PM PDT 24
Peak memory 202124 kb
Host smart-0ae0f93f-9052-49ab-a2c3-475b9c67dfbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790496582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.790496582
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2897944032
Short name T99
Test name
Test status
Simulation time 162406341313 ps
CPU time 386.17 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:21:26 PM PDT 24
Peak memory 202016 kb
Host smart-d3e0e271-5f04-49b5-b5fa-b211d049bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897944032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2897944032
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1510477815
Short name T587
Test name
Test status
Simulation time 499603293266 ps
CPU time 531.2 seconds
Started Aug 16 05:14:58 PM PDT 24
Finished Aug 16 05:23:49 PM PDT 24
Peak memory 202124 kb
Host smart-323521b2-a669-4fc7-b2a3-61199cafc904
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510477815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1510477815
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.437427353
Short name T591
Test name
Test status
Simulation time 486246204965 ps
CPU time 264.83 seconds
Started Aug 16 05:14:56 PM PDT 24
Finished Aug 16 05:19:21 PM PDT 24
Peak memory 202088 kb
Host smart-79862bd0-7f4a-44e9-8d6e-af875ee336b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437427353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.437427353
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2184022241
Short name T663
Test name
Test status
Simulation time 331854007000 ps
CPU time 208.37 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:18:28 PM PDT 24
Peak memory 202068 kb
Host smart-f49b2ed0-38ef-4eab-bcd0-042ce0a54c06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184022241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2184022241
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1372772270
Short name T500
Test name
Test status
Simulation time 203052087350 ps
CPU time 240.05 seconds
Started Aug 16 05:14:59 PM PDT 24
Finished Aug 16 05:18:59 PM PDT 24
Peak memory 202052 kb
Host smart-72b99884-ffe6-4f36-b902-69b166e4753a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372772270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1372772270
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2534090202
Short name T657
Test name
Test status
Simulation time 71847496903 ps
CPU time 274.34 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:19:39 PM PDT 24
Peak memory 202364 kb
Host smart-38be0a5e-5a29-4b83-9f92-0588d3ae8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534090202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2534090202
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.169791004
Short name T463
Test name
Test status
Simulation time 37015551433 ps
CPU time 24.85 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:15:31 PM PDT 24
Peak memory 201908 kb
Host smart-0bd14041-8f68-4a3c-9c92-747cc52b7168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169791004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.169791004
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3660500190
Short name T393
Test name
Test status
Simulation time 3338785858 ps
CPU time 8.75 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:15:15 PM PDT 24
Peak memory 201824 kb
Host smart-6754f8e5-26e4-407a-84d8-686a64bc1950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660500190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3660500190
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3733130503
Short name T753
Test name
Test status
Simulation time 5851459894 ps
CPU time 4.95 seconds
Started Aug 16 05:15:00 PM PDT 24
Finished Aug 16 05:15:05 PM PDT 24
Peak memory 202032 kb
Host smart-554045db-4810-4f4e-aab0-4c0f09895fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733130503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3733130503
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.665112109
Short name T769
Test name
Test status
Simulation time 341872483405 ps
CPU time 199.28 seconds
Started Aug 16 05:15:04 PM PDT 24
Finished Aug 16 05:18:24 PM PDT 24
Peak memory 202064 kb
Host smart-3c8024ed-2e87-44a4-88b2-0dc6d197477d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665112109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
665112109
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.415867284
Short name T387
Test name
Test status
Simulation time 521321183 ps
CPU time 0.92 seconds
Started Aug 16 05:15:17 PM PDT 24
Finished Aug 16 05:15:18 PM PDT 24
Peak memory 201940 kb
Host smart-25ba472d-f7ed-4579-a967-138d88e47a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415867284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.415867284
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.383082918
Short name T135
Test name
Test status
Simulation time 335859400711 ps
CPU time 793.19 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:28:19 PM PDT 24
Peak memory 202084 kb
Host smart-ce664bbb-2ac6-46e1-9f93-4e39ad7903b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383082918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.383082918
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.532062882
Short name T347
Test name
Test status
Simulation time 170462360829 ps
CPU time 86.87 seconds
Started Aug 16 05:15:07 PM PDT 24
Finished Aug 16 05:16:34 PM PDT 24
Peak memory 202064 kb
Host smart-e0205c05-3912-4dfb-b889-e458df364420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532062882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.532062882
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2244539289
Short name T731
Test name
Test status
Simulation time 165784725155 ps
CPU time 191.29 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:18:17 PM PDT 24
Peak memory 202072 kb
Host smart-29d1d5e6-649b-40a7-948b-2600925fa8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244539289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2244539289
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2596894608
Short name T562
Test name
Test status
Simulation time 494981434165 ps
CPU time 548.88 seconds
Started Aug 16 05:15:07 PM PDT 24
Finished Aug 16 05:24:16 PM PDT 24
Peak memory 202104 kb
Host smart-12af8f19-10ae-42ab-ae87-4fa9859d4487
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596894608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2596894608
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2931496618
Short name T101
Test name
Test status
Simulation time 325422720350 ps
CPU time 745 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:27:30 PM PDT 24
Peak memory 202056 kb
Host smart-5b33f880-832f-4c3a-a1de-336886d4f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931496618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2931496618
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3244613187
Short name T363
Test name
Test status
Simulation time 491108867225 ps
CPU time 1063.95 seconds
Started Aug 16 05:15:04 PM PDT 24
Finished Aug 16 05:32:49 PM PDT 24
Peak memory 202108 kb
Host smart-f3f47d60-d423-4a9c-940e-28af59921ffb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244613187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3244613187
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2632252920
Short name T416
Test name
Test status
Simulation time 603819609076 ps
CPU time 1421.23 seconds
Started Aug 16 05:15:05 PM PDT 24
Finished Aug 16 05:38:47 PM PDT 24
Peak memory 202068 kb
Host smart-f88b3506-2116-42e0-b8de-9d6c3cfb947b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632252920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2632252920
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2614144246
Short name T607
Test name
Test status
Simulation time 40578579664 ps
CPU time 43.27 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:15:59 PM PDT 24
Peak memory 201892 kb
Host smart-16864f7b-cef1-4246-a833-9e1e3990a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614144246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2614144246
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2103880400
Short name T175
Test name
Test status
Simulation time 2883616302 ps
CPU time 7.09 seconds
Started Aug 16 05:15:04 PM PDT 24
Finished Aug 16 05:15:11 PM PDT 24
Peak memory 201928 kb
Host smart-1b84aab7-afcf-4522-894c-503322a7509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103880400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2103880400
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1254747125
Short name T683
Test name
Test status
Simulation time 5748010698 ps
CPU time 7.3 seconds
Started Aug 16 05:15:06 PM PDT 24
Finished Aug 16 05:15:14 PM PDT 24
Peak memory 201920 kb
Host smart-053c0610-cf2d-40bc-89b6-dad673cbecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254747125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1254747125
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3874370340
Short name T308
Test name
Test status
Simulation time 204905678343 ps
CPU time 151.29 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:17:46 PM PDT 24
Peak memory 202088 kb
Host smart-0097be7e-de5e-44bb-96da-dbe8024d393c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874370340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3874370340
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1585415775
Short name T743
Test name
Test status
Simulation time 2048464413 ps
CPU time 5.84 seconds
Started Aug 16 05:15:16 PM PDT 24
Finished Aug 16 05:15:22 PM PDT 24
Peak memory 201964 kb
Host smart-9f246759-a0c9-4dc8-bb6a-1464ff3ce4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585415775 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1585415775
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2761698305
Short name T797
Test name
Test status
Simulation time 343174227 ps
CPU time 1.26 seconds
Started Aug 16 05:15:24 PM PDT 24
Finished Aug 16 05:15:26 PM PDT 24
Peak memory 201940 kb
Host smart-6275e318-46a8-4b27-a6a8-60521de63496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761698305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2761698305
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2746713602
Short name T291
Test name
Test status
Simulation time 524819075905 ps
CPU time 389.81 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:21:46 PM PDT 24
Peak memory 202096 kb
Host smart-4c301509-af01-4691-84f7-117762a9488b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746713602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2746713602
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.974285835
Short name T597
Test name
Test status
Simulation time 335521630970 ps
CPU time 807.43 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:28:43 PM PDT 24
Peak memory 202076 kb
Host smart-8d53427f-d531-4067-add3-fca57c9fffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974285835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.974285835
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.338280173
Short name T541
Test name
Test status
Simulation time 167402873578 ps
CPU time 375.63 seconds
Started Aug 16 05:15:16 PM PDT 24
Finished Aug 16 05:21:32 PM PDT 24
Peak memory 202072 kb
Host smart-8a37f082-f321-4121-9653-1fc8afe8b7ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=338280173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.338280173
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4029699524
Short name T284
Test name
Test status
Simulation time 162551647673 ps
CPU time 390.86 seconds
Started Aug 16 05:15:16 PM PDT 24
Finished Aug 16 05:21:48 PM PDT 24
Peak memory 202056 kb
Host smart-eb3e666f-1b64-479d-a692-301766a86182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029699524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4029699524
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.400074300
Short name T635
Test name
Test status
Simulation time 323194527982 ps
CPU time 780.89 seconds
Started Aug 16 05:15:17 PM PDT 24
Finished Aug 16 05:28:18 PM PDT 24
Peak memory 202032 kb
Host smart-2ca006f3-be3b-40ae-98f3-aed32386fda4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=400074300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.400074300
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2695075619
Short name T285
Test name
Test status
Simulation time 476216431499 ps
CPU time 978.74 seconds
Started Aug 16 05:15:17 PM PDT 24
Finished Aug 16 05:31:36 PM PDT 24
Peak memory 202000 kb
Host smart-f0ef58d3-683f-490a-b678-2d3a008557d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695075619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2695075619
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2489065971
Short name T457
Test name
Test status
Simulation time 193952510041 ps
CPU time 107.14 seconds
Started Aug 16 05:15:17 PM PDT 24
Finished Aug 16 05:17:04 PM PDT 24
Peak memory 202092 kb
Host smart-e3c4bd5a-5ce3-426a-9c07-22ca8cf46220
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489065971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2489065971
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3960942298
Short name T582
Test name
Test status
Simulation time 94277970657 ps
CPU time 540.62 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:24:23 PM PDT 24
Peak memory 202268 kb
Host smart-ebb7b61d-e6ea-4b19-b2a4-06372b1ccd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960942298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3960942298
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2157515294
Short name T439
Test name
Test status
Simulation time 27858346571 ps
CPU time 66.44 seconds
Started Aug 16 05:15:17 PM PDT 24
Finished Aug 16 05:16:24 PM PDT 24
Peak memory 201840 kb
Host smart-17a579f6-ee94-40d8-aa46-3790f496f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157515294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2157515294
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.920244104
Short name T527
Test name
Test status
Simulation time 4383268808 ps
CPU time 10.79 seconds
Started Aug 16 05:15:15 PM PDT 24
Finished Aug 16 05:15:26 PM PDT 24
Peak memory 201912 kb
Host smart-487c44ee-dc88-4433-8c3d-63ef7c7a6109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920244104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.920244104
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1061662922
Short name T407
Test name
Test status
Simulation time 6033156838 ps
CPU time 3.18 seconds
Started Aug 16 05:15:19 PM PDT 24
Finished Aug 16 05:15:22 PM PDT 24
Peak memory 201912 kb
Host smart-14214230-c9a5-435e-9408-31a145a48974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061662922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1061662922
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1707364867
Short name T251
Test name
Test status
Simulation time 337518274348 ps
CPU time 721.2 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:27:24 PM PDT 24
Peak memory 202088 kb
Host smart-a556ba88-2265-45d9-9f06-b8ab59d6c691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707364867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1707364867
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1500163519
Short name T61
Test name
Test status
Simulation time 1050608124 ps
CPU time 2.11 seconds
Started Aug 16 05:15:27 PM PDT 24
Finished Aug 16 05:15:30 PM PDT 24
Peak memory 201928 kb
Host smart-e841b646-4c2d-4013-aa3c-9f400244c1bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500163519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1500163519
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3544579498
Short name T73
Test name
Test status
Simulation time 476080215 ps
CPU time 1.78 seconds
Started Aug 16 05:15:25 PM PDT 24
Finished Aug 16 05:15:27 PM PDT 24
Peak memory 201932 kb
Host smart-61dbf506-8ec5-4049-aeb0-cf20c839d3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544579498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3544579498
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2689914977
Short name T275
Test name
Test status
Simulation time 165442435361 ps
CPU time 364.91 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:21:28 PM PDT 24
Peak memory 202108 kb
Host smart-9e8dfb64-7bde-45be-9a19-5d49467f42e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689914977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2689914977
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.560621386
Short name T552
Test name
Test status
Simulation time 170061876518 ps
CPU time 323.76 seconds
Started Aug 16 05:15:24 PM PDT 24
Finished Aug 16 05:20:48 PM PDT 24
Peak memory 202144 kb
Host smart-7cec64dd-12bc-4c5f-8cb6-aa4cca8d3798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560621386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.560621386
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1804230716
Short name T561
Test name
Test status
Simulation time 328887223211 ps
CPU time 720.36 seconds
Started Aug 16 05:15:24 PM PDT 24
Finished Aug 16 05:27:24 PM PDT 24
Peak memory 202068 kb
Host smart-34312f67-d637-4f4b-837d-223e81034b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804230716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1804230716
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.371238880
Short name T93
Test name
Test status
Simulation time 334725513336 ps
CPU time 812.87 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:28:56 PM PDT 24
Peak memory 202080 kb
Host smart-0fcd808c-dd20-4b53-be73-bc66637ca3c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371238880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.371238880
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3265427884
Short name T691
Test name
Test status
Simulation time 165691520641 ps
CPU time 78.21 seconds
Started Aug 16 05:15:22 PM PDT 24
Finished Aug 16 05:16:40 PM PDT 24
Peak memory 202088 kb
Host smart-9ce31ce4-3273-45e9-949e-280f2af2bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265427884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3265427884
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2218621091
Short name T631
Test name
Test status
Simulation time 332159623457 ps
CPU time 381.34 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:21:45 PM PDT 24
Peak memory 202056 kb
Host smart-2c8f548c-ca57-413c-92c8-41e9ab018527
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218621091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2218621091
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2668294631
Short name T214
Test name
Test status
Simulation time 592223151539 ps
CPU time 1267.18 seconds
Started Aug 16 05:15:22 PM PDT 24
Finished Aug 16 05:36:29 PM PDT 24
Peak memory 202096 kb
Host smart-b8f1b57d-388c-4824-809a-dd96fdeb43cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668294631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2668294631
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1315023312
Short name T432
Test name
Test status
Simulation time 199992901870 ps
CPU time 405.72 seconds
Started Aug 16 05:15:23 PM PDT 24
Finished Aug 16 05:22:09 PM PDT 24
Peak memory 202096 kb
Host smart-274593c0-55c6-4f8c-a906-890ba5edf503
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315023312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1315023312
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2170110097
Short name T205
Test name
Test status
Simulation time 131235660924 ps
CPU time 518.44 seconds
Started Aug 16 05:15:26 PM PDT 24
Finished Aug 16 05:24:05 PM PDT 24
Peak memory 202284 kb
Host smart-00938030-6793-42cf-95c7-3444ac86b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170110097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2170110097
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3527767538
Short name T442
Test name
Test status
Simulation time 35888331177 ps
CPU time 72.21 seconds
Started Aug 16 05:15:22 PM PDT 24
Finished Aug 16 05:16:34 PM PDT 24
Peak memory 201892 kb
Host smart-94fcd56a-dfb8-4ac1-992d-85c0c355162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527767538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3527767538
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1490984008
Short name T396
Test name
Test status
Simulation time 5339012893 ps
CPU time 12.47 seconds
Started Aug 16 05:15:25 PM PDT 24
Finished Aug 16 05:15:38 PM PDT 24
Peak memory 201908 kb
Host smart-5e30855f-5aaa-45b7-bf71-8bcd542f851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490984008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1490984008
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1743907456
Short name T401
Test name
Test status
Simulation time 5534435207 ps
CPU time 13.9 seconds
Started Aug 16 05:15:22 PM PDT 24
Finished Aug 16 05:15:37 PM PDT 24
Peak memory 201904 kb
Host smart-da9317cf-1ce7-49fa-8073-fc8c869ccb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743907456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1743907456
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2023731728
Short name T553
Test name
Test status
Simulation time 385189860 ps
CPU time 1.5 seconds
Started Aug 16 05:15:45 PM PDT 24
Finished Aug 16 05:15:46 PM PDT 24
Peak memory 201916 kb
Host smart-df3ec373-2c2f-42d2-8a3e-142c26f56362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023731728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2023731728
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1556753037
Short name T604
Test name
Test status
Simulation time 163344929752 ps
CPU time 177.73 seconds
Started Aug 16 05:15:29 PM PDT 24
Finished Aug 16 05:18:27 PM PDT 24
Peak memory 202104 kb
Host smart-7ec390bc-4a21-485a-8acc-c78b587ea5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556753037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1556753037
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1370905177
Short name T279
Test name
Test status
Simulation time 159872808479 ps
CPU time 200.22 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:18:50 PM PDT 24
Peak memory 202080 kb
Host smart-5844b0ce-b898-4038-8356-09ffd81b2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370905177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1370905177
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4192445510
Short name T441
Test name
Test status
Simulation time 491384641335 ps
CPU time 150.55 seconds
Started Aug 16 05:15:29 PM PDT 24
Finished Aug 16 05:18:00 PM PDT 24
Peak memory 202088 kb
Host smart-bf483bee-6002-4f0b-9c38-f035dae1899f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192445510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4192445510
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2034809720
Short name T739
Test name
Test status
Simulation time 163443246922 ps
CPU time 64.79 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:16:35 PM PDT 24
Peak memory 202120 kb
Host smart-68f3a4c4-af51-4997-b612-1a84e541ac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034809720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2034809720
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.136192128
Short name T360
Test name
Test status
Simulation time 502483977827 ps
CPU time 1206.57 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:35:37 PM PDT 24
Peak memory 201688 kb
Host smart-7163a118-985b-4ee8-814b-5301e59f695b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=136192128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.136192128
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4227962501
Short name T677
Test name
Test status
Simulation time 343110876138 ps
CPU time 284.21 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:20:14 PM PDT 24
Peak memory 202104 kb
Host smart-b460a164-e902-433b-ac1b-7ec119335671
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227962501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4227962501
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1888150942
Short name T440
Test name
Test status
Simulation time 201987353691 ps
CPU time 447.58 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:22:57 PM PDT 24
Peak memory 202092 kb
Host smart-8cff3443-949e-4ad3-aa39-c7fa96b6dded
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888150942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1888150942
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3422779286
Short name T358
Test name
Test status
Simulation time 101919439749 ps
CPU time 613.83 seconds
Started Aug 16 05:15:30 PM PDT 24
Finished Aug 16 05:25:45 PM PDT 24
Peak memory 202016 kb
Host smart-e9cb8364-fa53-44ee-9f55-027acda055a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422779286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3422779286
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2772092684
Short name T503
Test name
Test status
Simulation time 30096491784 ps
CPU time 20.72 seconds
Started Aug 16 05:15:31 PM PDT 24
Finished Aug 16 05:15:52 PM PDT 24
Peak memory 201888 kb
Host smart-da4eaede-8c7d-4ca4-a71f-394a84486c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772092684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2772092684
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2811649191
Short name T538
Test name
Test status
Simulation time 4191005915 ps
CPU time 9.39 seconds
Started Aug 16 05:15:29 PM PDT 24
Finished Aug 16 05:15:39 PM PDT 24
Peak memory 201824 kb
Host smart-923820e1-1cf5-4d48-a4a3-2c976a08a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811649191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2811649191
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.543849801
Short name T437
Test name
Test status
Simulation time 5661835837 ps
CPU time 14.24 seconds
Started Aug 16 05:15:22 PM PDT 24
Finished Aug 16 05:15:37 PM PDT 24
Peak memory 201988 kb
Host smart-ee264519-a904-4b2d-9c0e-e1dc8403f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543849801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.543849801
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3697425915
Short name T665
Test name
Test status
Simulation time 406630331045 ps
CPU time 61.11 seconds
Started Aug 16 05:15:39 PM PDT 24
Finished Aug 16 05:16:40 PM PDT 24
Peak memory 202168 kb
Host smart-eaf15c51-cee5-459f-b5c4-74b2de09695b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697425915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3697425915
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1799478965
Short name T750
Test name
Test status
Simulation time 3112814692 ps
CPU time 10.91 seconds
Started Aug 16 05:15:32 PM PDT 24
Finished Aug 16 05:15:43 PM PDT 24
Peak memory 210692 kb
Host smart-fa177b9a-6d37-4428-95b6-a08271527f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799478965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1799478965
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3928832019
Short name T394
Test name
Test status
Simulation time 494260252 ps
CPU time 0.73 seconds
Started Aug 16 05:15:50 PM PDT 24
Finished Aug 16 05:15:50 PM PDT 24
Peak memory 201892 kb
Host smart-0081d08f-0b7b-4794-964f-345c3d0bd666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928832019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3928832019
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1586211329
Short name T160
Test name
Test status
Simulation time 504461769001 ps
CPU time 1233 seconds
Started Aug 16 05:15:46 PM PDT 24
Finished Aug 16 05:36:19 PM PDT 24
Peak memory 202116 kb
Host smart-6bc07320-5b64-4d6d-9fa1-8a37f288e251
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586211329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1586211329
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.789565368
Short name T228
Test name
Test status
Simulation time 183586368705 ps
CPU time 109.85 seconds
Started Aug 16 05:15:38 PM PDT 24
Finished Aug 16 05:17:28 PM PDT 24
Peak memory 202112 kb
Host smart-de2df8fe-ae11-45be-9eed-16c91e2dd2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789565368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.789565368
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3073607841
Short name T114
Test name
Test status
Simulation time 325503702713 ps
CPU time 158.19 seconds
Started Aug 16 05:15:37 PM PDT 24
Finished Aug 16 05:18:16 PM PDT 24
Peak memory 202028 kb
Host smart-fa0221e2-aa01-4b5b-9d63-5ba64e75b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073607841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3073607841
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1010690397
Short name T6
Test name
Test status
Simulation time 330081031884 ps
CPU time 215.38 seconds
Started Aug 16 05:15:37 PM PDT 24
Finished Aug 16 05:19:13 PM PDT 24
Peak memory 202104 kb
Host smart-5d69ae0b-952d-4f0c-896a-e46480e9cdbb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010690397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1010690397
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2176053463
Short name T28
Test name
Test status
Simulation time 164268706195 ps
CPU time 200.39 seconds
Started Aug 16 05:15:38 PM PDT 24
Finished Aug 16 05:18:59 PM PDT 24
Peak memory 202100 kb
Host smart-882c02f8-c19c-45f0-8858-aff5ec875a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176053463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2176053463
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2441049861
Short name T724
Test name
Test status
Simulation time 487277218957 ps
CPU time 275.22 seconds
Started Aug 16 05:15:37 PM PDT 24
Finished Aug 16 05:20:13 PM PDT 24
Peak memory 202040 kb
Host smart-b72c0bb9-731e-400e-8224-309c48bff6e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441049861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2441049861
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1462563109
Short name T637
Test name
Test status
Simulation time 170723834185 ps
CPU time 398.25 seconds
Started Aug 16 05:15:39 PM PDT 24
Finished Aug 16 05:22:18 PM PDT 24
Peak memory 202080 kb
Host smart-d90d8a6c-eb0c-4876-9483-885ee09a9254
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462563109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1462563109
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1656250499
Short name T716
Test name
Test status
Simulation time 197697553790 ps
CPU time 142.64 seconds
Started Aug 16 05:15:37 PM PDT 24
Finished Aug 16 05:18:00 PM PDT 24
Peak memory 202088 kb
Host smart-3e870a45-b503-4334-9abf-e0f8f9a09c57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656250499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1656250499
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3739456922
Short name T193
Test name
Test status
Simulation time 91417240873 ps
CPU time 349.58 seconds
Started Aug 16 05:15:45 PM PDT 24
Finished Aug 16 05:21:35 PM PDT 24
Peak memory 202404 kb
Host smart-4c7e44b1-1ae2-46e0-b964-aec84f52cac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739456922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3739456922
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.87990824
Short name T464
Test name
Test status
Simulation time 23427346444 ps
CPU time 14.18 seconds
Started Aug 16 05:15:42 PM PDT 24
Finished Aug 16 05:15:56 PM PDT 24
Peak memory 201872 kb
Host smart-c11035d5-375f-4a55-8d76-b3694f3b0a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87990824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.87990824
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3485434773
Short name T531
Test name
Test status
Simulation time 4985879834 ps
CPU time 3.77 seconds
Started Aug 16 05:15:40 PM PDT 24
Finished Aug 16 05:15:44 PM PDT 24
Peak memory 201920 kb
Host smart-239e7709-92ee-45d5-9054-70236e0dc779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485434773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3485434773
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3991663239
Short name T638
Test name
Test status
Simulation time 5987655087 ps
CPU time 13.16 seconds
Started Aug 16 05:15:47 PM PDT 24
Finished Aug 16 05:16:00 PM PDT 24
Peak memory 201888 kb
Host smart-a78b5a7d-c637-4a9b-ae5f-ca6dd215dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991663239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3991663239
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4224733472
Short name T679
Test name
Test status
Simulation time 195929651731 ps
CPU time 474.25 seconds
Started Aug 16 05:15:48 PM PDT 24
Finished Aug 16 05:23:42 PM PDT 24
Peak memory 202052 kb
Host smart-1be9baef-d288-47f4-9dce-692b77e0ea13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224733472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4224733472
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.214075144
Short name T497
Test name
Test status
Simulation time 3242480774 ps
CPU time 5.42 seconds
Started Aug 16 05:15:46 PM PDT 24
Finished Aug 16 05:15:52 PM PDT 24
Peak memory 210460 kb
Host smart-8ddb9790-c76d-41be-98ea-b220fe79ee0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214075144 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.214075144
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1598747869
Short name T688
Test name
Test status
Simulation time 360569948 ps
CPU time 1.03 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:15 PM PDT 24
Peak memory 201928 kb
Host smart-0fa9897c-a98e-425f-a14b-c39a22e375b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598747869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1598747869
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.917587840
Short name T226
Test name
Test status
Simulation time 329779402129 ps
CPU time 735.8 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:25:21 PM PDT 24
Peak memory 202064 kb
Host smart-82b8826f-55c2-426f-9e68-90f09d5751af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917587840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.917587840
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.657880427
Short name T254
Test name
Test status
Simulation time 182531421163 ps
CPU time 220.27 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:16:37 PM PDT 24
Peak memory 202112 kb
Host smart-95350103-18b8-4188-9e2b-3808f8886526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657880427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.657880427
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1977328440
Short name T545
Test name
Test status
Simulation time 322446278626 ps
CPU time 347.37 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:19:02 PM PDT 24
Peak memory 202120 kb
Host smart-f13f3a31-c6b9-4aeb-8c0a-d682629efd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977328440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1977328440
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2650689524
Short name T781
Test name
Test status
Simulation time 161420641159 ps
CPU time 199.86 seconds
Started Aug 16 05:13:04 PM PDT 24
Finished Aug 16 05:16:24 PM PDT 24
Peak memory 202204 kb
Host smart-0c109d97-072f-4e12-8408-5c3f8e4da0b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650689524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2650689524
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2317337707
Short name T286
Test name
Test status
Simulation time 488269993446 ps
CPU time 1166.36 seconds
Started Aug 16 05:12:58 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 202112 kb
Host smart-a7305b71-109a-46e6-aad4-66bdbf99e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317337707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2317337707
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3035081084
Short name T468
Test name
Test status
Simulation time 163248876618 ps
CPU time 335.28 seconds
Started Aug 16 05:12:51 PM PDT 24
Finished Aug 16 05:18:27 PM PDT 24
Peak memory 202080 kb
Host smart-b50cb689-feb4-4a31-a161-338269a16e3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035081084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3035081084
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2893766352
Short name T449
Test name
Test status
Simulation time 621819762349 ps
CPU time 364.54 seconds
Started Aug 16 05:12:54 PM PDT 24
Finished Aug 16 05:18:59 PM PDT 24
Peak memory 202100 kb
Host smart-0ca791d9-5f88-4f40-81b2-c507a4963a38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893766352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2893766352
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1229903779
Short name T723
Test name
Test status
Simulation time 122295930418 ps
CPU time 633.19 seconds
Started Aug 16 05:13:07 PM PDT 24
Finished Aug 16 05:23:40 PM PDT 24
Peak memory 202340 kb
Host smart-4ee07e00-8740-4850-aef5-d54623f9adb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229903779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1229903779
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3919527913
Short name T784
Test name
Test status
Simulation time 26970403890 ps
CPU time 31.13 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:13:28 PM PDT 24
Peak memory 201876 kb
Host smart-b653ba06-200c-49ad-8b13-768840aecf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919527913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3919527913
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4214026110
Short name T412
Test name
Test status
Simulation time 4004220732 ps
CPU time 1.43 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 201904 kb
Host smart-67461ad0-a36f-4699-b583-d5a4844e593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214026110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4214026110
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3086085513
Short name T589
Test name
Test status
Simulation time 6073406498 ps
CPU time 8.55 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:13:04 PM PDT 24
Peak memory 201920 kb
Host smart-a16e240e-cac5-46c7-8cb6-66f6e5a00641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086085513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3086085513
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2670463152
Short name T204
Test name
Test status
Simulation time 350878379602 ps
CPU time 1156.2 seconds
Started Aug 16 05:12:57 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 202292 kb
Host smart-e9ad410d-3efe-4dc5-93b3-86968e1161c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670463152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2670463152
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1823318913
Short name T24
Test name
Test status
Simulation time 1878820189 ps
CPU time 5.27 seconds
Started Aug 16 05:12:55 PM PDT 24
Finished Aug 16 05:13:00 PM PDT 24
Peak memory 202188 kb
Host smart-99cee5ae-b13d-4fff-9365-11e26f2ead7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823318913 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1823318913
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.729779009
Short name T729
Test name
Test status
Simulation time 487012150 ps
CPU time 1.75 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:13:15 PM PDT 24
Peak memory 201908 kb
Host smart-e9fa0912-dbc8-4c39-8f28-5734e12f2eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729779009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.729779009
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3119564253
Short name T294
Test name
Test status
Simulation time 164960865471 ps
CPU time 103.34 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:14:56 PM PDT 24
Peak memory 202088 kb
Host smart-25a9f2b6-57a4-4e0e-b7c3-598af9cd426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119564253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3119564253
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1934098601
Short name T451
Test name
Test status
Simulation time 328667111777 ps
CPU time 713.19 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:24:55 PM PDT 24
Peak memory 202160 kb
Host smart-ff5eba66-70cb-4153-b54d-6b0f64f6ef69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934098601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1934098601
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1108234875
Short name T517
Test name
Test status
Simulation time 164631494647 ps
CPU time 182.96 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:16:09 PM PDT 24
Peak memory 202080 kb
Host smart-9c17c563-2938-480c-9f2d-8fdebb3e58de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108234875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1108234875
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2887362830
Short name T612
Test name
Test status
Simulation time 482097254336 ps
CPU time 285.37 seconds
Started Aug 16 05:12:45 PM PDT 24
Finished Aug 16 05:17:31 PM PDT 24
Peak memory 202028 kb
Host smart-fff51133-4a9c-4457-87fa-65f3229c94cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887362830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2887362830
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2383439323
Short name T185
Test name
Test status
Simulation time 522704144321 ps
CPU time 87.1 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:14:41 PM PDT 24
Peak memory 202004 kb
Host smart-dee49a21-7dd8-4e30-a1c9-f9a5cf82cd3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383439323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2383439323
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1168785915
Short name T773
Test name
Test status
Simulation time 203121741636 ps
CPU time 108.94 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:14:54 PM PDT 24
Peak memory 202180 kb
Host smart-616d38e8-d6bf-46e6-aac6-18cbac91cd70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168785915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1168785915
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.485208230
Short name T686
Test name
Test status
Simulation time 101275555175 ps
CPU time 526.04 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:21:53 PM PDT 24
Peak memory 202324 kb
Host smart-a1070687-7728-4c8b-b994-b927bed8df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485208230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.485208230
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1863655078
Short name T415
Test name
Test status
Simulation time 35613693405 ps
CPU time 78.97 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:14:32 PM PDT 24
Peak memory 201900 kb
Host smart-fb419c8f-0793-4079-b98e-864ebe5c80cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863655078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1863655078
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3450295921
Short name T433
Test name
Test status
Simulation time 5479902482 ps
CPU time 1.55 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:13:07 PM PDT 24
Peak memory 201908 kb
Host smart-467d95ec-7aff-4a5e-84cd-b663678fa027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450295921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3450295921
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1156848604
Short name T409
Test name
Test status
Simulation time 5884788414 ps
CPU time 14.67 seconds
Started Aug 16 05:12:56 PM PDT 24
Finished Aug 16 05:13:10 PM PDT 24
Peak memory 201872 kb
Host smart-791f8bac-7116-4e1e-b89e-f8083d9bd341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156848604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1156848604
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1414158665
Short name T759
Test name
Test status
Simulation time 4232498694 ps
CPU time 6.07 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:13:12 PM PDT 24
Peak memory 201988 kb
Host smart-1a10df57-86ce-42fe-abae-60de57c43e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414158665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1414158665
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3343226281
Short name T506
Test name
Test status
Simulation time 1674580816 ps
CPU time 4.47 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:13:10 PM PDT 24
Peak memory 202000 kb
Host smart-de73b476-b2a4-46ef-ad1e-0a9333f74a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343226281 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3343226281
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.521754155
Short name T509
Test name
Test status
Simulation time 406303384 ps
CPU time 1.51 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:13:10 PM PDT 24
Peak memory 201960 kb
Host smart-e8927f0a-cd68-4d34-912b-d72629839ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521754155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.521754155
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2014732337
Short name T307
Test name
Test status
Simulation time 536314755999 ps
CPU time 858.2 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:27:28 PM PDT 24
Peak memory 202092 kb
Host smart-88adbd5c-1ca3-4d3f-853d-0f69e0f01cef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014732337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2014732337
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2878270569
Short name T164
Test name
Test status
Simulation time 327706672463 ps
CPU time 47.39 seconds
Started Aug 16 05:13:08 PM PDT 24
Finished Aug 16 05:13:56 PM PDT 24
Peak memory 202148 kb
Host smart-cb8e18c5-1de9-4bca-9532-ec9c660b0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878270569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2878270569
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3469908636
Short name T273
Test name
Test status
Simulation time 333309218614 ps
CPU time 352.92 seconds
Started Aug 16 05:13:03 PM PDT 24
Finished Aug 16 05:18:56 PM PDT 24
Peak memory 202068 kb
Host smart-35136737-dfc1-4a24-87e9-b5601b65e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469908636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3469908636
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.245909202
Short name T623
Test name
Test status
Simulation time 163124512512 ps
CPU time 179.54 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:15:59 PM PDT 24
Peak memory 202100 kb
Host smart-6b839c8b-8ef1-47f1-8278-ee42ec06d704
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=245909202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.245909202
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.802368758
Short name T575
Test name
Test status
Simulation time 483038896830 ps
CPU time 1126.98 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:31:57 PM PDT 24
Peak memory 202012 kb
Host smart-f36d7b2d-59cc-48c2-93f8-8a37c05c58df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802368758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.802368758
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.583155967
Short name T453
Test name
Test status
Simulation time 333180897166 ps
CPU time 385.81 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:19:42 PM PDT 24
Peak memory 202060 kb
Host smart-8ee61632-c7f2-41a7-98bd-fe9cb4d8bc25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=583155967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.583155967
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.651862132
Short name T171
Test name
Test status
Simulation time 345672191120 ps
CPU time 200.39 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:16:31 PM PDT 24
Peak memory 202136 kb
Host smart-46e70726-c302-4ad5-9c9c-8580a2ba7b8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651862132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.651862132
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.871840230
Short name T12
Test name
Test status
Simulation time 215318194150 ps
CPU time 253.28 seconds
Started Aug 16 05:13:07 PM PDT 24
Finished Aug 16 05:17:21 PM PDT 24
Peak memory 202056 kb
Host smart-9af9af3e-f6a2-4d77-ab43-8c0113ef187a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871840230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.871840230
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3437187860
Short name T357
Test name
Test status
Simulation time 93647118771 ps
CPU time 474.78 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:20:57 PM PDT 24
Peak memory 202336 kb
Host smart-51e547ef-1bd3-49bb-9cfb-de505583a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437187860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3437187860
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3161553316
Short name T502
Test name
Test status
Simulation time 30909283592 ps
CPU time 25.27 seconds
Started Aug 16 05:13:04 PM PDT 24
Finished Aug 16 05:13:29 PM PDT 24
Peak memory 201872 kb
Host smart-abae66a4-da4f-4909-9e20-1a603bc83299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161553316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3161553316
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.549948676
Short name T504
Test name
Test status
Simulation time 4847563709 ps
CPU time 6.54 seconds
Started Aug 16 05:13:01 PM PDT 24
Finished Aug 16 05:13:08 PM PDT 24
Peak memory 201964 kb
Host smart-c0d4a333-5b19-4e15-b27e-9960a3d2410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549948676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.549948676
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1447567055
Short name T447
Test name
Test status
Simulation time 5778059113 ps
CPU time 2.84 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:13:05 PM PDT 24
Peak memory 201876 kb
Host smart-e44cf4a7-d6f2-45b8-bd52-ddbcf4f23d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447567055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1447567055
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3441432197
Short name T18
Test name
Test status
Simulation time 12836379592 ps
CPU time 4.93 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:13:17 PM PDT 24
Peak memory 210392 kb
Host smart-c99930b6-4638-4261-a101-de2e91d336cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441432197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3441432197
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1919244116
Short name T364
Test name
Test status
Simulation time 351688695 ps
CPU time 1.15 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:13:03 PM PDT 24
Peak memory 201924 kb
Host smart-eabfe633-3083-4d15-a45b-24cbba1febd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919244116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1919244116
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.4151152524
Short name T348
Test name
Test status
Simulation time 378290089894 ps
CPU time 365.6 seconds
Started Aug 16 05:13:08 PM PDT 24
Finished Aug 16 05:19:13 PM PDT 24
Peak memory 202016 kb
Host smart-45e46391-aed0-49ae-878b-2abcd23d18cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151152524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.4151152524
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3904440838
Short name T293
Test name
Test status
Simulation time 167009304049 ps
CPU time 71.66 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:14:17 PM PDT 24
Peak memory 202032 kb
Host smart-35e277a9-9ed5-4a02-9515-6fdef5ecf1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904440838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3904440838
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1065220547
Short name T342
Test name
Test status
Simulation time 162570919676 ps
CPU time 100.68 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:14:54 PM PDT 24
Peak memory 202076 kb
Host smart-3bb91865-7184-44a2-99f6-159b88530410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065220547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1065220547
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3590511773
Short name T529
Test name
Test status
Simulation time 321345229556 ps
CPU time 363.01 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:19:16 PM PDT 24
Peak memory 202124 kb
Host smart-c30ca097-c86b-4400-9a70-6a506d927702
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590511773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3590511773
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4241241193
Short name T629
Test name
Test status
Simulation time 496149719367 ps
CPU time 269.34 seconds
Started Aug 16 05:13:05 PM PDT 24
Finished Aug 16 05:17:34 PM PDT 24
Peak memory 202144 kb
Host smart-f21b29ff-f5c1-4de6-9a9d-3f4c18b22c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241241193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4241241193
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1312468354
Short name T678
Test name
Test status
Simulation time 486348714319 ps
CPU time 1152.89 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 202080 kb
Host smart-e3387a77-dc1e-4bac-8893-2b15cc5d0c57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312468354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1312468354
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2127193200
Short name T167
Test name
Test status
Simulation time 374670919728 ps
CPU time 221.58 seconds
Started Aug 16 05:13:10 PM PDT 24
Finished Aug 16 05:16:51 PM PDT 24
Peak memory 202096 kb
Host smart-25d2afb0-8c06-4d22-9a45-f9347cc3e53d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127193200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2127193200
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3935097144
Short name T486
Test name
Test status
Simulation time 602564112625 ps
CPU time 344.1 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:18:58 PM PDT 24
Peak memory 202084 kb
Host smart-96b3657a-49bb-48a0-8a02-397958fd0444
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935097144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3935097144
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2333718087
Short name T793
Test name
Test status
Simulation time 127532042962 ps
CPU time 614.67 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:23:29 PM PDT 24
Peak memory 202356 kb
Host smart-d9d49929-1801-4d49-9d99-76018c093c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333718087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2333718087
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1683108273
Short name T391
Test name
Test status
Simulation time 24968684215 ps
CPU time 14.26 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 201904 kb
Host smart-10ad8875-97d8-45ac-af3e-94b12c5340c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683108273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1683108273
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.628257562
Short name T511
Test name
Test status
Simulation time 4028550040 ps
CPU time 9.98 seconds
Started Aug 16 05:13:15 PM PDT 24
Finished Aug 16 05:13:25 PM PDT 24
Peak memory 201920 kb
Host smart-73f55d89-fad8-43a3-b868-45732e0b5bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628257562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.628257562
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3515487425
Short name T704
Test name
Test status
Simulation time 5757908945 ps
CPU time 3.34 seconds
Started Aug 16 05:13:09 PM PDT 24
Finished Aug 16 05:13:12 PM PDT 24
Peak memory 201908 kb
Host smart-e5386161-99bf-4772-874f-3578097ab1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515487425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3515487425
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1878899100
Short name T336
Test name
Test status
Simulation time 330668473803 ps
CPU time 781.81 seconds
Started Aug 16 05:13:12 PM PDT 24
Finished Aug 16 05:26:14 PM PDT 24
Peak memory 202104 kb
Host smart-1bd2ec6e-60c0-43d5-96b7-824c93f0a55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878899100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1878899100
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.475178745
Short name T130
Test name
Test status
Simulation time 156774675004 ps
CPU time 13.63 seconds
Started Aug 16 05:13:00 PM PDT 24
Finished Aug 16 05:13:14 PM PDT 24
Peak memory 202244 kb
Host smart-ca758917-a3f3-4edc-8fe8-5cbea2fb6655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475178745 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.475178745
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3946486146
Short name T516
Test name
Test status
Simulation time 430846455 ps
CPU time 0.87 seconds
Started Aug 16 05:13:16 PM PDT 24
Finished Aug 16 05:13:17 PM PDT 24
Peak memory 201920 kb
Host smart-b19f5d58-c469-4cb2-b28e-044b54a6e038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946486146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3946486146
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.120826881
Short name T341
Test name
Test status
Simulation time 529208450337 ps
CPU time 750.44 seconds
Started Aug 16 05:13:14 PM PDT 24
Finished Aug 16 05:25:45 PM PDT 24
Peak memory 202160 kb
Host smart-8b93a3d7-bac8-4f4f-9b7a-3557c9514c22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120826881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.120826881
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2244279829
Short name T183
Test name
Test status
Simulation time 366676082042 ps
CPU time 831.28 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:27:08 PM PDT 24
Peak memory 202044 kb
Host smart-f1ac58ff-b54a-4f79-9615-5f260f60e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244279829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2244279829
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1204223042
Short name T250
Test name
Test status
Simulation time 163356493401 ps
CPU time 388.08 seconds
Started Aug 16 05:12:58 PM PDT 24
Finished Aug 16 05:19:26 PM PDT 24
Peak memory 202072 kb
Host smart-876e7ffe-1d95-4d72-b28e-94780c714fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204223042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1204223042
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1474530348
Short name T525
Test name
Test status
Simulation time 331254165017 ps
CPU time 793.03 seconds
Started Aug 16 05:13:02 PM PDT 24
Finished Aug 16 05:26:15 PM PDT 24
Peak memory 202188 kb
Host smart-079e0a52-9a85-4d80-89f0-2c7c22f589ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474530348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1474530348
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2858969119
Short name T789
Test name
Test status
Simulation time 161901639728 ps
CPU time 192.31 seconds
Started Aug 16 05:13:06 PM PDT 24
Finished Aug 16 05:16:19 PM PDT 24
Peak memory 202124 kb
Host smart-243ba9d1-5127-4e3f-af83-91d6cc1aeb61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858969119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2858969119
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1799083911
Short name T282
Test name
Test status
Simulation time 172357144090 ps
CPU time 41.44 seconds
Started Aug 16 05:13:17 PM PDT 24
Finished Aug 16 05:13:59 PM PDT 24
Peak memory 202080 kb
Host smart-ed5ee215-41eb-4655-afab-973501e94385
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799083911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1799083911
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.763629578
Short name T673
Test name
Test status
Simulation time 391814594543 ps
CPU time 957.48 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:29:11 PM PDT 24
Peak memory 202112 kb
Host smart-6a1cf414-f336-4475-806e-24e7b5c5694c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763629578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.763629578
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1008915658
Short name T639
Test name
Test status
Simulation time 104504379707 ps
CPU time 344.86 seconds
Started Aug 16 05:13:13 PM PDT 24
Finished Aug 16 05:18:58 PM PDT 24
Peak memory 202320 kb
Host smart-d9fc9725-78ce-420f-a064-8871ed97a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008915658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1008915658
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4234575452
Short name T371
Test name
Test status
Simulation time 26217049010 ps
CPU time 59.22 seconds
Started Aug 16 05:13:07 PM PDT 24
Finished Aug 16 05:14:07 PM PDT 24
Peak memory 201908 kb
Host smart-03b265ee-c4a6-4ecd-ac5c-983d8c897af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234575452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4234575452
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1660726046
Short name T736
Test name
Test status
Simulation time 4364976703 ps
CPU time 11.57 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 201868 kb
Host smart-aedfbf3a-6f09-4645-8d1d-0a8608aa3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660726046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1660726046
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2744882914
Short name T100
Test name
Test status
Simulation time 5743199159 ps
CPU time 13.93 seconds
Started Aug 16 05:12:59 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 201908 kb
Host smart-e67e797b-8842-452f-a56f-c2f7783753e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744882914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2744882914
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2060826045
Short name T162
Test name
Test status
Simulation time 388486672703 ps
CPU time 212.39 seconds
Started Aug 16 05:13:11 PM PDT 24
Finished Aug 16 05:16:44 PM PDT 24
Peak memory 202108 kb
Host smart-82dc21aa-e674-460c-9f29-22014db6ce35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060826045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2060826045
Directory /workspace/9.adc_ctrl_stress_all/latest
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