Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5594	1			T2	32		T60	9		T65	20
testmodes[AdcCtrlTestmodeNormal]	4681	1			T1	3		T2	42		T5	2
testmodes[AdcCtrlTestmodeLowpower]	4886	1			T2	45		T3	2		T4	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2822	1			T2	7		T60	5		T65	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1485	1			T2	14		T60	4		T43	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1170	1			T2	11		T43	2		T40	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1452	1			T2	12		T60	3		T43	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1659	1			T1	2		T2	14		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1235	1			T2	16		T60	1		T62	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1209	1			T2	12		T43	1		T66	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1201	1			T2	14		T7	1		T147	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2228	1			T2	18		T3	1		T4	1