Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19869

1

T1

1

T2

119

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

3557

1

T1

2

T3

38

T7

55

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17466

1

T1

2

T2

119

T3

21

auto[1]

5960

1

T1

1

T3

17

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T221	4		T222	1		T223	4
values[0]	203	1			T224	22		T225	1		T32	21
values[1]	571	1			T7	21		T172	1		T51	1
values[2]	617	1			T1	1		T159	22		T147	15
values[3]	717	1			T151	9		T147	32		T52	17
values[4]	603	1			T11	1		T62	6		T161	17
values[5]	2964	1			T4	17		T5	25		T6	20
values[6]	758	1			T3	17		T7	34		T62	22
values[7]	809	1			T151	4		T147	27		T39	19
values[8]	561	1			T1	2		T11	2		T151	6
values[9]	1388	1			T3	21		T60	17		T154	22
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	913	1			T7	21		T172	1		T147	15
values[1]	675	1			T1	1		T159	22		T51	13
values[2]	683	1			T11	1		T151	9		T147	32
values[3]	3002	1			T4	17		T5	25		T6	20
values[4]	623	1			T7	1		T127	1		T62	22
values[5]	808	1			T3	17		T7	34		T63	10
values[6]	548	1			T151	4		T155	15		T44	9
values[7]	691	1			T1	2		T3	21		T11	2
values[8]	1100	1			T60	17		T154	22		T152	24
values[9]	146	1			T201	5		T211	1		T165	1
minimum	14237	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T172	1		T51	1		T52	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	10		T147	8		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T159	22		T51	13		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T55	1		T56	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T150	1		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	9		T147	14		T52	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T4	17		T5	2		T6	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T52	8		T55	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	1		T127	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T62	14		T150	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T63	6		T147	13		T156	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	17		T7	18		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T155	10		T102	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T151	4		T44	6		T30	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T41	9		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T3	21		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T60	9		T154	13		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T152	16		T43	5		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T201	1		T211	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T226	1		T227	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14144	1			T2	119		T7	18		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	5		T23	12		T158	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	11		T147	7		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T39	1		T228	1		T189	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T55	18		T41	11		T92	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	12		T165	11		T166	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	18		T52	9		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T5	23		T9	12		T64	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	9		T31	3		T114	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T230	4		T231	8		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T62	8		T27	10		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T63	4		T147	14		T234	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	16		T152	2		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	5		T180	19		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	3		T235	2		T176	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	8		T23	1		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T149	4		T45	3		T99	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T60	8		T154	9		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T152	8		T43	1		T41	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T201	4		T189	4		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T226	2		T227	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T43	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T221	1		T222	1		T223	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T32	12		T193	1		T237	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T224	22		T225	1		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T172	1		T51	1		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	10		T31	6		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T159	22		T51	13		T66	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T147	8		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	16		T150	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T151	9		T147	14		T52	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	1		T62	3		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T52	8		T55	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T4	17		T5	2		T6	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T114	5		T162	10		T157	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T63	6		T234	9		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	17		T7	18		T62	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T147	13		T155	10		T156	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T151	4		T39	9		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T41	9		T24	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T11	2		T151	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	438	1			T60	9		T154	13		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T3	21		T152	16		T43	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	3		T223	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T32	9		T239	10		T240	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T238	11		T241	17		T242	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T52	5		T39	1		T23	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	11		T31	3		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T158	6		T189	6		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	7		T161	2		T41	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	12		T228	1		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T147	18		T52	9		T55	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T62	3		T161	16		T92	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	9		T30	13		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T5	23		T9	12		T64	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T114	7		T162	9		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T63	4		T234	4		T180	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	16		T62	8		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T147	14		T155	5		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	10		T45	3		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	8		T233	12		T230	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T149	4		T44	3		T245	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T60	8		T154	9		T55	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T152	8		T43	1		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[9] , minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T172	1		T51	1		T52	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T7	12		T147	8		T161	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T159	1		T51	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T55	19		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T150	1		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	1		T147	19		T52	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T4	2		T5	25		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T52	10		T55	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T127	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T62	9		T150	1		T27	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T63	5		T147	15		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T7	17		T152	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T155	6		T102	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T151	1		T44	6		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T41	9		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T3	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T60	9		T154	10		T55	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T152	9		T43	4		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T201	5		T211	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T226	3		T227	13		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14232	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	2		T23	13		T157	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	9		T147	7		T57	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T159	21		T51	12		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T56	13		T41	17		T92	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	11		T166	12		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T151	8		T147	13		T52	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T4	15		T6	18		T10	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T52	7		T114	4		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T57	9		T156	11		T230	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T62	13		T229	12		T196	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T63	5		T147	12		T156	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	16		T7	17		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T155	9		T180	18		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T151	3		T44	3		T30	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	8		T24	10		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	20		T151	5		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T60	8		T154	12		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T152	15		T43	2		T41	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T189	6		T236	10		T247	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T187	2		T182	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T221	4		T222	1		T223	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T32	10		T193	1		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T224	1		T225	1		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T172	1		T51	1		T52	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	12		T31	4		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T159	1		T51	1		T66	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T147	8		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	1		T150	1		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	1		T147	19		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	1		T62	4		T161	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T52	10		T55	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T4	2		T5	25		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T114	8		T162	10		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T63	5		T234	5		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T7	17		T62	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T147	15		T155	6		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	1		T39	11		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T41	9		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T11	2		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T60	9		T154	10		T55	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T3	1		T152	9		T43	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T223	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T32	11		T237	1		T239	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T224	21		T241	18		T248	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T52	2		T23	13		T187	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	9		T31	5		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T159	21		T51	12		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T147	7		T57	6		T41	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	15		T29	11		T249	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T151	8		T147	13		T52	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T62	2		T156	11		T153	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	7		T24	9		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T4	15		T6	18		T10	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T114	4		T162	9		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T63	5		T234	8		T180	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	16		T7	17		T62	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T147	12		T155	9		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T151	3		T39	8		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T41	8		T24	10		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T151	5		T51	11		T44	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T60	8		T154	12		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T3	20		T152	15		T43	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19658

1

T1

2

T2

119

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

3768

1

T1

1

T3

38

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17114

1

T1

2

T2

116

T7

20

auto[1]

6312

1

T1

1

T2

3

T3

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	405	1			T2	3		T43	10		T66	1
values[0]	33	1			T189	31		T250	1		T251	1
values[1]	613	1			T159	22		T52	17		T57	10
values[2]	3206	1			T4	17		T5	25		T6	20
values[3]	662	1			T11	1		T62	22		T147	59
values[4]	800	1			T1	1		T151	6		T154	22
values[5]	599	1			T1	1		T7	1		T11	1
values[6]	646	1			T7	21		T151	9		T51	13
values[7]	683	1			T1	1		T3	21		T161	17
values[8]	563	1			T11	1		T127	1		T152	38
values[9]	1359	1			T3	17		T7	34		T62	6
minimum	13857	1			T2	116		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	875	1			T159	22		T51	12		T52	17
values[1]	3185	1			T4	17		T5	25		T6	20
values[2]	725	1			T11	1		T151	6		T154	22
values[3]	696	1			T1	1		T147	15		T149	5
values[4]	594	1			T1	1		T7	1		T11	1
values[5]	661	1			T1	1		T7	21		T51	13
values[6]	575	1			T3	21		T11	1		T127	1
values[7]	697	1			T152	14		T161	17		T51	1
values[8]	929	1			T3	17		T7	34		T63	10
values[9]	263	1			T62	6		T172	1		T52	8
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T150	1		T163	1		T153	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T159	22		T51	12		T52	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T4	17		T5	2		T6	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T60	9		T62	14		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T151	6		T147	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T154	13		T43	5		T30	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T147	8		T149	1		T155	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T246	5		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T7	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T161	1		T150	1		T201	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T7	10		T51	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T53	2		T55	1		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	1		T57	7		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	21		T127	1		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T51	1		T31	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	12		T161	1		T156	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T63	6		T152	16		T52	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	17		T7	18		T151	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T52	3		T99	4		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T62	3		T172	1		T156	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	14		T254	2		T247	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T52	9		T111	9		T23	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T5	23		T9	12		T64	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T60	8		T62	8		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	32		T255	12		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	9		T43	1		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	7		T149	4		T155	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T189	4		T257	16		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T233	12		T258	12		T259	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T161	2		T201	4		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	11		T44	3		T173	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T55	18		T39	10		T201	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	13		T165	11		T109	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T23	1		T158	4		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T31	3		T245	4		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T152	2		T161	16		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T63	4		T152	8		T52	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	16		T41	8		T92	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T52	5		T99	1		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T62	3		T29	12		T233	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T2	3		T43	10		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T168	3		T226	1		T260	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	15		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T150	1		T163	1		T168	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T159	22		T52	8		T57	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T4	17		T5	2		T6	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T60	9		T51	12		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T147	27		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T62	14		T43	5		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	6		T149	1		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	1		T154	13		T234	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T7	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T161	1		T55	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	10		T151	9		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	2		T39	9		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T57	7		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	21		T161	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T152	16		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T127	1		T152	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T63	6		T51	1		T52	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	491	1			T3	17		T7	18		T62	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13768	1			T2	116		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T253	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T168	2		T226	8		T260	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T168	20		T198	17		T195	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T52	9		T111	9		T92	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T5	23		T9	12		T64	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	8		T55	13		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T147	32		T261	13		T262	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T62	8		T43	1		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T149	4		T230	2		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T154	9		T234	6		T245	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	7		T155	5		T234	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	2		T55	18		T201	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	11		T44	3		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	10		T201	4		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	13		T165	11		T109	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T161	16		T23	1		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T152	8		T31	3		T41	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T152	2		T12	1		T179	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T63	4		T52	14		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T7	16		T62	3		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1