Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19840

1

T1

2

T2

119

T3

21

auto[ADC_CTRL_FILTER_COND_OUT]

3586

1

T1

1

T3

17

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17277

1

T1

2

T2

119

T7

20

auto[1]

6149

1

T1

1

T3

38

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	209	1			T201	5		T12	5		T109	9
values[0]	71	1			T31	9		T224	22		T238	12
values[1]	686	1			T7	21		T172	1		T161	3
values[2]	633	1			T1	1		T159	22		T147	15
values[3]	732	1			T11	1		T151	9		T147	32
values[4]	617	1			T62	6		T161	17		T52	17
values[5]	2975	1			T4	17		T5	25		T6	20
values[6]	742	1			T3	17		T7	34		T62	22
values[7]	747	1			T151	4		T147	27		T39	19
values[8]	563	1			T1	2		T11	2		T151	6
values[9]	1225	1			T3	21		T60	17		T154	22
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T7	21		T147	15		T51	1
values[1]	634	1			T1	1		T159	22		T161	3
values[2]	685	1			T11	1		T151	9		T147	32
values[3]	2972	1			T4	17		T5	25		T6	20
values[4]	628	1			T127	1		T62	22		T53	1
values[5]	840	1			T3	17		T7	34		T63	10
values[6]	529	1			T151	4		T155	15		T156	10
values[7]	711	1			T1	2		T3	21		T11	2
values[8]	1146	1			T60	17		T154	22		T152	24
values[9]	91	1			T201	5		T165	1		T189	11
minimum	14420	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	10		T51	1		T52	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	8		T66	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T159	22		T51	13		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T161	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	1		T150	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T151	9		T147	14		T52	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T4	17		T5	2		T6	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T62	3		T52	8		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T127	1		T53	1		T57	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T62	14		T27	1		T157	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T63	6		T234	13		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	17		T7	18		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T155	10		T102	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T151	4		T156	10		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	2		T3	21		T41	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	2		T151	6		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T60	9		T152	16		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T154	13		T43	5		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T201	1		T165	1		T189	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T247	7		T226	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14210	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T149	1		T243	3		T193	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	11		T52	5		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	7		T109	2		T192	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T244	10		T324	1		T256	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T161	2		T55	18		T41	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T165	11		T229	14		T166	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T147	18		T52	9		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T5	23		T9	12		T64	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T62	3		T52	9		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T234	4		T230	4		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T62	8		T27	10		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T63	4		T234	14		T180	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	16		T147	14		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T155	5		T180	15		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T44	3		T235	2		T176	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T41	8		T99	1		T23	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T149	4		T45	3		T245	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T60	8		T152	8		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T154	9		T43	1		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T201	4		T189	4		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T247	6		T226	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T43	2		T31	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T243	2		T257	13		T240	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T201	1		T12	4		T189	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T109	4		T283	16		T198	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T31	6		T311	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T224	22		T238	1		T240	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	10		T172	1		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T161	1		T66	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T159	22		T51	13		T157	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T147	8		T57	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T35	16		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T151	9		T147	14		T52	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T161	1		T92	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T62	3		T52	8		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T4	17		T5	2		T6	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T27	1		T157	6		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T63	6		T234	9		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	17		T7	18		T62	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	10		T102	1		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T151	4		T147	13		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	2		T41	9		T24	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	2		T151	6		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T3	21		T60	9		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T154	13		T43	5		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T201	4		T12	1		T189	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T109	5		T283	4		T198	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T31	3		T311	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T238	11		T240	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	11		T52	5		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T161	2		T243	2		T253	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	6		T189	6		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T147	7		T41	11		T92	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T165	11		T166	10		T255	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T147	18		T52	9		T55	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T161	16		T92	4		T153	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	3		T52	9		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T5	23		T9	12		T64	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T27	10		T233	12		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T63	4		T234	4		T180	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	16		T62	8		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T155	5		T234	14		T180	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T147	14		T39	10		T247	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	8		T231	8		T261	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	4		T44	3		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T60	8		T152	8		T55	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T154	9		T43	1		T149	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	12		T51	1		T52	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T147	8		T66	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T159	1		T51	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T161	3		T55	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T150	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	1		T147	19		T52	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T4	2		T5	25		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T62	4		T52	10		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T127	1		T53	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T62	9		T27	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T63	5		T234	15		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T7	17		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T155	6		T102	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T151	1		T156	1		T44	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T3	1		T41	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	2		T151	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T60	9		T152	9		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T154	10		T43	4		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T201	5		T165	1		T189	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T247	7		T226	3		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14299	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T149	1		T243	3		T193	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	9		T52	2		T157	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T147	7		T224	21		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T159	21		T51	12		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T56	13		T57	6		T41	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T229	11		T166	12		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T151	8		T147	13		T52	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T4	15		T6	18		T10	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T62	2		T52	7		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T57	9		T156	11		T234	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T62	13		T157	5		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T63	5		T234	12		T180	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	16		T7	17		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T155	9		T180	14		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T151	3		T156	9		T44	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	20		T41	8		T99	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	5		T51	11		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T60	8		T152	15		T41	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T154	12		T43	2		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T189	6		T236	10		T287	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T247	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T31	5		T23	13		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T243	2		T257	10		T240	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T201	5		T12	3		T189	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T109	6		T283	5		T198	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T31	4		T311	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T224	1		T238	12		T240	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	12		T172	1		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	3		T66	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T159	1		T51	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T147	8		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T35	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T151	1		T147	19		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T161	17		T92	5		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T62	4		T52	10		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T4	2		T5	25		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	11		T157	1		T233	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T63	5		T234	5		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T7	17		T62	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T155	6		T102	1		T234	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T151	1		T147	15		T39	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	2		T41	9		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	2		T151	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T3	1		T60	9		T152	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T154	10		T43	4		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T12	2		T189	6		T287	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T109	3		T283	15		T198	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T31	5		T311	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T224	21		T240	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	9		T52	2		T23	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T157	12		T243	2		T236	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T159	21		T51	12		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T147	7		T57	6		T41	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	15		T166	12		T249	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T151	8		T147	13		T52	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T153	16		T24	9		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	2		T52	7		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T4	15		T6	18		T10	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T157	5		T196	18		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T63	5		T234	8		T180	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	16		T7	17		T62	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T155	9		T234	12		T180	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	3		T147	12		T39	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T41	8		T24	10		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T151	5		T51	11		T44	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T3	20		T60	8		T152	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T154	12		T43	2		T234	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18