Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20008

1

T1

1

T2

119

T3

21

auto[ADC_CTRL_FILTER_COND_OUT]

3418

1

T1

2

T3

17

T7

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17327

1

T1

1

T2

119

T3

21

auto[1]

6099

1

T1

2

T3

17

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T157	6		T187	3		T180	30
values[0]	50	1			T189	11		T167	1		T271	24
values[1]	771	1			T1	1		T127	1		T53	1
values[2]	656	1			T147	15		T52	17		T55	19
values[3]	714	1			T3	21		T7	21		T62	6
values[4]	750	1			T147	27		T35	16		T162	19
values[5]	712	1			T7	35		T60	17		T62	22
values[6]	790	1			T1	1		T172	1		T151	4
values[7]	574	1			T1	1		T11	1		T154	22
values[8]	600	1			T11	1		T63	10		T51	12
values[9]	3298	1			T3	17		T4	17		T5	25
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	677	1			T1	1		T127	1		T147	15
values[1]	648	1			T52	17		T55	19		T34	1
values[2]	721	1			T3	21		T7	21		T62	6
values[3]	846	1			T35	16		T150	1		T44	11
values[4]	685	1			T7	35		T60	17		T62	22
values[5]	818	1			T1	1		T151	4		T154	22
values[6]	2924	1			T1	1		T4	17		T5	25
values[7]	485	1			T11	1		T63	10		T152	14
values[8]	975	1			T3	17		T11	1		T152	24
values[9]	133	1			T151	9		T57	10		T157	6
minimum	14514	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T127	1		T56	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T147	8		T102	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	9		T41	9		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T52	8		T55	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	21		T7	10		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T151	6		T161	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T44	8		T201	8		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	16		T150	1		T70	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	9		T172	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	19		T62	14		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T151	4		T154	13		T51	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T159	22		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T4	17		T5	2		T6	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T11	1		T147	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T51	12		T55	1		T149	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T63	6		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	1		T52	3		T41	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	17		T152	16		T52	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T57	10		T266	14		T267	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T151	9		T157	6		T187	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14230	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T189	7		T192	10		T167	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T234	14		T230	4		T257	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T147	7		T243	2		T32	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	10		T41	8		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	9		T55	18		T27	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	11		T62	3		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T161	16		T149	4		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T44	3		T201	4		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T233	12		T254	10		T247	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T60	8		T161	2		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	16		T62	8		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	9		T55	13		T41	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T155	5		T153	14		T173	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T5	23		T9	12		T64	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T147	18		T29	12		T158	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T149	9		T45	3		T261	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T63	4		T152	2		T245	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T52	5		T41	11		T114	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T152	8		T52	9		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T267	11		T327	2		T270	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T189	4		T192	7		T197	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T180	15		T229	12		T274	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T157	6		T187	3		T328	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T271	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	7		T167	1		T272	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	1		T127	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T234	9		T165	1		T243	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	9		T41	9		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	8		T52	8		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	21		T7	10		T62	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T151	6		T161	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T147	13		T162	10		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	16		T150	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	9		T161	1		T150	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	19		T62	14		T159	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T172	1		T151	4		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T40	2		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	13		T51	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T11	1		T147	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	12		T149	2		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T63	6		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T4	17		T5	2		T6	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	17		T151	9		T152	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T180	15		T229	14		T178	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T239	1		T329	15		T330	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T271	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T189	4		T272	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T23	1		T234	14		T230	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T234	4		T243	2		T32	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	10		T41	8		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T147	7		T52	9		T55	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	11		T62	3		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T161	16		T149	4		T92	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T147	14		T162	9		T201	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T228	1		T254	10		T247	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T60	8		T161	2		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	16		T62	8		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T55	13		T41	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	5		T92	8		T99	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T154	9		T23	12		T173	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T147	18		T158	6		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T149	9		T45	3		T109	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T63	4		T29	12		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T5	23		T9	12		T64	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	10		T52	9		T31	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T127	1		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T147	8		T102	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T39	11		T41	9		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	10		T55	19		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T7	12		T62	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T151	1		T161	17		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T44	8		T201	5		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	1		T150	1		T70	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	9		T172	1		T161	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	18		T62	9		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T151	1		T154	10		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T159	1		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T4	2		T5	25		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T11	1		T147	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T51	1		T55	1		T149	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T63	5		T152	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	1		T52	6		T41	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T152	9		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T57	1		T266	1		T267	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T151	1		T157	1		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14312	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T189	5		T192	8		T167	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T56	13		T57	6		T24	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T147	7		T243	2		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	8		T41	8		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T52	7		T30	13		T234	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	20		T7	9		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T151	5		T156	9		T189	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T44	3		T201	7		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	15		T196	9		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T60	8		T111	8		T23	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	17		T62	13		T92	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T151	3		T154	12		T51	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T159	21		T155	9		T153	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T4	15		T6	18		T10	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T147	13		T29	11		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T51	11		T45	3		T276	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T63	5		T152	11		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T52	2		T41	17		T114	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	16		T152	15		T52	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T57	9		T266	13		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T151	8		T157	5		T187	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T157	23		T229	10		T215	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T189	6		T192	9		T197	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T180	16		T229	15		T274	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T157	1		T187	1		T328	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T189	5		T167	1		T272	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	1		T127	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T234	5		T165	1		T243	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	11		T41	9		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	8		T52	10		T55	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T7	12		T62	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	1		T161	17		T149	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T147	15		T162	10		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	1		T150	1		T228	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T60	9		T161	3		T150	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	18		T62	9		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T172	1		T151	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T40	2		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T154	10		T51	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T11	1		T147	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T51	1		T149	11		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	1		T63	5		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T4	2		T5	25		T6	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T151	1		T152	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T180	14		T229	11		T274	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T157	5		T187	2		T329	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T189	6		T272	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T56	13		T57	6		T24	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T234	8		T243	2		T32	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	8		T41	8		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T147	7		T52	7		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	20		T7	9		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	5		T156	9		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T147	12		T162	9		T201	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	15		T196	9		T275	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T60	8		T44	3		T30	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	17		T62	13		T159	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T151	3		T51	12		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T155	9		T92	17		T99	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T154	12		T23	13		T196	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	13		T253	16		T296	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T51	11		T45	3		T109	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T63	5		T29	11		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T4	15		T6	18		T10	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	16		T151	8		T152	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18