Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19709

1

T1

2

T2

119

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3717

1

T1

1

T7

35

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17287

1

T1

2

T2

119

T3

17

auto[1]

6139

1

T1

1

T3

21

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	273	1			T60	17		T52	17		T156	10
values[0]	123	1			T179	20		T296	7		T275	8
values[1]	869	1			T1	1		T151	10		T152	24
values[2]	760	1			T7	1		T147	15		T57	17
values[3]	521	1			T152	14		T161	3		T51	1
values[4]	705	1			T11	1		T39	19		T41	29
values[5]	3085	1			T4	17		T5	25		T6	20
values[6]	581	1			T1	1		T11	1		T63	10
values[7]	790	1			T1	1		T3	38		T7	34
values[8]	658	1			T7	21		T172	1		T159	22
values[9]	835	1			T62	6		T151	9		T51	13
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	613	1			T1	1		T151	4		T52	25
values[1]	943	1			T7	1		T147	15		T152	14
values[2]	573	1			T161	3		T51	1		T55	14
values[3]	3001	1			T4	17		T5	25		T6	20
values[4]	600	1			T1	1		T62	22		T56	14
values[5]	671	1			T11	1		T63	10		T154	22
values[6]	771	1			T3	38		T7	55		T11	1
values[7]	643	1			T1	1		T62	6		T172	1
values[8]	762	1			T151	9		T53	1		T31	9
values[9]	181	1			T60	17		T52	17		T44	9
minimum	14668	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T150	1		T224	22		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	1		T151	4		T52	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	12		T57	7		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T7	1		T147	8		T57	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T161	1		T51	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	2		T41	18		T243	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T4	17		T5	2		T6	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T150	1		T252	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T56	14		T156	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T62	14		T111	9		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T63	6		T154	13		T51	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T147	13		T43	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	38		T7	10		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	18		T27	1		T246	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T62	3		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T172	1		T159	22		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	1		T31	6		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	9		T156	10		T234	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T165	1		T176	14		T300	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T60	9		T52	8		T44	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14300	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T102	1		T179	8		T275	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T179	11		T164	6		T239	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T52	14		T55	18		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	2		T149	9		T201	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T147	7		T114	7		T192	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T161	2		T55	13		T234	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T41	11		T243	2		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T5	23		T9	12		T64	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T229	13		T168	2		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T153	14		T23	1		T254	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T62	8		T111	9		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T63	4		T154	9		T41	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T147	14		T43	1		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	11		T147	18		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	16		T27	10		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T62	3		T92	4		T201	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T92	8		T29	12		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T31	3		T39	1		T245	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T234	6		T173	12		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T165	11		T176	4		T323	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T60	8		T52	9		T44	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T152	8		T161	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T262	12		T238	10		T298	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T245	1		T165	1		T230	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T60	9		T52	8		T156	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T179	1		T275	8		T183	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	8		T296	7		T238	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	6		T152	16		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	1		T151	4		T52	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	7		T35	16		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T7	1		T147	8		T57	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T152	12		T161	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	2		T24	11		T230	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T39	9		T234	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T41	18		T150	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T4	17		T5	2		T6	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T62	14		T111	9		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T63	6		T51	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T147	13		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	1		T3	38		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	18		T43	5		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	10		T53	1		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	1		T159	22		T92	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T62	3		T53	1		T31	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T151	9		T51	13		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T245	4		T165	11		T230	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T60	8		T52	9		T44	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T179	11		T183	4		T297	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T238	10		T299	18		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	8		T161	16		T70	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T52	14		T55	18		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T149	9		T201	4		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T147	7		T114	7		T192	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T152	2		T161	2		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T230	4		T273	4		T176	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	10		T234	4		T235	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	11		T243	2		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T5	23		T9	12		T64	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	8		T111	9		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T63	4		T41	8		T23	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T147	14		T155	5		T23	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T154	9		T147	18		T99	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	16		T43	1		T27	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	11		T41	8		T201	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T92	8		T29	12		T189	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T62	3		T31	3		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T234	6		T173	12		T109	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T150	1		T224	1		T179	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	1		T151	1		T52	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	3		T57	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	1		T147	8		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T161	3		T51	1		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	2		T41	12		T243	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T4	2		T5	25		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T150	1		T252	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T56	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T62	9		T111	10		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T63	5		T154	10		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	1		T147	15		T43	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	2		T7	12		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	17		T27	11		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T62	4		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T172	1		T159	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T53	1		T31	4		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T151	1		T156	1		T234	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T165	12		T176	5		T300	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T60	9		T52	10		T44	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14350	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T102	1		T179	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T224	21		T164	2		T274	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	3		T52	9		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	11		T57	6		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T147	7		T57	9		T114	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T234	20		T246	15		T180	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	17		T243	2		T230	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T4	15		T6	18		T10	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T229	10		T168	2		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T56	13		T156	11		T153	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T62	13		T111	8		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T63	5		T154	12		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T147	12		T43	2		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	36		T7	9		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	17		T246	4		T189	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T62	2		T12	2		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T159	21		T51	12		T92	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	5		T230	4		T331	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T151	8		T156	9		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T176	13		T300	12		T332	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T60	8		T52	7		T44	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T151	5		T152	15		T70	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T179	7		T275	9		T262	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T245	5		T165	12		T230	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T60	9		T52	10		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T179	12		T275	1		T183	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T179	1		T296	1		T238	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T151	1		T152	9		T161	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	1		T151	1		T52	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T57	1		T35	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	1		T147	8		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T152	3		T161	3		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	2		T24	1		T230	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T39	11		T234	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	12		T150	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T4	2		T5	25		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T62	9		T111	10		T244	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T63	5		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T147	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T3	2		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	17		T43	4		T27	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	12		T53	1		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	1		T159	1		T92	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	4		T53	1		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T151	1		T51	1		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T230	4		T287	3		T300	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T60	8		T52	7		T156	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T275	7		T183	13		T297	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T179	7		T296	6		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T151	5		T152	15		T224	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T151	3		T52	9		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T57	6		T35	15		T201	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T147	7		T57	9		T114	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T152	11		T234	12		T246	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	10		T230	5		T291	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	8		T234	8		T180	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	17		T243	2		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T4	15		T6	18		T10	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T62	13		T111	8		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T63	5		T51	11		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T147	12		T155	9		T23	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	36		T154	12		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	17		T43	2		T246	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	9		T41	8		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T159	21		T92	17		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T62	2		T31	5		T309	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T151	8		T51	12		T24	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18