Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20109

1

T1

3

T2

119

T3

21

auto[ADC_CTRL_FILTER_COND_OUT]

3317

1

T3

17

T7

56

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17095

1

T1

1

T2

119

T7

19

auto[1]

6331

1

T1

2

T3

38

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	157	1			T172	1		T43	6		T51	12
values[0]	43	1			T23	2		T187	3		T189	11
values[1]	663	1			T3	21		T152	14		T55	19
values[2]	718	1			T1	1		T52	25		T55	1
values[3]	837	1			T7	34		T60	17		T151	9
values[4]	2948	1			T4	17		T5	25		T6	20
values[5]	973	1			T3	17		T7	21		T41	34
values[6]	611	1			T63	10		T53	1		T31	4
values[7]	625	1			T62	28		T151	6		T39	19
values[8]	712	1			T1	2		T11	2		T147	27
values[9]	913	1			T7	1		T11	1		T127	1
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T1	1		T3	21		T55	19
values[1]	671	1			T60	17		T154	22		T52	25
values[2]	678	1			T7	34		T151	9		T147	47
values[3]	3247	1			T3	17		T4	17		T5	25
values[4]	698	1			T53	1		T40	2		T41	34
values[5]	622	1			T62	6		T63	10		T31	4
values[6]	716	1			T1	1		T11	1		T62	22
values[7]	640	1			T1	1		T11	1		T57	10
values[8]	820	1			T7	1		T11	1		T127	1
values[9]	113	1			T172	1		T245	10		T173	1
minimum	14498	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T3	21		T156	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	1		T30	5		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T60	9		T154	13		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T52	8		T55	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	22		T161	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	18		T151	9		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1707	1			T4	17		T5	2		T6	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	17		T7	10		T159	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T53	1		T41	9		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	2		T41	9		T162	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T62	3		T63	6		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T66	1		T149	1		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T62	14		T151	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	1		T147	13		T39	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T150	1		T92	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T57	10		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T11	1		T151	4		T152	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T127	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T173	1		T13	3		T314	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T172	1		T245	1		T192	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14228	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T23	1		T187	3		T275	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	12		T30	13		T180	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T55	18		T179	11		T173	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T60	8		T154	9		T52	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T52	9		T155	5		T253	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	25		T161	2		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	16		T111	9		T333	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T5	23		T9	12		T64	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	11		T149	9		T23	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T41	8		T99	1		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	8		T162	9		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T62	3		T63	4		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T149	4		T228	1		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	8		T41	11		T189	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	14		T39	10		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T92	8		T27	10		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T244	10		T273	2		T318	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T152	8		T43	1		T234	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	16		T52	9		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T13	1		T314	2		T334	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T245	9		T192	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T152	2		T43	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T23	1		T195	14		T316	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	5		T51	12		T173	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T172	1		T150	1		T192	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T189	7		T312	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T23	1		T187	3		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	21		T152	12		T29	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T55	1		T30	5		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T52	3		T156	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	8		T55	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T60	9		T154	13		T147	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	18		T151	9		T51	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T4	17		T5	2		T6	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T159	22		T149	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T41	9		T114	5		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T3	17		T7	10		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T63	6		T53	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	2		T66	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T62	17		T151	6		T41	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	9		T44	2		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T92	18		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	2		T147	13		T57	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T11	1		T151	4		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T127	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T43	1		T335	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T192	7		T324	1		T287	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T189	4		T312	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T23	1		T254	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T152	2		T29	12		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T55	18		T179	11		T173	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	5		T30	13		T173	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T52	9		T253	1		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T60	8		T154	9		T147	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	16		T111	9		T155	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T5	23		T9	12		T64	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T149	9		T23	12		T235	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T41	8		T114	7		T99	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	11		T41	8		T162	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T63	4		T31	3		T92	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T149	4		T233	12		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	11		T41	11		T258	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	10		T228	1		T158	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T92	8		T164	6		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T147	14		T45	3		T234	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T152	8		T27	10		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T161	16		T52	9		T31	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T3	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	19		T30	1		T179	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T60	9		T154	10		T52	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T52	10		T55	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T147	27		T161	3		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	17		T151	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T4	2		T5	25		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T7	12		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T53	1		T41	9		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	2		T41	9		T162	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T62	4		T63	5		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T66	1		T149	5		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T62	9		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T147	15		T39	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T150	1		T92	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	1		T57	1		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	1		T151	1		T152	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T127	1		T161	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T173	1		T13	4		T314	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T172	1		T245	10		T192	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14326	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T23	2		T187	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	20		T156	9		T29	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T30	4		T246	4		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T60	8		T154	12		T52	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	7		T155	9		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T147	20		T56	13		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	17		T151	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T4	15		T6	18		T10	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	16		T7	9		T159	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	8		T99	3		T189	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	8		T162	9		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T62	2		T63	5		T23	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T157	11		T246	15		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T62	13		T151	5		T41	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T147	12		T39	8		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T92	17		T246	8		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T57	9		T244	12		T291	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T151	3		T152	15		T43	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	7		T57	6		T31	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T314	4		T334	20		T286	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T192	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T152	11		T189	6		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T187	2		T275	7		T336	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T43	4		T51	1		T173	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T172	1		T150	1		T192	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T189	5		T312	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T23	2		T187	1		T254	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T152	3		T29	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	19		T30	1		T179	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T52	6		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	10		T55	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T60	9		T154	10		T147	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	17		T151	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T4	2		T5	25		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T159	1		T149	10		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T41	9		T114	8		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	1		T7	12		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T63	5		T53	1		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	2		T66	1		T149	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	13		T151	1		T41	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	11		T44	2		T228	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	2		T92	9		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	2		T147	15		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	1		T151	1		T152	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	1		T127	1		T161	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T43	2		T51	11		T320	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T192	9		T287	3		T337	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T189	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T187	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	20		T152	11		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	4		T246	4		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	2		T156	9		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T52	7		T24	10		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T60	8		T154	12		T147	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	17		T151	8		T51	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T4	15		T6	18		T10	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T159	21		T23	13		T24	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	8		T114	4		T99	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	16		T7	9		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T63	5		T23	2		T230	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	11		T246	15		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T62	15		T151	5		T41	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	8		T257	13		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T92	17		T246	8		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T147	12		T57	9		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T151	3		T152	15		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T52	7		T57	6		T31	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18