Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20144

1

T1

1

T2

119

T3

21

auto[ADC_CTRL_FILTER_COND_OUT]

3282

1

T1

2

T3

17

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17409

1

T1

1

T2

119

T3

17

auto[1]

6017

1

T1

2

T3

21

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	365	1			T159	22		T27	11		T30	27
values[0]	73	1			T23	6		T282	15		T308	17
values[1]	751	1			T151	6		T51	1		T52	17
values[2]	3044	1			T3	17		T4	17		T5	25
values[3]	533	1			T1	1		T161	17		T55	1
values[4]	591	1			T1	1		T7	21		T11	1
values[5]	872	1			T3	21		T7	34		T151	4
values[6]	597	1			T1	1		T11	1		T63	10
values[7]	670	1			T11	1		T172	1		T52	25
values[8]	722	1			T62	22		T147	42		T152	24
values[9]	982	1			T7	1		T127	1		T161	3
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	696	1			T3	17		T151	6		T51	14
values[1]	3117	1			T4	17		T5	25		T6	20
values[2]	561	1			T1	1		T11	1		T161	17
values[3]	760	1			T1	1		T3	21		T7	55
values[4]	628	1			T151	4		T43	6		T40	2
values[5]	623	1			T1	1		T11	1		T172	1
values[6]	704	1			T11	1		T62	22		T52	17
values[7]	753	1			T7	1		T147	42		T152	24
values[8]	1028	1			T127	1		T159	22		T57	10
values[9]	161	1			T161	3		T27	11		T245	5
minimum	14395	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	6		T51	14		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	17		T52	8		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T4	17		T5	2		T6	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	1		T35	16		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T57	7		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	1		T161	1		T41	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	21		T7	10		T151	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T7	18		T111	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T151	4		T150	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	5		T40	2		T92	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T147	14		T53	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T11	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T52	8		T56	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T62	14		T149	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	1		T147	13		T152	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T147	8		T245	1		T246	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T127	1		T159	22		T57	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T29	12		T225	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T316	1		T19	1		T338	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T161	1		T27	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14163	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T165	1		T176	16		T308	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T114	7		T109	5		T254	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T52	9		T39	10		T23	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T5	23		T9	12		T64	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T149	9		T201	4		T164	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T41	11		T92	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T161	16		T41	8		T162	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	11		T154	9		T55	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	16		T111	9		T234	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T229	12		T192	7		T273	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T43	1		T92	8		T109	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	18		T55	13		T234	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T63	4		T52	5		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T52	9		T244	10		T180	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T62	8		T149	4		T153	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T147	14		T152	8		T31	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T147	7		T245	9		T254	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T30	13		T189	6		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T29	12		T180	12		T247	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T316	5		T339	10		T312	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T161	2		T27	10		T245	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T176	2		T308	8		T241	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T159	22		T30	14		T229	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T27	1		T245	1		T247	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T23	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T282	1		T308	9		T340	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	6		T51	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T52	8		T35	16		T39	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T4	17		T5	2		T6	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	17		T149	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T57	7		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T161	1		T55	1		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	10		T151	9		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T11	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	21		T151	4		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	18		T40	2		T92	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T147	14		T55	1		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T11	1		T63	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T52	8		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T172	1		T52	3		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T147	13		T152	16		T56	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T62	14		T147	8		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	1		T127	1		T57	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T161	1		T29	12		T157	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T30	13		T229	13		T166	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T27	10		T245	4		T247	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T23	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T282	14		T308	8		T270	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T114	7		T173	9		T109	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T52	9		T39	10		T23	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T5	23		T9	12		T64	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	9		T201	4		T164	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	1		T41	11		T45	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T161	16		T41	8		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	11		T55	18		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T234	14		T229	14		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T154	9		T155	5		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	16		T92	8		T109	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T147	18		T55	13		T32	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T63	4		T43	1		T234	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	9		T234	4		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T52	5		T149	4		T165	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T147	14		T152	8		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T62	8		T147	7		T153	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T173	12		T189	6		T257	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T161	2		T29	12		T180	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	1		T51	2		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T52	10		T39	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T4	2		T5	25		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	1		T35	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T57	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T161	17		T41	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T7	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T7	17		T111	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T151	1		T150	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	4		T40	2		T92	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	19		T53	1		T55	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T11	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T52	10		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T62	9		T149	5		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T147	15		T152	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T147	8		T245	10		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T127	1		T159	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T29	13		T225	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T316	6		T19	1		T338	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T161	3		T27	11		T245	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14263	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T165	1		T176	3		T308	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	5		T51	12		T114	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	16		T52	7		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	15		T6	18		T10	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	15		T164	2		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T57	6		T41	17		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T41	8		T162	9		T23	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	20		T7	9		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	17		T111	8		T234	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T151	3		T179	7		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T43	2		T92	17		T30	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T147	13		T234	8		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T63	5		T51	11		T52	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T52	7		T56	13		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T62	13		T153	16		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T147	12		T152	15		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T147	7		T246	15		T175	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T159	21		T57	9		T24	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	11		T180	12		T275	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T339	10		T341	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T157	5		T166	12		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T23	2		T182	3		T183	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T176	15		T308	8		T241	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T159	1		T30	14		T229	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T27	11		T245	5		T247	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T23	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T282	15		T308	9		T340	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	1		T51	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	10		T35	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T4	2		T5	25		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	1		T149	10		T201	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T57	1		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T161	17		T55	1		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	12		T151	1		T55	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T11	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T151	1		T154	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	17		T40	2		T92	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T147	19		T55	14		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T11	1		T63	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T52	10		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T172	1		T52	6		T149	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T147	15		T152	9		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T62	9		T147	8		T153	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	1		T127	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T161	3		T29	13		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T159	21		T30	13		T229	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T247	11		T262	10		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T23	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T308	8		T270	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	5		T114	4		T109	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T52	7		T35	15		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T4	15		T6	18		T10	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	16		T164	2		T230	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T57	6		T41	17		T45	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T41	8		T111	8		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	9		T151	8		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T234	12		T229	11		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	20		T151	3		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	17		T92	17		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T147	13		T32	11		T247	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T63	5		T43	2		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	7		T156	9		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T52	2		T156	11		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T147	12		T152	15		T56	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	13		T147	7		T153	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T57	9		T24	9		T246	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T29	11		T157	5		T180	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18