Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T150	1		T163	1		T153	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T159	1		T51	1		T52	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T4	2		T5	25		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T60	9		T62	9		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T151	1		T147	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T154	10		T43	4		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T147	8		T149	5		T155	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T246	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T7	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T161	3		T150	1		T201	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	1		T7	12		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	2		T55	19		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T57	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T3	1		T127	1		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T51	1		T31	4		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T152	3		T161	17		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T63	5		T152	9		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T7	17		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T52	6		T99	2		T253	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T62	4		T172	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T153	16		T247	11		T168	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T159	21		T51	11		T52	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T4	15		T6	18		T10	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T60	8		T62	13		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T151	5		T147	25		T215	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T154	12		T43	2		T30	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	7		T155	9		T234	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T246	4		T189	6		T257	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T151	8		T187	2		T196	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T201	7		T189	6		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	9		T51	12		T35	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	8		T234	8		T70	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T57	6		T30	13		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	20		T166	14		T236	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T243	12		T196	9		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T152	11		T156	9		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T63	5		T152	15		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	16		T7	17		T151	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T52	2		T99	3		T240	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T62	2		T156	11		T29	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T2	3		T43	10		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T168	3		T226	9		T260	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T189	17		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	1		T163	1		T168	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T159	1		T52	10		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T4	2		T5	25		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T60	9		T51	1		T55	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T147	34		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T62	9		T43	4		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T151	1		T149	5		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T154	10		T234	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T7	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T161	3		T55	19		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	12		T151	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	2		T39	11		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T57	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T161	17		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	1		T152	9		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T127	1		T152	3		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T63	5		T51	1		T52	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T3	1		T7	17		T62	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13857	1			T2	116		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T168	2		T260	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T189	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T168	14		T237	1		T263	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T159	21		T52	7		T57	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T4	15		T6	18		T10	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T60	8		T51	11		T162	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	25		T262	10		T215	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	13		T43	2		T30	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T151	5		T230	4		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T154	12		T234	16		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T147	7		T155	9		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T201	7		T246	4		T189	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	9		T151	8		T51	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T39	8		T234	8		T70	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	6		T30	13		T157	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	20		T156	9		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T152	15		T41	8		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	11		T12	2		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T63	5		T52	9		T56	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T3	16		T7	17		T62	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18