Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20035

1

T1

1

T2

119

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3391

1

T1

2

T7

35

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17451

1

T1

1

T2

119

T3

38

auto[1]

5975

1

T1

2

T4

17

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T251	2		T264	10		-	-
values[0]	52	1			T163	1		T189	11		T167	1
values[1]	815	1			T1	1		T127	1		T147	15
values[2]	608	1			T62	6		T52	17		T55	19
values[3]	708	1			T7	21		T151	6		T161	17
values[4]	692	1			T3	21		T147	27		T35	16
values[5]	781	1			T7	35		T60	17		T62	22
values[6]	787	1			T1	1		T172	1		T151	4
values[7]	580	1			T1	1		T11	1		T154	22
values[8]	585	1			T11	1		T63	10		T51	12
values[9]	3580	1			T3	17		T4	17		T5	25
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	945	1			T127	1		T147	15		T53	1
values[1]	694	1			T1	1		T52	17		T55	19
values[2]	740	1			T3	21		T7	21		T62	6
values[3]	795	1			T35	16		T44	11		T201	12
values[4]	709	1			T7	35		T60	17		T62	22
values[5]	800	1			T1	1		T11	1		T154	22
values[6]	2913	1			T1	1		T4	17		T5	25
values[7]	502	1			T11	1		T63	10		T152	14
values[8]	932	1			T3	17		T11	1		T152	24
values[9]	169	1			T151	9		T57	10		T157	6
minimum	14227	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T127	1		T53	1		T56	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T147	8		T102	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T265	1		T164	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T52	8		T55	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	21		T7	10		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T151	6		T161	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T44	8		T201	8		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	16		T70	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T60	9		T172	1		T151	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	19		T62	14		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T154	13		T51	13		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T11	1		T159	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T4	17		T5	2		T6	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T147	14		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T55	1		T149	2		T45	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T63	6		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	17		T11	1		T52	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T152	16		T52	8		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T57	10		T266	14		T267	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T151	9		T157	6		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T23	1		T234	14		T229	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	7		T234	4		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T164	6		T244	10		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	9		T55	18		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	11		T62	3		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	16		T149	4		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	3		T201	4		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T233	12		T254	27		T257	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	8		T161	2		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	16		T62	8		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T154	9		T55	13		T41	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T155	5		T153	14		T173	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	23		T9	12		T64	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T147	18		T29	12		T158	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T149	9		T45	3		T261	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T63	4		T152	2		T201	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T52	5		T41	11		T114	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T152	8		T52	9		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T267	11		T269	11		T270	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T229	12		T15	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T251	1		T264	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T163	1		T271	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T189	7		T167	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T1	1		T127	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T147	8		T234	9		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T62	3		T265	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T52	8		T55	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	10		T43	5		T31	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T151	6		T161	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	21		T147	13		T162	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T35	16		T150	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T60	9		T161	1		T150	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	19		T62	14		T159	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T172	1		T151	4		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T40	2		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T154	13		T102	1		T23	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T11	1		T147	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	12		T149	2		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T63	6		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1817	1			T3	17		T4	17		T5	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T151	9		T152	28		T52	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	1		T264	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T271	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T189	4		T272	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T23	1		T234	14		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	7		T234	4		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T62	3		T254	2		T273	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T52	9		T55	18		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	11		T43	1		T31	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T161	16		T149	4		T92	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	14		T162	9		T201	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T254	27		T247	17		T262	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T60	8		T161	2		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	16		T62	8		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	13		T41	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T155	5		T92	8		T99	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T154	9		T23	12		T173	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T147	18		T158	6		T253	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T149	9		T45	3		T109	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T63	4		T29	12		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T5	23		T9	12		T64	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T152	10		T52	9		T31	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T127	1		T53	1		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T147	8		T102	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T265	1		T164	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T52	10		T55	19		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T7	12		T62	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T151	1		T161	17		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T44	8		T201	5		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	1		T70	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T60	9		T172	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	18		T62	9		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T154	10		T51	1		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T11	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T4	2		T5	25		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T147	19		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T55	1		T149	11		T45	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T63	5		T152	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T11	1		T52	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T152	9		T52	10		T31	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T57	1		T266	1		T267	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T151	1		T157	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T56	13		T57	6		T24	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T147	7		T234	8		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T164	2		T244	12		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	7		T39	8		T41	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	20		T7	9		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	5		T156	9		T189	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T44	3		T201	7		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T35	15		T196	9		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T60	8		T151	3		T111	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	17		T62	13		T92	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T154	12		T51	12		T41	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T159	21		T155	9		T153	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T4	15		T6	18		T10	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	13		T29	11		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T45	3		T276	10		T277	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T63	5		T152	11		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	16		T52	2		T41	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T152	15		T52	7		T24	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T57	9		T266	13		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T151	8		T157	5		T229	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T251	2		T264	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T163	1		T271	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T189	5		T167	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T1	1		T127	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T147	8		T234	5		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T62	4		T265	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	10		T55	19		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	12		T43	4		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	1		T161	17		T149	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	1		T147	15		T162	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	1		T150	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T60	9		T161	3		T150	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	18		T62	9		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T172	1		T151	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T40	2		T66	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T154	10		T102	1		T23	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T11	1		T147	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T51	1		T149	11		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T63	5		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T3	1		T4	2		T5	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T151	1		T152	12		T52	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T271	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T189	6		T272	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T56	13		T57	6		T24	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T147	7		T234	8		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T62	2		T170	10		T278	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T52	7		T39	8		T41	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	9		T43	2		T31	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	5		T156	9		T246	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	20		T147	12		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T35	15		T247	11		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	8		T44	3		T30	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	17		T62	13		T159	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T151	3		T51	12		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	9		T92	17		T99	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T154	12		T23	13		T196	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T147	13		T253	16		T275	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T51	11		T45	3		T109	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T63	5		T29	11		T166	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T3	16		T4	15		T6	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T151	8		T152	26		T52	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18