Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17843

1

T2

119

T3

38

T7

75

auto[ADC_CTRL_FILTER_COND_OUT]

5583

1

T1

3

T4

17

T5

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17445

1

T1

1

T2

119

T3

38

auto[1]

5981

1

T1

2

T4

17

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T169	1		-	-		-	-
values[0]	64	1			T39	19		T254	3		T262	23
values[1]	579	1			T1	1		T147	32		T51	1
values[2]	576	1			T7	1		T151	9		T147	15
values[3]	629	1			T1	1		T127	1		T62	28
values[4]	578	1			T52	8		T41	17		T114	12
values[5]	758	1			T11	1		T53	1		T55	14
values[6]	798	1			T3	17		T63	10		T151	6
values[7]	617	1			T7	21		T60	17		T161	17
values[8]	725	1			T11	1		T52	17		T31	4
values[9]	3875	1			T1	1		T3	21		T4	17
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T1	1		T147	32		T51	1
values[1]	2917	1			T1	1		T4	17		T5	25
values[2]	710	1			T62	28		T172	1		T152	24
values[3]	599	1			T11	1		T151	4		T55	14
values[4]	870	1			T151	6		T161	3		T53	1
values[5]	779	1			T3	17		T7	21		T60	17
values[6]	524	1			T161	17		T55	19		T41	29
values[7]	805	1			T3	21		T11	1		T52	17
values[8]	1034	1			T1	1		T7	34		T11	1
values[9]	215	1			T154	22		T159	22		T152	14
minimum	14240	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T147	14		T51	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T55	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	1		T151	9		T56	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T1	1		T4	17		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T62	17		T52	3		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T172	1		T152	16		T41	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T151	4		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	10		T41	9		T29	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T151	6		T161	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T31	6		T245	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	17		T7	10		T60	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T57	7		T35	16		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T162	10		T150	1		T156	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	1		T55	1		T41	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	21		T52	8		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T155	10		T12	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T7	18		T92	18		T179	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T1	1		T11	1		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T52	8		T279	6		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T154	13		T159	22		T152	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14138	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T201	8		T280	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T147	18		T39	10		T23	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T39	1		T253	1		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T44	3		T92	4		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	979	1			T5	23		T9	12		T64	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T62	11		T52	5		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T152	8		T41	8		T23	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T55	13		T114	7		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	8		T29	12		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T161	2		T164	6		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	3		T245	4		T49	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	11		T60	8		T63	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T166	14		T257	14		T239	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T162	9		T234	6		T258	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T161	16		T55	18		T41	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T52	9		T31	3		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T155	5		T12	1		T253	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	16		T92	8		T109	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	3		T27	10		T234	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T52	9		T279	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T154	9		T152	2		T99	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T201	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T169	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T39	9		T254	1		T262	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T281	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T147	14		T51	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T55	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T151	9		T56	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	8		T23	4		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T62	17		T151	4		T44	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T127	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T52	3		T114	5		T153	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	9		T29	12		T189	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T53	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T31	6		T30	5		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	17		T63	6		T151	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T57	7		T41	18		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	10		T60	9		T43	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T161	1		T55	1		T35	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T52	8		T31	1		T156	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T155	10		T12	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T3	21		T7	18		T52	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1929	1			T1	1		T4	17		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T39	10		T254	2		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T147	18		T23	12		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T39	1		T201	4		T253	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T179	11		T173	12		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T147	7		T23	4		T282	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T62	11		T44	3		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T152	8		T41	8		T70	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T52	5		T114	7		T153	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T41	8		T29	12		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	13		T149	9		T164	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	3		T245	4		T165	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T63	4		T147	14		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	11		T49	4		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	11		T60	8		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T161	16		T55	18		T201	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T52	9		T31	3		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	5		T12	1		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T7	16		T52	9		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1207	1			T5	23		T9	12		T64	29
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T147	19		T51	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	1		T55	1		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	1		T151	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T1	1		T4	2		T5	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T62	13		T52	6		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T172	1		T152	9		T41	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T151	1		T55	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T57	1		T41	9		T29	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T151	1		T161	3		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T31	4		T245	5		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T7	12		T60	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T57	1		T35	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T162	10		T150	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T161	17		T55	19		T41	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	1		T52	10		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T155	6		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T7	17		T92	9		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T11	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T52	10		T279	6		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T154	10		T159	1		T152	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14227	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T201	5		T280	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	13		T39	8		T23	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T236	8		T175	14		T283	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	8		T56	13		T156	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1264	1			T4	15		T6	18		T10	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T62	15		T52	2		T30	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	15		T41	8		T23	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	3		T114	4		T153	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T57	9		T41	8		T29	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T151	5		T164	2		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	5		T49	3		T275	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	16		T7	9		T60	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T57	6		T35	15		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T162	9		T156	9		T234	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T41	17		T284	11		T285	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	20		T52	7		T111	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	9		T12	2		T157	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T7	17		T92	17		T179	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T51	12		T45	3		T224	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T52	7		T279	2		T286	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T154	12		T159	21		T152	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T201	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T169	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T39	11		T254	3		T262	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T147	19		T51	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T55	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T151	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	8		T23	6		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T62	13		T151	1		T44	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T127	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T52	6		T114	8		T153	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	9		T29	13		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T53	1		T55	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	4		T30	1		T245	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	1		T63	5		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T57	1		T41	12		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	12		T60	9		T43	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	17		T55	19		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T52	10		T31	4		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T155	6		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T3	1		T7	17		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1597	1			T1	1		T4	2		T5	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T39	8		T262	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T281	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T147	13		T23	13		T166	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T201	7		T175	14		T287	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	8		T56	13		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T147	7		T23	2		T236	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T62	15		T151	3		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T152	15		T57	9		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	2		T114	4		T153	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	8		T29	11		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	2		T243	12		T109	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	5		T30	4		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	16		T63	5		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T57	6		T41	17		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	9		T60	8		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	15		T166	14		T196	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	7		T156	9		T187	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T155	9		T12	2		T157	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T3	20		T7	17		T52	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1539	1			T4	15		T6	18		T10	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18