Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19756

1

T1

3

T2

119

T4

17

auto[ADC_CTRL_FILTER_COND_OUT]

3670

1

T3

38

T7

34

T60

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17141

1

T1

2

T2

116

T7

53

auto[1]

6285

1

T1

1

T2

3

T3

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	591	1			T2	3		T62	6		T63	10
values[0]	1	1			T251	1		-	-		-	-
values[1]	675	1			T159	22		T52	17		T57	10
values[2]	3104	1			T4	17		T5	25		T6	20
values[3]	759	1			T11	1		T62	22		T147	59
values[4]	798	1			T1	1		T151	6		T154	22
values[5]	604	1			T1	1		T7	1		T11	1
values[6]	612	1			T7	21		T151	9		T51	13
values[7]	668	1			T1	1		T3	21		T161	17
values[8]	550	1			T11	1		T127	1		T152	14
values[9]	1207	1			T3	17		T7	34		T172	1
minimum	13857	1			T2	116		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	738	1			T159	22		T51	12		T52	17
values[1]	3213	1			T4	17		T5	25		T6	20
values[2]	694	1			T11	1		T151	6		T154	22
values[3]	733	1			T1	1		T147	47		T149	5
values[4]	620	1			T1	1		T7	22		T11	1
values[5]	604	1			T1	1		T51	13		T53	2
values[6]	609	1			T3	21		T127	1		T161	17
values[7]	709	1			T11	1		T152	14		T51	1
values[8]	953	1			T3	17		T7	34		T62	6
values[9]	231	1			T52	8		T233	13		T253	2
minimum	14322	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	8		T150	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T159	22		T51	12		T111	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T4	17		T5	2		T6	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T60	9		T55	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T151	6		T147	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T154	13		T43	5		T30	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T147	22		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T234	13		T46	1		T189	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T7	11		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T161	1		T150	1		T201	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T35	16		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T51	13		T53	2		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T161	1		T57	7		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	21		T127	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	1		T51	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	12		T157	12		T243	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T151	4		T152	16		T52	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	17		T7	18		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T52	3		T253	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T233	1		T257	11		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14177	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T57	10		T228	1		T175	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T52	9		T254	2		T168	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T111	9		T92	4		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T5	23		T9	12		T64	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T60	8		T55	13		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T147	14		T245	9		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T154	9		T43	1		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T147	25		T149	4		T155	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T234	14		T189	4		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	11		T233	12		T235	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T161	2		T201	4		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T44	3		T201	4		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T55	18		T39	10		T27	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T161	16		T23	1		T30	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T165	11		T158	4		T109	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	3		T41	8		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T152	2		T243	9		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	8		T52	9		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	16		T62	3		T63	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T52	5		T253	1		T240	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T233	12		T257	13		T215	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T228	1		T289	6		T290	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T2	3		T43	10		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T62	3		T63	6		T41	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	8		T150	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T159	22		T57	10		T111	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T4	17		T5	2		T6	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T60	9		T51	12		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	1		T62	14		T147	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	5		T30	5		T180	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T151	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T154	13		T234	17		T189	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T7	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T161	1		T55	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	10		T151	9		T35	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T51	13		T53	2		T39	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T161	1		T57	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	21		T149	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T51	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	1		T152	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T151	4		T152	16		T52	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T3	17		T7	18		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13768	1			T2	116		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T180	4		T231	2		T227	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T62	3		T63	4		T41	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T52	9		T168	20		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T111	9		T92	4		T23	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T5	23		T9	12		T64	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T60	8		T55	13		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T62	8		T147	32		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	1		T180	27		T261	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T149	4		T245	9		T230	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	9		T234	6		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T147	7		T155	5		T235	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T161	2		T55	18		T201	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	11		T44	3		T201	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	10		T27	10		T234	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T161	16		T23	1		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T164	6		T165	11		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T31	3		T41	8		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T152	2		T243	9		T229	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T152	8		T52	14		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T7	16		T41	8		T92	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T52	10		T150	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T159	1		T51	1		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T4	2		T5	25		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T60	9		T55	14		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T151	1		T147	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T154	10		T43	4		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T147	27		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T234	15		T46	1		T189	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T7	13		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T161	3		T150	1		T201	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T35	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T51	1		T53	2		T55	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	17		T57	1		T23	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T127	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	1		T51	1		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	3		T157	1		T243	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	1		T152	9		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	1		T7	17		T62	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T52	6		T253	2		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T233	13		T257	14		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14251	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T57	1		T228	2		T175	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T52	7		T168	14		T198	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T159	21		T51	11		T111	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T4	15		T6	18		T10	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T60	8		T162	9		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	5		T147	12		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	12		T43	2		T30	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T147	20		T155	9		T246	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T234	12		T189	6		T291	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	9		T151	8		T246	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T201	7		T189	6		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	15		T44	3		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	12		T39	8		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	6		T30	13		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	20		T156	9		T109	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	8		T12	2		T196	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	11		T157	11		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T151	3		T152	15		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	16		T7	17		T62	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T52	2		T240	6		T292	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T257	10		T215	15		T198	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T287	9		T293	2		T294	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T57	9		T175	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T2	3		T43	10		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T62	4		T63	5		T41	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	10		T150	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T159	1		T57	1		T111	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T4	2		T5	25		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T60	9		T51	1		T55	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T62	9		T147	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	4		T30	1		T180	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T151	1		T149	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T154	10		T234	7		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T7	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T161	3		T55	19		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	12		T151	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T51	1		T53	2		T39	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T161	17		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T149	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	1		T51	1		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T127	1		T152	3		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T151	1		T152	9		T52	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T3	1		T7	17		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13857	1			T2	116		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T180	4		T274	8		T240	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T62	2		T63	5		T41	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T52	7		T168	14		T287	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T159	21		T57	9		T111	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T4	15		T6	18		T10	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T60	8		T51	11		T162	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T62	13		T147	25		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T43	2		T30	4		T180	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T151	5		T230	4		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T154	12		T234	16		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T147	7		T155	9		T246	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T201	7		T234	12		T189	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	9		T151	8		T35	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	12		T39	8		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	6		T30	13		T157	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	20		T156	9		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	8		T12	2		T196	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T152	11		T157	11		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T151	3		T152	15		T52	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	16		T7	17		T41	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18