Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19713

1

T1

2

T2

119

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3713

1

T1

1

T7

35

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17245

1

T1

2

T2

119

T3

17

auto[1]

6181

1

T1

1

T3

21

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T231	9		T169	1		T227	16
values[0]	139	1			T179	20		T47	2		T295	1
values[1]	855	1			T151	6		T152	24		T161	17
values[2]	712	1			T1	1		T7	1		T151	4
values[3]	561	1			T152	14		T161	3		T51	1
values[4]	679	1			T11	1		T39	19		T41	29
values[5]	3116	1			T4	17		T5	25		T6	20
values[6]	582	1			T1	1		T11	1		T63	10
values[7]	769	1			T1	1		T3	38		T7	34
values[8]	680	1			T7	21		T172	1		T159	22
values[9]	1081	1			T60	17		T62	6		T151	9
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1079	1			T1	1		T151	10		T147	15
values[1]	837	1			T7	1		T152	14		T57	17
values[2]	644	1			T161	3		T51	1		T55	14
values[3]	3024	1			T4	17		T5	25		T6	20
values[4]	555	1			T1	1		T62	22		T56	14
values[5]	740	1			T3	21		T11	1		T63	10
values[6]	751	1			T3	17		T7	55		T11	1
values[7]	598	1			T1	1		T172	1		T159	22
values[8]	717	1			T60	17		T62	6		T151	9
values[9]	236	1			T52	17		T44	9		T45	11
minimum	14245	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T151	6		T152	16		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T1	1		T151	4		T147	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T152	12		T57	7		T35	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T7	1		T57	10		T114	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T161	1		T51	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	2		T41	18		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T4	17		T5	2		T6	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T252	1		T265	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T56	14		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T62	14		T111	9		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	21		T63	6		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T147	13		T43	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	17		T7	10		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	18		T27	1		T246	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T53	1		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T172	1		T159	22		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T60	9		T62	3		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	9		T156	10		T234	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T165	1		T176	14		T287	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T52	8		T44	6		T45	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14154	1			T2	119		T7	18		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	8		T161	16		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T147	7		T52	14		T55	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T152	2		T201	4		T253	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T114	7		T192	7		T253	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T161	2		T55	13		T234	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	11		T243	2		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T5	23		T9	12		T64	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T229	13		T247	12		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T31	3		T153	14		T23	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T62	8		T111	9		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T63	4		T154	9		T41	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T147	14		T43	1		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	11		T147	18		T41	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	16		T27	10		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T92	4		T201	4		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T92	8		T29	12		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T60	8		T62	3		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T234	6		T173	12		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T165	11		T176	4		T287	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T52	9		T44	3		T45	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	1		T43	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	1		T169	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T227	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T179	1		T295	1		T275	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T179	8		T47	2		T296	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T151	6		T152	16		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T52	8		T55	1		T57	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T57	7		T35	16		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	1		T7	1		T151	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T152	12		T161	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	2		T24	11		T230	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T39	9		T234	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T41	18		T150	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1680	1			T4	17		T5	2		T6	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T62	14		T111	9		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T63	6		T51	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T147	13		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	1		T3	38		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	18		T43	5		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	10		T53	1		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T172	1		T159	22		T92	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T60	9		T62	3		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T151	9		T51	13		T52	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T231	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T227	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T179	11		T297	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T238	10		T298	10		T299	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T152	8		T161	16		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T52	9		T55	18		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T50	2		T271	11		T239	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T147	7		T52	5		T114	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T152	2		T161	2		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T230	4		T273	4		T176	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	10		T234	4		T180	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	11		T243	2		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T5	23		T9	12		T64	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T62	8		T111	9		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T63	4		T41	8		T23	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T147	14		T155	5		T23	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T154	9		T147	18		T158	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	16		T43	1		T27	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	11		T41	8		T99	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T92	8		T29	12		T189	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T60	8		T62	3		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T52	9		T44	3		T45	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T151	1		T152	9		T161	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T1	1		T151	1		T147	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	3		T57	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	1		T57	1		T114	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T161	3		T51	1		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	2		T41	12		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T4	2		T5	25		T6	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T252	1		T265	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T56	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T62	9		T111	10		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T63	5		T154	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	1		T147	15		T43	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T7	12		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	17		T27	11		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T53	1		T92	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T172	1		T159	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T60	9		T62	4		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T151	1		T156	1		T234	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T165	12		T176	5		T287	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T52	10		T44	6		T45	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14230	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	5		T152	15		T224	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T151	3		T147	7		T52	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	11		T57	6		T35	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T57	9		T114	4		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T234	20		T246	15		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	17		T243	2		T230	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T4	15		T6	18		T10	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T229	10		T247	11		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	13		T156	11		T153	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T62	13		T111	8		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	20		T63	5		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	12		T43	2		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	16		T7	9		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	17		T246	4		T189	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	2		T30	13		T157	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T159	21		T51	12		T92	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	8		T62	2		T31	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T151	8		T156	9		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T176	13		T287	9		T300	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T52	7		T44	3		T45	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T275	7		T297	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T231	9		T169	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T227	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T179	12		T295	1		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	1		T47	2		T296	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T151	1		T152	9		T161	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T52	10		T55	19		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T57	1		T35	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	1		T7	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	3		T161	3		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	2		T24	1		T230	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T39	11		T234	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	12		T150	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T4	2		T5	25		T6	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T62	9		T111	10		T244	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T63	5		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T147	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T3	2		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	17		T43	4		T27	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	12		T53	1		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T172	1		T159	1		T92	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T60	9		T62	4		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T151	1		T51	1		T52	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T275	7		T297	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T179	7		T296	6		T274	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	5		T152	15		T224	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T52	7		T57	9		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T57	6		T35	15		T246	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T151	3		T147	7		T52	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	11		T201	7		T234	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	10		T230	5		T291	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	8		T234	8		T180	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	17		T243	2		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T4	15		T6	18		T10	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T62	13		T111	8		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T63	5		T51	11		T56	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T147	12		T155	9		T23	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	36		T154	12		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	17		T43	2		T109	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	9		T41	8		T99	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T159	21		T92	17		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T60	8		T62	2		T31	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T151	8		T51	12		T52	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18