Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20142

1

T1

1

T2

119

T3

21

auto[ADC_CTRL_FILTER_COND_OUT]

3284

1

T1

2

T3

17

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17391

1

T1

1

T2

119

T3

17

auto[1]

6035

1

T1

2

T3

21

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T245	5		T305	1		T306	1
values[0]	80	1			T51	1		T23	6		T282	15
values[1]	641	1			T151	6		T52	17		T34	1
values[2]	3165	1			T3	17		T4	17		T5	25
values[3]	478	1			T1	1		T55	1		T57	7
values[4]	708	1			T1	1		T3	21		T7	21
values[5]	809	1			T7	34		T151	4		T154	22
values[6]	601	1			T1	1		T11	1		T63	10
values[7]	606	1			T172	1		T52	25		T53	1
values[8]	793	1			T11	1		T62	22		T147	42
values[9]	1312	1			T7	1		T127	1		T159	22
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	817	1			T3	17		T151	6		T51	14
values[1]	3101	1			T4	17		T5	25		T6	20
values[2]	503	1			T1	1		T11	1		T161	17
values[3]	899	1			T1	1		T3	21		T7	55
values[4]	584	1			T151	4		T43	6		T55	14
values[5]	591	1			T1	1		T11	1		T172	1
values[6]	695	1			T11	1		T62	22		T56	14
values[7]	774	1			T7	1		T147	42		T152	24
values[8]	919	1			T127	1		T159	22		T57	10
values[9]	255	1			T161	3		T27	11		T245	5
minimum	14288	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T151	6		T51	14		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	17		T52	8		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T4	17		T5	2		T6	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T55	1		T35	16		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T57	7		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	1		T161	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	21		T7	10		T151	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T7	18		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T151	4		T55	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T43	5		T40	2		T92	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T147	14		T53	1		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T11	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T56	14		T156	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	14		T149	1		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T7	1		T147	13		T152	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T147	8		T245	1		T246	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T127	1		T159	22		T57	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T29	12		T225	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T229	11		T296	7		T275	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T161	1		T27	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14141	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T165	1		T270	18		T307	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	3		T41	8		T114	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	9		T39	10		T23	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T5	23		T9	12		T64	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T149	9		T201	4		T164	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	1		T92	4		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T161	16		T162	9		T23	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	11		T154	9		T55	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	16		T41	8		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T55	13		T229	12		T192	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T43	1		T92	8		T109	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T147	18		T234	4		T32	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T63	4		T52	5		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T180	15		T13	1		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	8		T149	4		T153	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T147	14		T152	8		T52	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T147	7		T245	9		T254	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	13		T189	6		T166	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	12		T180	12		T247	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T229	13		T258	9		T176	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T161	2		T27	10		T245	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T270	14		T307	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T245	1		T305	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T51	1		T23	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T282	1		T308	9		T241	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	6		T34	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T52	8		T39	9		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T4	17		T5	2		T6	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	17		T35	16		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T57	7		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T55	1		T41	9		T111	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	21		T7	10		T151	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T11	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T151	4		T154	13		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	18		T40	2		T92	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T147	14		T55	1		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T11	1		T63	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T52	8		T53	1		T156	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T172	1		T52	3		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T11	1		T147	13		T152	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T62	14		T147	8		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T7	1		T127	1		T159	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T161	1		T27	1		T29	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T23	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T282	14		T308	8		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T173	9		T109	5		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	9		T39	10		T23	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T5	23		T9	12		T64	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T201	4		T164	6		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T39	1		T45	3		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	8		T111	9		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	11		T55	18		T41	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T161	16		T234	14		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	9		T155	5		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	16		T92	8		T109	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	18		T55	13		T32	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T63	4		T43	1		T234	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	9		T234	4		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T52	5		T149	4		T165	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	14		T152	8		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T62	8		T147	7		T153	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T30	13		T173	12		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T161	2		T27	10		T29	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T151	1		T51	2		T31	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	1		T52	10		T39	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T4	2		T5	25		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T55	1		T35	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T57	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T161	17		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T7	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T7	17		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T151	1		T55	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T43	4		T40	2		T92	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T147	19		T53	1		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	1		T11	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T56	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T62	9		T149	5		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T147	15		T152	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T147	8		T245	10		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T127	1		T159	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	13		T225	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T229	14		T296	1		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T161	3		T27	11		T245	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14230	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T165	1		T270	15		T307	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	5		T51	12		T41	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	16		T52	7		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T4	15		T6	18		T10	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	15		T164	2		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T57	6		T24	10		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T162	9		T23	13		T309	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	20		T7	9		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	17		T41	8		T111	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T151	3		T229	12		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T43	2		T92	17		T109	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T147	13		T234	8		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T63	5		T51	11		T52	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T56	13		T156	9		T180	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T62	13		T156	11		T153	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T147	12		T152	15		T52	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	7		T246	15		T175	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T159	21		T57	9		T24	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T29	11		T180	12		T275	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T229	10		T296	6		T275	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T157	5		T166	12		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T310	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T270	17		T307	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T245	5		T305	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T51	1		T23	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T282	15		T308	9		T241	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	1		T34	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T52	10		T39	11		T23	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T4	2		T5	25		T6	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T35	1		T201	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	1		T57	1		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T55	1		T41	9		T111	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T7	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T11	1		T161	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T151	1		T154	10		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	17		T40	2		T92	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	19		T55	14		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T11	1		T63	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	10		T53	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T172	1		T52	6		T149	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	1		T147	15		T152	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T62	9		T147	8		T153	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T7	1		T127	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T161	3		T27	11		T29	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T23	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T308	8		T241	4		T270	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T151	5		T109	3		T283	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	7		T39	8		T246	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T4	15		T6	18		T10	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	16		T35	15		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T57	6		T45	3		T24	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T41	8		T111	8		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	20		T7	9		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T234	12		T229	11		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T151	3		T154	12		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	17		T92	17		T30	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T147	13		T32	11		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T63	5		T43	2		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T52	7		T156	9		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T52	2		T156	11		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T147	12		T152	15		T56	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T62	13		T147	7		T153	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T159	21		T57	9		T24	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T29	11		T157	5		T180	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18