Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23426

1

T1

3

T2

119

T3

38

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19852

1

T2

119

T4

17

T5

25

auto[ADC_CTRL_FILTER_COND_OUT]

3574

1

T1

3

T3

38

T7

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17462

1

T2

119

T3

21

T7

41

auto[1]

5964

1

T1

3

T3

17

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

3

T2

119

T3

38

auto[1]

3866

1

T5

23

T7

28

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	73	1			T52	17		T23	26		T291	10
values[0]	38	1			T148	3		T282	5		T301	26
values[1]	526	1			T53	1		T31	4		T102	1
values[2]	772	1			T11	1		T151	6		T43	6
values[3]	683	1			T3	38		T60	17		T99	5
values[4]	717	1			T1	1		T151	4		T147	15
values[5]	816	1			T7	1		T154	22		T147	32
values[6]	740	1			T7	34		T62	6		T161	17
values[7]	592	1			T7	21		T52	8		T53	1
values[8]	3142	1			T4	17		T5	25		T6	20
values[9]	1101	1			T1	2		T11	2		T62	22
minimum	14226	1			T2	119		T7	19		T60	28

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T151	6		T51	12		T53	1
values[1]	590	1			T11	1		T43	6		T31	9
values[2]	831	1			T3	38		T60	17		T151	4
values[3]	703	1			T1	1		T147	15		T152	14
values[4]	944	1			T7	1		T154	22		T147	32
values[5]	627	1			T7	34		T62	6		T161	17
values[6]	2921	1			T4	17		T5	25		T6	20
values[7]	839	1			T1	1		T11	1		T127	1
values[8]	820	1			T62	22		T159	22		T147	27
values[9]	169	1			T1	1		T11	1		T52	17
minimum	14262	1			T2	119		T7	19		T60	28

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

4399

1

T3

36

T4

15

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T151	6		T31	1		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	12		T53	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T149	1		T30	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	5		T31	6		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	9		T99	4		T234	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T3	38		T60	9		T151	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T152	12		T39	9		T201	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T147	8		T52	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T161	1		T57	7		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	1		T154	13		T147	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T161	1		T52	3		T35	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	18		T62	3		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T4	17		T5	2		T6	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	10		T149	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T127	1		T151	9		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T11	1		T57	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T62	14		T152	16		T162	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T159	22		T147	13		T155	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T55	1		T56	14		T168	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T1	1		T11	1		T52	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14139	1			T2	119		T7	18		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T311	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T31	3		T189	4		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T109	2		T236	11		T253	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T149	4		T30	13		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T43	1		T31	3		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T41	8		T99	1		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T60	8		T245	9		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T152	2		T39	10		T201	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T147	7		T52	9		T55	31
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T161	2		T234	4		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T154	9		T147	18		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T161	16		T52	5		T41	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T7	16		T62	3		T23	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T5	23		T9	12		T64	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	11		T149	9		T23	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T153	14		T201	4		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	8		T92	8		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T62	8		T152	8		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T147	14		T155	5		T44	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T168	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T52	9		T258	9		T301	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T43	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T311	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T291	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T52	8		T23	14		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T301	14		T251	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T148	2		T282	1		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	1		T102	1		T189	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T53	1		T252	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	1		T151	6		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	5		T51	12		T31	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T99	4		T211	1		T180	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	38		T60	9		T245	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T152	12		T39	9		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T151	4		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T161	1		T57	7		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	1		T154	13		T147	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T161	1		T35	16		T41	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	18		T62	3		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T52	3		T53	1		T114	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	10		T149	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T4	17		T5	2		T6	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T246	5		T165	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T62	14		T152	16		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T1	2		T11	2		T159	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14137	1			T2	119		T7	18		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T52	9		T23	12		T312	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T301	12		T251	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T148	1		T282	4		T313	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T31	3		T189	4		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T109	2		T253	1		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T149	4		T30	13		T189	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	1		T31	3		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T99	1		T180	15		T253	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T60	8		T245	13		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T152	2		T39	10		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T147	7		T52	9		T55	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T161	2		T234	4		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T154	9		T147	18		T92	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T161	16		T41	11		T29	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	16		T62	3		T228	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T52	5		T114	7		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T7	11		T149	9		T23	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T5	23		T9	12		T64	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T173	9		T243	2		T230	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T62	8		T152	8		T162	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T147	14		T41	8		T155	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	1		T43	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T151	1		T31	4		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	1		T53	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T149	5		T30	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T43	4		T31	4		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	9		T99	2		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T3	2		T60	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T152	3		T39	11		T201	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	1		T147	8		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T161	3		T57	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T154	10		T147	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T161	17		T52	6		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	17		T62	4		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T4	2		T5	25		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	12		T149	10		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T127	1		T151	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T11	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T62	9		T152	9		T162	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T159	1		T147	15		T155	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T55	1		T56	1		T168	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	1		T11	1		T52	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14245	1			T2	119		T7	19		T60	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T311	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T151	5		T189	6		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	11		T109	16		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T30	13		T229	10		T253	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T43	2		T31	5		T111	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T41	8		T99	3		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	36		T60	8		T151	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	11		T39	8		T201	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T147	7		T52	7		T24	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T57	6		T234	8		T157	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T154	12		T147	13		T51	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	2		T35	15		T41	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	17		T62	2		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T4	15		T6	18		T10	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T7	9		T23	2		T179	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T151	8		T153	16		T30	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T57	9		T41	8		T92	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T62	13		T152	15		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T159	21		T147	12		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T56	13		T168	2		T248	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T52	7		T301	9		T286	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T311	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T52	10		T23	13		T312	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T301	13		T251	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T148	2		T282	5		T313	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T31	4		T102	1		T189	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	1		T252	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T151	1		T149	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	4		T51	1		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T99	2		T211	1		T180	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	2		T60	9		T245	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	3		T39	11		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	1		T151	1		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T161	3		T57	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	1		T154	10		T147	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T161	17		T35	1		T41	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	17		T62	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	6		T53	1		T114	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	12		T149	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T4	2		T5	25		T6	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T246	1		T165	1		T173	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	9		T152	9		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T1	2		T11	2		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14226	1			T2	119		T7	19		T60	28
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T291	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T52	7		T23	13		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T301	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T148	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T189	6		T253	16		T284	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	16		T296	7		T176	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T151	5		T30	13		T189	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	2		T51	11		T31	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T99	3		T180	14		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	36		T60	8		T236	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T152	11		T39	8		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T151	3		T147	7		T52	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	6		T156	9		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T154	12		T147	13		T51	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T35	15		T41	17		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	17		T62	2		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	2		T114	4		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	9		T23	2		T179	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T4	15		T6	18		T10	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T246	4		T243	2		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T62	13		T152	15		T56	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T159	21		T147	12		T57	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19027

1

T1

3

T2

119

T3

2

auto[1]

auto[0]

4399

1

T3

36

T4

15

T6

18