Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.51


Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T789 /workspace/coverage/default/19.adc_ctrl_lowpower_counter.302570249 Aug 17 05:28:36 PM PDT 24 Aug 17 05:29:09 PM PDT 24 28941903748 ps
T790 /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1946719477 Aug 17 05:28:18 PM PDT 24 Aug 17 05:28:28 PM PDT 24 13314972036 ps
T791 /workspace/coverage/default/28.adc_ctrl_filters_polled.1428736894 Aug 17 05:29:09 PM PDT 24 Aug 17 05:35:19 PM PDT 24 326455770443 ps
T792 /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3229158067 Aug 17 05:28:11 PM PDT 24 Aug 17 05:28:20 PM PDT 24 1769882243 ps
T793 /workspace/coverage/default/25.adc_ctrl_stress_all.1447659362 Aug 17 05:28:55 PM PDT 24 Aug 17 05:32:45 PM PDT 24 542398844111 ps
T794 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.586607500 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:56 PM PDT 24 412562277 ps
T795 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2445172745 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:02 PM PDT 24 474665564 ps
T796 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3470227259 Aug 17 06:35:02 PM PDT 24 Aug 17 06:35:04 PM PDT 24 368482948 ps
T129 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1843732972 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:00 PM PDT 24 457338331 ps
T797 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2508124191 Aug 17 06:35:14 PM PDT 24 Aug 17 06:35:16 PM PDT 24 492105493 ps
T100 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456026 Aug 17 06:35:06 PM PDT 24 Aug 17 06:35:10 PM PDT 24 475186834 ps
T77 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3071980294 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:53 PM PDT 24 979259633 ps
T74 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2208079636 Aug 17 06:35:05 PM PDT 24 Aug 17 06:35:24 PM PDT 24 8176475307 ps
T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3406049455 Aug 17 06:35:07 PM PDT 24 Aug 17 06:35:11 PM PDT 24 4736801229 ps
T82 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.861999524 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:01 PM PDT 24 630828325 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.825486883 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:53 PM PDT 24 370400093 ps
T87 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3714276104 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:57 PM PDT 24 487056187 ps
T798 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3760811826 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:52 PM PDT 24 433623757 ps
T83 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2984109386 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:59 PM PDT 24 332991190 ps
T131 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4125006915 Aug 17 06:34:44 PM PDT 24 Aug 17 06:34:48 PM PDT 24 891212505 ps
T76 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1527523741 Aug 17 06:34:53 PM PDT 24 Aug 17 06:35:09 PM PDT 24 7819122640 ps
T799 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2861863433 Aug 17 06:35:04 PM PDT 24 Aug 17 06:35:06 PM PDT 24 336049442 ps
T71 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2487944932 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:13 PM PDT 24 4053564431 ps
T72 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3573644292 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:53 PM PDT 24 2585170693 ps
T73 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2542287518 Aug 17 06:34:55 PM PDT 24 Aug 17 06:36:15 PM PDT 24 19575288188 ps
T144 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2290196948 Aug 17 06:34:54 PM PDT 24 Aug 17 06:35:07 PM PDT 24 5357215131 ps
T84 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1009244647 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 741990671 ps
T132 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2637759110 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:04 PM PDT 24 572857096 ps
T78 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2423902545 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:56 PM PDT 24 7952307144 ps
T101 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2030995147 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:53 PM PDT 24 762479764 ps
T88 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.26836840 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:58 PM PDT 24 460256879 ps
T800 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2393558774 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:50 PM PDT 24 592615378 ps
T801 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.648429085 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:03 PM PDT 24 365896641 ps
T145 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.398762844 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:55 PM PDT 24 2697202757 ps
T802 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3672897614 Aug 17 06:34:35 PM PDT 24 Aug 17 06:34:36 PM PDT 24 427335176 ps
T133 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.902181906 Aug 17 06:34:57 PM PDT 24 Aug 17 06:35:10 PM PDT 24 32909258698 ps
T342 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1032000685 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:04 PM PDT 24 5677574081 ps
T803 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2470529928 Aug 17 06:34:58 PM PDT 24 Aug 17 06:35:01 PM PDT 24 388188765 ps
T134 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.510592744 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:01 PM PDT 24 436360343 ps
T344 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3090813308 Aug 17 06:34:57 PM PDT 24 Aug 17 06:35:01 PM PDT 24 4148667550 ps
T804 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2895306401 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:57 PM PDT 24 374675905 ps
T805 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3902730685 Aug 17 06:35:05 PM PDT 24 Aug 17 06:35:06 PM PDT 24 514626972 ps
T806 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3238637038 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:02 PM PDT 24 492305798 ps
T345 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3520049334 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:49 PM PDT 24 4382802655 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1815640916 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:07 PM PDT 24 4534718565 ps
T808 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3804873994 Aug 17 06:35:02 PM PDT 24 Aug 17 06:35:03 PM PDT 24 340743608 ps
T135 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3331605262 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:55 PM PDT 24 563190957 ps
T809 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.656704202 Aug 17 06:35:02 PM PDT 24 Aug 17 06:35:03 PM PDT 24 532800395 ps
T146 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1145831410 Aug 17 06:35:02 PM PDT 24 Aug 17 06:35:04 PM PDT 24 420815820 ps
T810 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2747052926 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:57 PM PDT 24 405322697 ps
T811 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2076352621 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:02 PM PDT 24 314577016 ps
T812 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3641057593 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:56 PM PDT 24 748344580 ps
T813 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1690917264 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:55 PM PDT 24 358366201 ps
T814 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2147686383 Aug 17 06:35:08 PM PDT 24 Aug 17 06:35:09 PM PDT 24 491506140 ps
T815 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1087492264 Aug 17 06:34:58 PM PDT 24 Aug 17 06:35:01 PM PDT 24 493912056 ps
T816 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1892914868 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 307131745 ps
T817 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1335209869 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:54 PM PDT 24 496041060 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2611395734 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:45 PM PDT 24 405705702 ps
T819 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2649060442 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:56 PM PDT 24 551454991 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.718546302 Aug 17 06:34:55 PM PDT 24 Aug 17 06:35:06 PM PDT 24 4663390080 ps
T821 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1733966067 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:00 PM PDT 24 655624568 ps
T822 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.785825567 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:03 PM PDT 24 476547586 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1736912319 Aug 17 06:34:41 PM PDT 24 Aug 17 06:34:43 PM PDT 24 458706538 ps
T136 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3461847113 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:53 PM PDT 24 593706131 ps
T824 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4054789660 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:56 PM PDT 24 3857690753 ps
T825 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1014289745 Aug 17 06:34:55 PM PDT 24 Aug 17 06:35:04 PM PDT 24 8722790226 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.849043154 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:58 PM PDT 24 379410330 ps
T89 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2546893226 Aug 17 06:34:56 PM PDT 24 Aug 17 06:35:13 PM PDT 24 8886496981 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.995015332 Aug 17 06:35:07 PM PDT 24 Aug 17 06:35:09 PM PDT 24 412199377 ps
T828 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3994717608 Aug 17 06:35:07 PM PDT 24 Aug 17 06:35:08 PM PDT 24 418261629 ps
T829 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2210485738 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 379552865 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1843907959 Aug 17 06:34:32 PM PDT 24 Aug 17 06:34:34 PM PDT 24 592745113 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2353198871 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:59 PM PDT 24 607720273 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1423505968 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:25 PM PDT 24 8368120178 ps
T833 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.255437529 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:57 PM PDT 24 474130270 ps
T834 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.743634461 Aug 17 06:34:48 PM PDT 24 Aug 17 06:34:50 PM PDT 24 621327762 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.487763114 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:58 PM PDT 24 319988609 ps
T836 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2639288595 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:54 PM PDT 24 2060870547 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2418692064 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:52 PM PDT 24 350487782 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3994096941 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:54 PM PDT 24 345348000 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3567390480 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:58 PM PDT 24 331988122 ps
T839 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1059748424 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:03 PM PDT 24 374122327 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3286184268 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:55 PM PDT 24 4506459246 ps
T841 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3665960741 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:53 PM PDT 24 546563909 ps
T343 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2905310293 Aug 17 06:34:53 PM PDT 24 Aug 17 06:35:14 PM PDT 24 8326904682 ps
T842 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1087183051 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 525925054 ps
T843 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4047684428 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:59 PM PDT 24 374490102 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.59934299 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:56 PM PDT 24 833061846 ps
T845 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3587049547 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:57 PM PDT 24 420619989 ps
T846 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3363130684 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:57 PM PDT 24 522258574 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1751404991 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:53 PM PDT 24 5063809235 ps
T848 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2253436046 Aug 17 06:34:48 PM PDT 24 Aug 17 06:34:50 PM PDT 24 557742573 ps
T849 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1989677697 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:02 PM PDT 24 556029051 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3448244105 Aug 17 06:34:49 PM PDT 24 Aug 17 06:37:46 PM PDT 24 53391557120 ps
T138 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2853753764 Aug 17 06:34:36 PM PDT 24 Aug 17 06:34:46 PM PDT 24 1982905563 ps
T851 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1851228445 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:01 PM PDT 24 505545186 ps
T143 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2236613297 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:57 PM PDT 24 542881178 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1261791619 Aug 17 06:34:38 PM PDT 24 Aug 17 06:34:42 PM PDT 24 1457580390 ps
T853 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.310813822 Aug 17 06:34:58 PM PDT 24 Aug 17 06:34:59 PM PDT 24 369215549 ps
T854 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2053419044 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:52 PM PDT 24 745694447 ps
T855 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1587302036 Aug 17 06:34:54 PM PDT 24 Aug 17 06:35:02 PM PDT 24 4992024300 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.885514747 Aug 17 06:35:04 PM PDT 24 Aug 17 06:35:05 PM PDT 24 642275127 ps
T857 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.667006779 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 350304057 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4050957038 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:52 PM PDT 24 397206566 ps
T859 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4221746289 Aug 17 06:34:52 PM PDT 24 Aug 17 06:34:54 PM PDT 24 508531753 ps
T139 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3663876323 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:45 PM PDT 24 1133949045 ps
T860 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.65504206 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:58 PM PDT 24 555499907 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1655283923 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:58 PM PDT 24 508504820 ps
T862 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3488354172 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:54 PM PDT 24 395676159 ps
T863 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4239746869 Aug 17 06:35:04 PM PDT 24 Aug 17 06:35:05 PM PDT 24 428152433 ps
T864 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4096550278 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:01 PM PDT 24 5684273281 ps
T865 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1838208447 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:56 PM PDT 24 354090367 ps
T866 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.945937232 Aug 17 06:35:02 PM PDT 24 Aug 17 06:35:03 PM PDT 24 352271604 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.463430720 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:52 PM PDT 24 2384788230 ps
T868 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1009380289 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:00 PM PDT 24 415881917 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1464239074 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:58 PM PDT 24 756556755 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.758712715 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:05 PM PDT 24 4954699434 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1784791409 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:54 PM PDT 24 688406050 ps
T872 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.611197518 Aug 17 06:34:49 PM PDT 24 Aug 17 06:34:55 PM PDT 24 1214748212 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3765336362 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:57 PM PDT 24 547116587 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3169084278 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:57 PM PDT 24 920959839 ps
T140 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1164201876 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:52 PM PDT 24 351545157 ps
T875 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3439733906 Aug 17 06:35:23 PM PDT 24 Aug 17 06:35:24 PM PDT 24 319414676 ps
T876 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3168650622 Aug 17 06:34:58 PM PDT 24 Aug 17 06:35:19 PM PDT 24 8397562075 ps
T877 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1488800257 Aug 17 06:35:06 PM PDT 24 Aug 17 06:35:07 PM PDT 24 465518586 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2275097951 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:12 PM PDT 24 4729936689 ps
T879 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1680371509 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:55 PM PDT 24 380057304 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4217634184 Aug 17 06:34:53 PM PDT 24 Aug 17 06:35:01 PM PDT 24 8801545756 ps
T881 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2788850285 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:02 PM PDT 24 481652273 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1847927401 Aug 17 06:35:11 PM PDT 24 Aug 17 06:35:12 PM PDT 24 556596831 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1863095422 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:56 PM PDT 24 664637786 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1536933092 Aug 17 06:34:44 PM PDT 24 Aug 17 06:34:46 PM PDT 24 575260694 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2612742176 Aug 17 06:34:59 PM PDT 24 Aug 17 06:35:11 PM PDT 24 5109376993 ps
T886 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2024765011 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:52 PM PDT 24 1194239589 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2081601724 Aug 17 06:34:56 PM PDT 24 Aug 17 06:35:18 PM PDT 24 8766726610 ps
T888 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3221704320 Aug 17 06:35:19 PM PDT 24 Aug 17 06:35:20 PM PDT 24 545314477 ps
T889 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1322793952 Aug 17 06:34:56 PM PDT 24 Aug 17 06:35:01 PM PDT 24 2936431316 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2879468185 Aug 17 06:34:51 PM PDT 24 Aug 17 06:35:52 PM PDT 24 26778448903 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1423250007 Aug 17 06:34:58 PM PDT 24 Aug 17 06:35:00 PM PDT 24 327810100 ps
T892 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.680930857 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:51 PM PDT 24 392475437 ps
T893 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2754711571 Aug 17 06:34:55 PM PDT 24 Aug 17 06:34:56 PM PDT 24 482267099 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2269387961 Aug 17 06:34:54 PM PDT 24 Aug 17 06:34:56 PM PDT 24 554374394 ps
T895 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3359628137 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:57 PM PDT 24 2490508270 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.257881570 Aug 17 06:34:43 PM PDT 24 Aug 17 06:35:04 PM PDT 24 4513715446 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.337667036 Aug 17 06:35:04 PM PDT 24 Aug 17 06:35:06 PM PDT 24 1924117650 ps
T898 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1767785517 Aug 17 06:34:58 PM PDT 24 Aug 17 06:34:59 PM PDT 24 326097208 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2873681912 Aug 17 06:34:42 PM PDT 24 Aug 17 06:34:46 PM PDT 24 501410197 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.787708695 Aug 17 06:34:53 PM PDT 24 Aug 17 06:34:56 PM PDT 24 602374290 ps
T901 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3867840136 Aug 17 06:34:37 PM PDT 24 Aug 17 06:34:39 PM PDT 24 876337671 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.216024561 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:10 PM PDT 24 362193795 ps
T903 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3490548254 Aug 17 06:35:03 PM PDT 24 Aug 17 06:35:05 PM PDT 24 427435287 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2192631580 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:54 PM PDT 24 4078173907 ps
T905 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.270606970 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:54 PM PDT 24 5260294029 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3768869417 Aug 17 06:34:48 PM PDT 24 Aug 17 06:34:49 PM PDT 24 776300104 ps
T907 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.541947664 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:13 PM PDT 24 4625493410 ps
T908 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3645202083 Aug 17 06:34:46 PM PDT 24 Aug 17 06:34:48 PM PDT 24 405635564 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3212904597 Aug 17 06:35:01 PM PDT 24 Aug 17 06:35:04 PM PDT 24 485006823 ps
T141 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1046121215 Aug 17 06:34:50 PM PDT 24 Aug 17 06:34:52 PM PDT 24 1107924830 ps
T910 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2953118629 Aug 17 06:35:00 PM PDT 24 Aug 17 06:35:02 PM PDT 24 417824305 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2194405933 Aug 17 06:34:58 PM PDT 24 Aug 17 06:35:00 PM PDT 24 466418191 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2763517637 Aug 17 06:35:09 PM PDT 24 Aug 17 06:35:11 PM PDT 24 496426696 ps
T913 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2036945770 Aug 17 06:34:40 PM PDT 24 Aug 17 06:34:43 PM PDT 24 634488057 ps
T914 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.361900305 Aug 17 06:35:10 PM PDT 24 Aug 17 06:35:11 PM PDT 24 549620535 ps
T142 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.38562639 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:52 PM PDT 24 1108954981 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2089339665 Aug 17 06:35:23 PM PDT 24 Aug 17 06:35:25 PM PDT 24 2604577166 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2938852034 Aug 17 06:34:51 PM PDT 24 Aug 17 06:34:52 PM PDT 24 533731888 ps
T917 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3233103539 Aug 17 06:34:57 PM PDT 24 Aug 17 06:34:58 PM PDT 24 2381587599 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3403998475 Aug 17 06:34:53 PM PDT 24 Aug 17 06:35:15 PM PDT 24 9054343530 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1757720953 Aug 17 06:34:56 PM PDT 24 Aug 17 06:34:57 PM PDT 24 370757288 ps
T920 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2201880883 Aug 17 06:34:45 PM PDT 24 Aug 17 06:34:47 PM PDT 24 428355785 ps

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.870579013
Short name T7
Test name
Test status
Simulation time 577044280047 ps
CPU time 86.22 seconds
Started Aug 17 05:31:55 PM PDT 24
Finished Aug 17 05:33:21 PM PDT 24
Peak memory 202136 kb
Host smart-da8fc03f-7e7d-49bf-bd92-719f0840abc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870579013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
870579013
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1152331021
Short name T66
Test name
Test status
Simulation time 271234907815 ps
CPU time 481.27 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:36:09 PM PDT 24
Peak memory 212624 kb
Host smart-40237ba3-c522-4cc5-9bf5-7f19a536309e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152331021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1152331021
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1973843630
Short name T43
Test name
Test status
Simulation time 1340077496738 ps
CPU time 52.71 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:29:37 PM PDT 24
Peak memory 210748 kb
Host smart-b037ff95-5b35-49f9-b768-9fa5ba831c63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973843630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1973843630
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3367150759
Short name T52
Test name
Test status
Simulation time 497429421515 ps
CPU time 78.68 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:29:58 PM PDT 24
Peak memory 202080 kb
Host smart-c373dc85-964e-4f78-82b5-a1cb3b35c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367150759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3367150759
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1112392239
Short name T11
Test name
Test status
Simulation time 491237387315 ps
CPU time 225.77 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:32:10 PM PDT 24
Peak memory 202136 kb
Host smart-ca3f41ad-18f5-44df-a8ee-e16327be8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112392239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1112392239
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3163570837
Short name T13
Test name
Test status
Simulation time 7674749422 ps
CPU time 20.51 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:29:00 PM PDT 24
Peak memory 210716 kb
Host smart-ddfafbb6-ecd3-44d5-809d-425bc165a4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163570837 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3163570837
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4182414178
Short name T189
Test name
Test status
Simulation time 525445334420 ps
CPU time 307.03 seconds
Started Aug 17 05:31:03 PM PDT 24
Finished Aug 17 05:36:10 PM PDT 24
Peak memory 202160 kb
Host smart-f5daa900-030c-40a0-ab4b-91e70535cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182414178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4182414178
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.262008171
Short name T147
Test name
Test status
Simulation time 503536242969 ps
CPU time 1129.96 seconds
Started Aug 17 05:30:19 PM PDT 24
Finished Aug 17 05:49:09 PM PDT 24
Peak memory 202164 kb
Host smart-0afe23fa-9680-4037-8154-49a51598397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262008171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.262008171
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1340615496
Short name T180
Test name
Test status
Simulation time 528639861807 ps
CPU time 299.63 seconds
Started Aug 17 05:29:44 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 202008 kb
Host smart-ff7ba2a3-4d18-4b79-8b59-f9146d22a578
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340615496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1340615496
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.468685616
Short name T41
Test name
Test status
Simulation time 537690755786 ps
CPU time 317.93 seconds
Started Aug 17 05:28:31 PM PDT 24
Finished Aug 17 05:33:49 PM PDT 24
Peak memory 202148 kb
Host smart-631babd7-3a6f-4c33-8bd2-84491e7b00fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468685616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.468685616
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.564855395
Short name T229
Test name
Test status
Simulation time 549246101003 ps
CPU time 1283.06 seconds
Started Aug 17 05:31:23 PM PDT 24
Finished Aug 17 05:52:46 PM PDT 24
Peak memory 202124 kb
Host smart-a266c252-e82c-4d11-a01d-0f898d257d0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564855395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.564855395
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3071980294
Short name T77
Test name
Test status
Simulation time 979259633 ps
CPU time 2.78 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 210440 kb
Host smart-d0882fec-7fd9-4210-bb4d-5942237fc159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071980294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3071980294
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3997893194
Short name T79
Test name
Test status
Simulation time 7577667577 ps
CPU time 9.98 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:28:04 PM PDT 24
Peak memory 217476 kb
Host smart-55460c1a-c4e0-4645-9818-8b4eb72750f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997893194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3997893194
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1162307953
Short name T173
Test name
Test status
Simulation time 654679235114 ps
CPU time 284.08 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:33:54 PM PDT 24
Peak memory 202128 kb
Host smart-6c039233-1f58-44f1-9987-4379e9e08764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162307953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1162307953
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2523967173
Short name T6
Test name
Test status
Simulation time 403591839643 ps
CPU time 217.97 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:32:17 PM PDT 24
Peak memory 202108 kb
Host smart-a13ea6cc-b1c3-4da4-b34c-a5feef1aeba1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523967173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2523967173
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.359276154
Short name T254
Test name
Test status
Simulation time 495515630210 ps
CPU time 276.49 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:35:32 PM PDT 24
Peak memory 202176 kb
Host smart-1b134bb0-6cc4-4c14-ab66-b90f0cc29862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359276154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.359276154
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4238465475
Short name T157
Test name
Test status
Simulation time 535316327792 ps
CPU time 195.85 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:31:16 PM PDT 24
Peak memory 202124 kb
Host smart-948b8e3d-ea08-4d9a-b491-cc3ec63affdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238465475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4238465475
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.902181906
Short name T133
Test name
Test status
Simulation time 32909258698 ps
CPU time 12.64 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 201144 kb
Host smart-20b7db35-a8de-4c8e-8876-1b7d467b3287
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902181906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.902181906
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2603062476
Short name T168
Test name
Test status
Simulation time 539913485641 ps
CPU time 80.88 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:30:08 PM PDT 24
Peak memory 202156 kb
Host smart-3573b6d5-8867-4dc8-a96a-d03ff3a842b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603062476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2603062476
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.291159277
Short name T23
Test name
Test status
Simulation time 496873851402 ps
CPU time 180.69 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:30:52 PM PDT 24
Peak memory 202116 kb
Host smart-0f45ae4f-e889-46ac-beec-afbe4cda051d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291159277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.291159277
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3575133413
Short name T176
Test name
Test status
Simulation time 367374767045 ps
CPU time 224.12 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:33:22 PM PDT 24
Peak memory 202176 kb
Host smart-654424f5-af14-4d76-91dd-330c8d71d369
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575133413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3575133413
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3069981594
Short name T238
Test name
Test status
Simulation time 689731305919 ps
CPU time 1493.63 seconds
Started Aug 17 05:30:15 PM PDT 24
Finished Aug 17 05:55:09 PM PDT 24
Peak memory 202068 kb
Host smart-b00d9db0-b553-4150-a00d-2cef88487e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069981594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3069981594
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1094003313
Short name T234
Test name
Test status
Simulation time 535439522381 ps
CPU time 1190.58 seconds
Started Aug 17 05:31:03 PM PDT 24
Finished Aug 17 05:50:53 PM PDT 24
Peak memory 202092 kb
Host smart-9981b2b5-b815-4bc9-b2b0-67009790df5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094003313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1094003313
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2710493604
Short name T45
Test name
Test status
Simulation time 24157383927 ps
CPU time 21.28 seconds
Started Aug 17 05:29:01 PM PDT 24
Finished Aug 17 05:29:22 PM PDT 24
Peak memory 210436 kb
Host smart-23998ba6-58b4-44e1-88f5-241808b9c16b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710493604 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2710493604
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2081162755
Short name T166
Test name
Test status
Simulation time 347244427469 ps
CPU time 196.31 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:31:29 PM PDT 24
Peak memory 202088 kb
Host smart-757f9ad1-66e9-46cf-abc9-3efba04e1e10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081162755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2081162755
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1107940593
Short name T245
Test name
Test status
Simulation time 329541381883 ps
CPU time 747.74 seconds
Started Aug 17 05:28:28 PM PDT 24
Finished Aug 17 05:40:56 PM PDT 24
Peak memory 202120 kb
Host smart-7b638fa7-c3a2-48c3-b339-a6ab5f388b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107940593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1107940593
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.705552261
Short name T270
Test name
Test status
Simulation time 350382712431 ps
CPU time 141.75 seconds
Started Aug 17 05:28:02 PM PDT 24
Finished Aug 17 05:30:24 PM PDT 24
Peak memory 202108 kb
Host smart-e984839f-4f2e-4fdb-93db-63435c78995f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705552261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.705552261
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.298753497
Short name T247
Test name
Test status
Simulation time 511651893315 ps
CPU time 318.21 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:33:22 PM PDT 24
Peak memory 202116 kb
Host smart-b11c5994-fec1-4bfe-a140-cd109bdad6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298753497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.298753497
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3888847275
Short name T5
Test name
Test status
Simulation time 323902342991 ps
CPU time 699.42 seconds
Started Aug 17 05:28:42 PM PDT 24
Finished Aug 17 05:40:22 PM PDT 24
Peak memory 202120 kb
Host smart-adf6edf0-6ee3-424c-949a-0bbdd6814f74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888847275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3888847275
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1617226475
Short name T42
Test name
Test status
Simulation time 474464160 ps
CPU time 1.67 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:28:06 PM PDT 24
Peak memory 201972 kb
Host smart-abb39162-6882-48b5-8285-9b244bfb378e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617226475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1617226475
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4285451844
Short name T316
Test name
Test status
Simulation time 547388940572 ps
CPU time 309.86 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:33:58 PM PDT 24
Peak memory 202116 kb
Host smart-21acc200-9200-4408-ad2a-e1514d155cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285451844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4285451844
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3010615050
Short name T150
Test name
Test status
Simulation time 490646680672 ps
CPU time 1064.73 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:48:38 PM PDT 24
Peak memory 202084 kb
Host smart-c21be53b-229d-4219-ab20-c6b5b43c5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010615050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3010615050
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1014289745
Short name T825
Test name
Test status
Simulation time 8722790226 ps
CPU time 8.69 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 201124 kb
Host smart-54439d71-bc07-47cf-927a-f62d61845432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014289745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1014289745
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.4134446538
Short name T301
Test name
Test status
Simulation time 372512992762 ps
CPU time 459.76 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:35:57 PM PDT 24
Peak memory 202184 kb
Host smart-ef479aa0-b5b8-4325-9ae6-a7693e0c6f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134446538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4134446538
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1654799399
Short name T311
Test name
Test status
Simulation time 507059838206 ps
CPU time 1115.11 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:47:24 PM PDT 24
Peak memory 201904 kb
Host smart-1eb526cf-b5ad-4bf5-a73d-a1ed1bfd0fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654799399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1654799399
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.386908640
Short name T271
Test name
Test status
Simulation time 450213806875 ps
CPU time 999.12 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:46:11 PM PDT 24
Peak memory 202136 kb
Host smart-9a70e41c-b972-4243-970c-f29eeae45569
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386908640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.386908640
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.551866989
Short name T215
Test name
Test status
Simulation time 438120241676 ps
CPU time 1148.48 seconds
Started Aug 17 05:29:33 PM PDT 24
Finished Aug 17 05:48:41 PM PDT 24
Peak memory 202396 kb
Host smart-44b69e27-729c-438e-b508-e24c584d2dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551866989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
551866989
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3720854188
Short name T70
Test name
Test status
Simulation time 463645492666 ps
CPU time 1270.38 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:49:18 PM PDT 24
Peak memory 202288 kb
Host smart-ab85dd26-5f54-47fe-84bf-31cfd97485a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720854188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3720854188
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2851040225
Short name T244
Test name
Test status
Simulation time 242479009045 ps
CPU time 89.25 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:29:28 PM PDT 24
Peak memory 202092 kb
Host smart-b23d26f6-36ba-4f0a-9fb0-ffb963077217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851040225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2851040225
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.360798252
Short name T275
Test name
Test status
Simulation time 536999626843 ps
CPU time 316.18 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 202036 kb
Host smart-16d33e81-2a9c-4d25-adfd-052efd462509
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360798252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.360798252
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.217655265
Short name T227
Test name
Test status
Simulation time 494938059206 ps
CPU time 1124.97 seconds
Started Aug 17 05:30:34 PM PDT 24
Finished Aug 17 05:49:19 PM PDT 24
Peak memory 202060 kb
Host smart-7ed85cb8-fac4-4796-99ee-3fdd36380bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217655265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.217655265
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3974809681
Short name T17
Test name
Test status
Simulation time 15664138841 ps
CPU time 18.43 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:29:01 PM PDT 24
Peak memory 210684 kb
Host smart-186a0d85-33e3-4d44-bba6-4edbb869836b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974809681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3974809681
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.197171927
Short name T264
Test name
Test status
Simulation time 498267540690 ps
CPU time 1154.44 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:47:24 PM PDT 24
Peak memory 202120 kb
Host smart-13888988-5fd8-4eda-b90a-014b159afcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197171927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.197171927
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.398762844
Short name T145
Test name
Test status
Simulation time 2697202757 ps
CPU time 1.82 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 200944 kb
Host smart-85f801f0-482b-4b07-8b1d-e58bd58bf8a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398762844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.398762844
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2189319462
Short name T212
Test name
Test status
Simulation time 133047676345 ps
CPU time 689.19 seconds
Started Aug 17 05:28:32 PM PDT 24
Finished Aug 17 05:40:01 PM PDT 24
Peak memory 202364 kb
Host smart-8c8d5f10-b68a-41a9-8a15-0188e771625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189319462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2189319462
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.684495169
Short name T148
Test name
Test status
Simulation time 63162923461 ps
CPU time 23.12 seconds
Started Aug 17 05:30:09 PM PDT 24
Finished Aug 17 05:30:32 PM PDT 24
Peak memory 201968 kb
Host smart-497de0fc-d1b7-46ae-a998-83d0ad591c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684495169 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.684495169
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2349853425
Short name T240
Test name
Test status
Simulation time 231911527792 ps
CPU time 496.06 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:36:30 PM PDT 24
Peak memory 202084 kb
Host smart-06b1e906-2bf2-48b4-bb4c-d39967e2ff23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349853425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2349853425
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1608987786
Short name T201
Test name
Test status
Simulation time 337347211310 ps
CPU time 367.14 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:35:03 PM PDT 24
Peak memory 202132 kb
Host smart-c7b90823-8819-4755-9fe0-d99a740d0622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608987786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1608987786
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2254888627
Short name T315
Test name
Test status
Simulation time 391913055778 ps
CPU time 864.58 seconds
Started Aug 17 05:29:34 PM PDT 24
Finished Aug 17 05:43:59 PM PDT 24
Peak memory 201532 kb
Host smart-82390d34-6a2a-41a4-84eb-4d35d5d69e65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254888627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2254888627
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3196383681
Short name T169
Test name
Test status
Simulation time 330585299533 ps
CPU time 199.93 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:31:30 PM PDT 24
Peak memory 202148 kb
Host smart-91788e7a-dcf1-4059-922a-6f9396a3fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196383681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3196383681
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.782430939
Short name T223
Test name
Test status
Simulation time 17354078971 ps
CPU time 15.18 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:32 PM PDT 24
Peak memory 210728 kb
Host smart-514e12b3-0f69-4f83-a67c-c2e5eb362edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782430939 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.782430939
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2184209271
Short name T248
Test name
Test status
Simulation time 530678355270 ps
CPU time 1151.23 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:47:17 PM PDT 24
Peak memory 202108 kb
Host smart-7a2f69f3-e623-4d2e-9bbb-415e2d055357
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184209271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2184209271
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3795076203
Short name T567
Test name
Test status
Simulation time 574499971959 ps
CPU time 1023.85 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:46:30 PM PDT 24
Peak memory 210556 kb
Host smart-fe1fee6d-80f5-4bc2-bf5d-12ecf84fe50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795076203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3795076203
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3902826905
Short name T325
Test name
Test status
Simulation time 377210627218 ps
CPU time 212.03 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:31:45 PM PDT 24
Peak memory 202100 kb
Host smart-32c13064-3c95-4d78-b853-51ae1047d008
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902826905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3902826905
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.26836840
Short name T88
Test name
Test status
Simulation time 460256879 ps
CPU time 2.86 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 209384 kb
Host smart-ea9434e9-e968-4281-b577-f4de687a17d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.26836840
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2764286872
Short name T281
Test name
Test status
Simulation time 182942694892 ps
CPU time 216.69 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:31:51 PM PDT 24
Peak memory 202052 kb
Host smart-0164a963-50bb-4675-88d9-316ec54b0e71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764286872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2764286872
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.360364306
Short name T251
Test name
Test status
Simulation time 502533487864 ps
CPU time 245.01 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:32:43 PM PDT 24
Peak memory 202196 kb
Host smart-ef800708-ef4c-4a9f-b8c5-1d92ca97d72a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360364306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.360364306
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1600671119
Short name T291
Test name
Test status
Simulation time 348714718590 ps
CPU time 791.7 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:42:22 PM PDT 24
Peak memory 202136 kb
Host smart-868cce6a-a56e-4b03-8b53-2e498be3f17e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600671119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1600671119
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2991163323
Short name T219
Test name
Test status
Simulation time 309990012576 ps
CPU time 710.21 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:42:43 PM PDT 24
Peak memory 202432 kb
Host smart-7cf6aaf3-6d96-4e69-a9ce-62606c93ef49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991163323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2991163323
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2546893226
Short name T89
Test name
Test status
Simulation time 8886496981 ps
CPU time 17.14 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 201172 kb
Host smart-e724027f-eaed-4e2b-b401-e71a1e565b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546893226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2546893226
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.372040587
Short name T62
Test name
Test status
Simulation time 358074064677 ps
CPU time 760.24 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:40:57 PM PDT 24
Peak memory 202084 kb
Host smart-6265095c-80a1-4ac7-a956-eba023c93f1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372040587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.372040587
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.311361253
Short name T15
Test name
Test status
Simulation time 69844037167 ps
CPU time 15.64 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:28:34 PM PDT 24
Peak memory 218676 kb
Host smart-99b3efe2-c538-412b-95d9-e12f858a27ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311361253 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.311361253
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.97230123
Short name T179
Test name
Test status
Simulation time 355348636331 ps
CPU time 231.72 seconds
Started Aug 17 05:28:23 PM PDT 24
Finished Aug 17 05:32:15 PM PDT 24
Peak memory 202072 kb
Host smart-7c9d4595-cbaa-4c0c-b783-08e218975044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97230123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.97230123
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3795951482
Short name T306
Test name
Test status
Simulation time 491164508422 ps
CPU time 1073.98 seconds
Started Aug 17 05:28:37 PM PDT 24
Finished Aug 17 05:46:31 PM PDT 24
Peak memory 202120 kb
Host smart-52f38eee-e567-4c4d-899c-f521a3590749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795951482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3795951482
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.365493619
Short name T682
Test name
Test status
Simulation time 127695293979 ps
CPU time 460.61 seconds
Started Aug 17 05:28:42 PM PDT 24
Finished Aug 17 05:36:23 PM PDT 24
Peak memory 202264 kb
Host smart-3d014670-a804-4fe2-8ed1-3e5b2c21e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365493619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.365493619
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.956147305
Short name T187
Test name
Test status
Simulation time 199754587987 ps
CPU time 82.22 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:30:18 PM PDT 24
Peak memory 202128 kb
Host smart-b229a675-bacd-4841-8e65-0ec1570410af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956147305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.956147305
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.626777038
Short name T262
Test name
Test status
Simulation time 168292551058 ps
CPU time 266.08 seconds
Started Aug 17 05:29:08 PM PDT 24
Finished Aug 17 05:33:34 PM PDT 24
Peak memory 202100 kb
Host smart-de316296-390b-4008-a144-13565e2a1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626777038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.626777038
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.981586075
Short name T268
Test name
Test status
Simulation time 493285460831 ps
CPU time 1143.09 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:47:06 PM PDT 24
Peak memory 202116 kb
Host smart-a078a914-49d8-4760-ac3c-4df27fc0bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981586075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.981586075
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3364060054
Short name T192
Test name
Test status
Simulation time 338362591723 ps
CPU time 164.08 seconds
Started Aug 17 05:29:37 PM PDT 24
Finished Aug 17 05:32:21 PM PDT 24
Peak memory 202152 kb
Host smart-54925cb5-ca69-47df-8417-1c73754bf692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364060054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3364060054
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1257791252
Short name T250
Test name
Test status
Simulation time 164415114384 ps
CPU time 114.47 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:30:11 PM PDT 24
Peak memory 202120 kb
Host smart-d18f74d9-8979-423c-8ead-33133a685fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257791252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1257791252
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3000240949
Short name T330
Test name
Test status
Simulation time 354502888176 ps
CPU time 211.11 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:31:32 PM PDT 24
Peak memory 202048 kb
Host smart-4892e68b-5ea9-4c6f-b8c8-0a30e4f7fb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000240949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3000240949
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.661772925
Short name T286
Test name
Test status
Simulation time 580027651519 ps
CPU time 162.75 seconds
Started Aug 17 05:28:41 PM PDT 24
Finished Aug 17 05:31:23 PM PDT 24
Peak memory 202148 kb
Host smart-afa74e9d-f3ec-4db9-8351-9dfa7662b152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661772925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.661772925
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.525265059
Short name T253
Test name
Test status
Simulation time 526597539920 ps
CPU time 498.19 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:37:14 PM PDT 24
Peak memory 202128 kb
Host smart-029eb5f1-759b-4c3d-a545-0234328f5b39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525265059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.525265059
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3483629014
Short name T213
Test name
Test status
Simulation time 119849312217 ps
CPU time 393.93 seconds
Started Aug 17 05:28:59 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 202424 kb
Host smart-8d6cc6c7-60a6-4089-97aa-3f15a900751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483629014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3483629014
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3815598620
Short name T57
Test name
Test status
Simulation time 422805352621 ps
CPU time 234.04 seconds
Started Aug 17 05:29:31 PM PDT 24
Finished Aug 17 05:33:26 PM PDT 24
Peak memory 202112 kb
Host smart-09a0ecc8-967c-4fa6-a530-8ae9c0093436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815598620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3815598620
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.736328202
Short name T255
Test name
Test status
Simulation time 331739057244 ps
CPU time 745.85 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:42:04 PM PDT 24
Peak memory 202132 kb
Host smart-d0b265c8-5108-448f-8116-4b8749863875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736328202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.736328202
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2661836964
Short name T231
Test name
Test status
Simulation time 493053868101 ps
CPU time 1117.31 seconds
Started Aug 17 05:29:51 PM PDT 24
Finished Aug 17 05:48:29 PM PDT 24
Peak memory 202068 kb
Host smart-78f283ca-618e-4047-b8a4-8f41e8481c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661836964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2661836964
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2446238017
Short name T339
Test name
Test status
Simulation time 162834478433 ps
CPU time 127.17 seconds
Started Aug 17 05:30:20 PM PDT 24
Finished Aug 17 05:32:28 PM PDT 24
Peak memory 202140 kb
Host smart-e649bc1b-9d82-4783-8de2-695b1d6b1fbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446238017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2446238017
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2240086842
Short name T214
Test name
Test status
Simulation time 120241257757 ps
CPU time 500.67 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:36:24 PM PDT 24
Peak memory 202352 kb
Host smart-ac0e311a-97de-4f15-a926-c58e641d4d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240086842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2240086842
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3143073592
Short name T310
Test name
Test status
Simulation time 565191537922 ps
CPU time 21.63 seconds
Started Aug 17 05:31:01 PM PDT 24
Finished Aug 17 05:31:23 PM PDT 24
Peak memory 210680 kb
Host smart-d50c9a3a-6492-49fa-b251-b722b6653bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143073592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3143073592
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4125006915
Short name T131
Test name
Test status
Simulation time 891212505 ps
CPU time 4.27 seconds
Started Aug 17 06:34:44 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 201152 kb
Host smart-eba0a00d-f66c-4b54-ad8c-aabccb738d1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125006915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.4125006915
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3448244105
Short name T850
Test name
Test status
Simulation time 53391557120 ps
CPU time 177.52 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 201188 kb
Host smart-22822bc0-2c24-48d2-afaf-b95e944d4bc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448244105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3448244105
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3768869417
Short name T906
Test name
Test status
Simulation time 776300104 ps
CPU time 1.14 seconds
Started Aug 17 06:34:48 PM PDT 24
Finished Aug 17 06:34:49 PM PDT 24
Peak memory 200928 kb
Host smart-b021c41b-ed4d-463a-9f0c-efaf034489f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768869417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3768869417
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3672897614
Short name T802
Test name
Test status
Simulation time 427335176 ps
CPU time 1.17 seconds
Started Aug 17 06:34:35 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 201032 kb
Host smart-eb6c7402-2340-487c-9db8-d88916b3379f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672897614 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3672897614
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1843907959
Short name T830
Test name
Test status
Simulation time 592745113 ps
CPU time 1.11 seconds
Started Aug 17 06:34:32 PM PDT 24
Finished Aug 17 06:34:34 PM PDT 24
Peak memory 200968 kb
Host smart-45db4c47-8b6e-4b6f-a429-3a0898948d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843907959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1843907959
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1736912319
Short name T823
Test name
Test status
Simulation time 458706538 ps
CPU time 1.72 seconds
Started Aug 17 06:34:41 PM PDT 24
Finished Aug 17 06:34:43 PM PDT 24
Peak memory 200912 kb
Host smart-d3b83617-b8a5-44c3-a5e2-4f6c0025cdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736912319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1736912319
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.257881570
Short name T896
Test name
Test status
Simulation time 4513715446 ps
CPU time 16.37 seconds
Started Aug 17 06:34:43 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 201184 kb
Host smart-8fc4f0a3-06b5-4f0a-8029-d476d6116466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257881570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.257881570
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2036945770
Short name T913
Test name
Test status
Simulation time 634488057 ps
CPU time 3.46 seconds
Started Aug 17 06:34:40 PM PDT 24
Finished Aug 17 06:34:43 PM PDT 24
Peak memory 201156 kb
Host smart-256b49ec-e048-4c1c-a520-202c04498dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036945770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2036945770
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3520049334
Short name T345
Test name
Test status
Simulation time 4382802655 ps
CPU time 6.32 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:49 PM PDT 24
Peak memory 201180 kb
Host smart-6e0620b1-a0cd-4008-beed-ce64f479df83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520049334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3520049334
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1261791619
Short name T852
Test name
Test status
Simulation time 1457580390 ps
CPU time 3.68 seconds
Started Aug 17 06:34:38 PM PDT 24
Finished Aug 17 06:34:42 PM PDT 24
Peak memory 201164 kb
Host smart-24666ba3-b5a3-4c14-b3cc-2c164a58f542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261791619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1261791619
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2853753764
Short name T138
Test name
Test status
Simulation time 1982905563 ps
CPU time 9.9 seconds
Started Aug 17 06:34:36 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 201156 kb
Host smart-c2c3702f-35e1-40d6-b54e-cfe60013b260
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853753764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2853753764
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3867840136
Short name T901
Test name
Test status
Simulation time 876337671 ps
CPU time 1.68 seconds
Started Aug 17 06:34:37 PM PDT 24
Finished Aug 17 06:34:39 PM PDT 24
Peak memory 200940 kb
Host smart-d4aa7030-e2b5-4986-822f-467959a20102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867840136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3867840136
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3641057593
Short name T812
Test name
Test status
Simulation time 748344580 ps
CPU time 1.16 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201000 kb
Host smart-4da857f9-91db-4d36-8bc1-970d0d452a3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641057593 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3641057593
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1536933092
Short name T884
Test name
Test status
Simulation time 575260694 ps
CPU time 1 seconds
Started Aug 17 06:34:44 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 200872 kb
Host smart-17a2b9ab-46bc-40b2-975c-f6299b12b81d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536933092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1536933092
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1757720953
Short name T919
Test name
Test status
Simulation time 370757288 ps
CPU time 0.72 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200908 kb
Host smart-687e9da1-a082-4a93-8a0c-0f425fbd637d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757720953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1757720953
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2639288595
Short name T836
Test name
Test status
Simulation time 2060870547 ps
CPU time 4.8 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200952 kb
Host smart-48b484a8-948a-43c2-b211-cba67cc95894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639288595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2639288595
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2873681912
Short name T899
Test name
Test status
Simulation time 501410197 ps
CPU time 3.13 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:46 PM PDT 24
Peak memory 217504 kb
Host smart-1a2c3dce-04f9-4493-8eed-41de1dac6847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873681912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2873681912
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3286184268
Short name T840
Test name
Test status
Simulation time 4506459246 ps
CPU time 12.63 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 201220 kb
Host smart-bca811ce-e816-4007-8a97-2525ba827ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286184268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3286184268
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2649060442
Short name T819
Test name
Test status
Simulation time 551454991 ps
CPU time 2.05 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201032 kb
Host smart-04dbc446-a70a-44df-98a1-e3f44965af79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649060442 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2649060442
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.995015332
Short name T827
Test name
Test status
Simulation time 412199377 ps
CPU time 1.72 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 200876 kb
Host smart-202eeada-c9bf-4597-9273-f217a3fb3567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995015332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.995015332
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.586607500
Short name T794
Test name
Test status
Simulation time 412562277 ps
CPU time 1.54 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 200828 kb
Host smart-74a63666-1364-40c9-8c41-b3fd9517bdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586607500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.586607500
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2470529928
Short name T803
Test name
Test status
Simulation time 388188765 ps
CPU time 3 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201184 kb
Host smart-e0e900d5-6c74-416d-8838-12a023df5504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470529928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2470529928
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4096550278
Short name T864
Test name
Test status
Simulation time 5684273281 ps
CPU time 2.19 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201088 kb
Host smart-2421aa05-6e1b-458c-9057-edeb8ae00695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096550278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4096550278
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.680930857
Short name T892
Test name
Test status
Simulation time 392475437 ps
CPU time 1.02 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:51 PM PDT 24
Peak memory 201012 kb
Host smart-427fd8b4-cbdb-45cf-aed9-22b0b8562d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680930857 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.680930857
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.510592744
Short name T134
Test name
Test status
Simulation time 436360343 ps
CPU time 1.1 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 200968 kb
Host smart-95ebca0e-3e4c-458e-8029-3dd66395a003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510592744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.510592744
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3363130684
Short name T846
Test name
Test status
Simulation time 522258574 ps
CPU time 0.91 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200872 kb
Host smart-8fc38d5c-48f2-4524-9dc9-a25737e8690f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363130684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3363130684
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1322793952
Short name T889
Test name
Test status
Simulation time 2936431316 ps
CPU time 4.92 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201148 kb
Host smart-355081ac-5f04-432d-ba81-4c80a19b52c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322793952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1322793952
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1815640916
Short name T807
Test name
Test status
Simulation time 4534718565 ps
CPU time 6.4 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 201188 kb
Host smart-2a8f97f3-938c-44d0-8285-3fdf6af33d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815640916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1815640916
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2194405933
Short name T911
Test name
Test status
Simulation time 466418191 ps
CPU time 1.89 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 201004 kb
Host smart-3543e4bd-68d3-4f06-96df-f9e88fe9fc96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194405933 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2194405933
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.487763114
Short name T835
Test name
Test status
Simulation time 319988609 ps
CPU time 1.4 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 200944 kb
Host smart-fbdb4705-8726-48ec-92fc-44058209caec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487763114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.487763114
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3902730685
Short name T805
Test name
Test status
Simulation time 514626972 ps
CPU time 0.85 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 200848 kb
Host smart-11000242-9bbe-4379-8371-ae04784a9289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902730685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3902730685
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3233103539
Short name T917
Test name
Test status
Simulation time 2381587599 ps
CPU time 1.4 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 201032 kb
Host smart-2518c419-baee-4a8b-b308-2c8af6ca31c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233103539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3233103539
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1989677697
Short name T849
Test name
Test status
Simulation time 556029051 ps
CPU time 2.7 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 201168 kb
Host smart-230f1df3-269a-4c36-abe2-33eabbba9a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989677697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1989677697
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1527523741
Short name T76
Test name
Test status
Simulation time 7819122640 ps
CPU time 12.18 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 201172 kb
Host smart-7cd9acc8-87de-4335-93c0-640b0c977328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527523741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1527523741
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4221746289
Short name T859
Test name
Test status
Simulation time 508531753 ps
CPU time 1.37 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200976 kb
Host smart-628ca906-d97d-4cce-87ed-876278f6d16b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221746289 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4221746289
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2637759110
Short name T132
Test name
Test status
Simulation time 572857096 ps
CPU time 1.14 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 200940 kb
Host smart-6c4bd15e-cac7-45c0-b872-f637465026af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637759110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2637759110
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1335209869
Short name T817
Test name
Test status
Simulation time 496041060 ps
CPU time 1.76 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200872 kb
Host smart-ea646ec2-f75c-48bb-bdfc-ea11f99551a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335209869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1335209869
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1587302036
Short name T855
Test name
Test status
Simulation time 4992024300 ps
CPU time 3.02 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 201204 kb
Host smart-42824a92-ea35-4021-bfe0-0a4bcc1f7a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587302036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1587302036
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1863095422
Short name T883
Test name
Test status
Simulation time 664637786 ps
CPU time 2.53 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201076 kb
Host smart-a3ba47f5-7fad-4dfa-a6cb-2859e29dccce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863095422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1863095422
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2275097951
Short name T878
Test name
Test status
Simulation time 4729936689 ps
CPU time 12.2 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 201144 kb
Host smart-1acd64b9-51eb-48a4-bc75-79caa3d3928f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275097951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2275097951
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456026
Short name T100
Test name
Test status
Simulation time 475186834 ps
CPU time 1.8 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 201032 kb
Host smart-4d079799-ef81-4002-ab0f-e55760981e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117456026 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456026
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3488354172
Short name T862
Test name
Test status
Simulation time 395676159 ps
CPU time 1.17 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200968 kb
Host smart-9b027498-7384-4774-9f4f-36c9eb16d487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488354172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3488354172
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3587049547
Short name T845
Test name
Test status
Simulation time 420619989 ps
CPU time 1.53 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200812 kb
Host smart-7dcfb9cf-2e45-4982-b42a-52d5904be14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587049547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3587049547
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2290196948
Short name T144
Test name
Test status
Simulation time 5357215131 ps
CPU time 13.07 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 201144 kb
Host smart-b75c95fd-b3d7-48e5-ab41-744c7b6af7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290196948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2290196948
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.861999524
Short name T82
Test name
Test status
Simulation time 630828325 ps
CPU time 1.95 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201220 kb
Host smart-f827274b-0891-4b20-b888-46fbb3c61a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861999524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.861999524
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3406049455
Short name T75
Test name
Test status
Simulation time 4736801229 ps
CPU time 4.06 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 201240 kb
Host smart-6ca934ba-3c19-4173-b4b7-7942cb69e97f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406049455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3406049455
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.849043154
Short name T826
Test name
Test status
Simulation time 379410330 ps
CPU time 1.44 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 201024 kb
Host smart-4db69d86-c54d-44a0-b1d6-3d2ea7211d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849043154 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.849043154
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.65504206
Short name T860
Test name
Test status
Simulation time 555499907 ps
CPU time 0.85 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 200812 kb
Host smart-1a86e88f-9f4e-4d58-b05e-5ad14c5a4bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65504206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.65504206
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4047684428
Short name T843
Test name
Test status
Simulation time 374490102 ps
CPU time 1.54 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:59 PM PDT 24
Peak memory 200864 kb
Host smart-6c055075-427b-4cce-a7a4-df777b99e4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047684428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4047684428
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2487944932
Short name T71
Test name
Test status
Simulation time 4053564431 ps
CPU time 13.52 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 201156 kb
Host smart-e34a6653-1835-400c-96ae-883fa4050d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487944932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2487944932
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1009244647
Short name T84
Test name
Test status
Simulation time 741990671 ps
CPU time 2.17 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 201172 kb
Host smart-f79e34a0-e61b-4a26-9830-e4613c0dbeae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009244647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1009244647
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3090813308
Short name T344
Test name
Test status
Simulation time 4148667550 ps
CPU time 3.55 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201216 kb
Host smart-049ae489-cbe9-4afa-b55b-7672ad7a0d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090813308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3090813308
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1059748424
Short name T839
Test name
Test status
Simulation time 374122327 ps
CPU time 1.6 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 201032 kb
Host smart-526f507b-9656-4f3a-b105-8a9eee0d5df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059748424 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1059748424
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1784791409
Short name T871
Test name
Test status
Simulation time 688406050 ps
CPU time 0.89 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200892 kb
Host smart-cc8c00a7-89db-46a2-b583-86a1613b32ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784791409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1784791409
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1690917264
Short name T813
Test name
Test status
Simulation time 358366201 ps
CPU time 1.5 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 200860 kb
Host smart-df69fb0a-c966-4980-a855-e75f661557a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690917264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1690917264
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2612742176
Short name T885
Test name
Test status
Simulation time 5109376993 ps
CPU time 11.46 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 201144 kb
Host smart-8ae9276c-37f7-4356-bf3c-c2a6b2ce8dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612742176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2612742176
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3212904597
Short name T909
Test name
Test status
Simulation time 485006823 ps
CPU time 2.03 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 216996 kb
Host smart-f4e0c3f8-3bd9-4b32-a662-56b5d8fdeb88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212904597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3212904597
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.656704202
Short name T809
Test name
Test status
Simulation time 532800395 ps
CPU time 1.08 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 201060 kb
Host smart-7535a59a-514e-4172-95b8-a538e8c28ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656704202 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.656704202
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1843732972
Short name T129
Test name
Test status
Simulation time 457338331 ps
CPU time 0.89 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 200968 kb
Host smart-65899d31-b426-4de9-b596-482baacfb977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843732972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1843732972
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1851228445
Short name T851
Test name
Test status
Simulation time 505545186 ps
CPU time 1.17 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 200796 kb
Host smart-7faa2164-3ae0-4d8c-a0f6-e900367649b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851228445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1851228445
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.337667036
Short name T897
Test name
Test status
Simulation time 1924117650 ps
CPU time 2.33 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 200940 kb
Host smart-1d3492bd-28aa-48e9-b3c7-c82490c02624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337667036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.337667036
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.787708695
Short name T900
Test name
Test status
Simulation time 602374290 ps
CPU time 3.13 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201160 kb
Host smart-95eedcb6-37dc-49eb-98cf-94df9010b92c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787708695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.787708695
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1032000685
Short name T342
Test name
Test status
Simulation time 5677574081 ps
CPU time 2.92 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 201184 kb
Host smart-a10ee6e1-f242-41c3-adf8-d77edb01c66f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032000685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1032000685
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.885514747
Short name T856
Test name
Test status
Simulation time 642275127 ps
CPU time 0.97 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200992 kb
Host smart-81cc7121-7d7b-47ab-ac49-a5c97c2d64ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885514747 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.885514747
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2236613297
Short name T143
Test name
Test status
Simulation time 542881178 ps
CPU time 1.93 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200968 kb
Host smart-76f96c5a-6c32-4fe0-8c53-b90057c16eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236613297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2236613297
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1892914868
Short name T816
Test name
Test status
Simulation time 307131745 ps
CPU time 0.95 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200864 kb
Host smart-b4e239ed-0be6-48a9-aa05-60f900cc6869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892914868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1892914868
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.541947664
Short name T907
Test name
Test status
Simulation time 4625493410 ps
CPU time 11.44 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 201152 kb
Host smart-b613e446-c784-4ec9-b03b-e58440b40616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541947664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.541947664
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2353198871
Short name T831
Test name
Test status
Simulation time 607720273 ps
CPU time 3.32 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:59 PM PDT 24
Peak memory 201120 kb
Host smart-2d58ebe0-ba42-44c9-aa30-fa9d205be7ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353198871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2353198871
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2208079636
Short name T74
Test name
Test status
Simulation time 8176475307 ps
CPU time 19.55 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:24 PM PDT 24
Peak memory 201128 kb
Host smart-6cfb20cf-9df4-4ff1-858a-56df5bc58355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208079636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2208079636
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2763517637
Short name T912
Test name
Test status
Simulation time 496426696 ps
CPU time 2 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 201044 kb
Host smart-69dabae8-3830-4667-bb12-4bdc4fb784d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763517637 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2763517637
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1145831410
Short name T146
Test name
Test status
Simulation time 420815820 ps
CPU time 1.62 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 200864 kb
Host smart-804846b0-b32c-4f5e-a5c9-ae41f340f676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145831410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1145831410
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3470227259
Short name T796
Test name
Test status
Simulation time 368482948 ps
CPU time 1.51 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 200868 kb
Host smart-38d5bb9b-f5d5-47f9-8611-54c2ca3feaa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470227259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3470227259
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2089339665
Short name T915
Test name
Test status
Simulation time 2604577166 ps
CPU time 1.31 seconds
Started Aug 17 06:35:23 PM PDT 24
Finished Aug 17 06:35:25 PM PDT 24
Peak memory 200988 kb
Host smart-bf4d13dd-db33-43c1-a4b8-45491447355b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089339665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2089339665
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.216024561
Short name T902
Test name
Test status
Simulation time 362193795 ps
CPU time 2.2 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 201184 kb
Host smart-bde0ff3c-85e4-4c32-a9a4-286d23ced599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216024561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.216024561
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3168650622
Short name T876
Test name
Test status
Simulation time 8397562075 ps
CPU time 20.98 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:19 PM PDT 24
Peak memory 201184 kb
Host smart-64c3d9da-e71b-440e-af40-36253c803376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168650622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3168650622
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3663876323
Short name T139
Test name
Test status
Simulation time 1133949045 ps
CPU time 2.95 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 201128 kb
Host smart-bb42e2c1-fbb5-4167-9c19-bdf2d5f37048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663876323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3663876323
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1046121215
Short name T141
Test name
Test status
Simulation time 1107924830 ps
CPU time 1.22 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200936 kb
Host smart-ac3d5b3f-03ca-4689-bc13-b1e089df80a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046121215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1046121215
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3169084278
Short name T874
Test name
Test status
Simulation time 920959839 ps
CPU time 1.5 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 211624 kb
Host smart-1257e0b4-4fbe-48cd-88da-629073918734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169084278 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3169084278
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3567390480
Short name T137
Test name
Test status
Simulation time 331988122 ps
CPU time 1.57 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 200976 kb
Host smart-31cdc02b-cebe-4309-ab01-1987af278179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567390480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3567390480
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2418692064
Short name T837
Test name
Test status
Simulation time 350487782 ps
CPU time 0.86 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200892 kb
Host smart-310bf453-d467-4fcd-9984-62ae1a7f84b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418692064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2418692064
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.758712715
Short name T870
Test name
Test status
Simulation time 4954699434 ps
CPU time 4.36 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 201132 kb
Host smart-58cbd995-04a1-47b1-b3f1-917a15d7b5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758712715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.758712715
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2611395734
Short name T818
Test name
Test status
Simulation time 405705702 ps
CPU time 2.36 seconds
Started Aug 17 06:34:42 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 201176 kb
Host smart-e2e23a1d-730c-432c-b065-d8672c878236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611395734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2611395734
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2905310293
Short name T343
Test name
Test status
Simulation time 8326904682 ps
CPU time 20.9 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 201156 kb
Host smart-a03b099a-2092-4ae2-8709-0878d022c838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905310293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2905310293
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2210485738
Short name T829
Test name
Test status
Simulation time 379552865 ps
CPU time 1.07 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200896 kb
Host smart-9ea272ad-129b-4ee3-b540-79a89a7dc07e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210485738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2210485738
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4239746869
Short name T863
Test name
Test status
Simulation time 428152433 ps
CPU time 0.88 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200768 kb
Host smart-d85f66bb-d3de-42fd-9b06-745335b0c47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239746869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4239746869
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1767785517
Short name T898
Test name
Test status
Simulation time 326097208 ps
CPU time 0.85 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:34:59 PM PDT 24
Peak memory 200828 kb
Host smart-bc7eb019-0477-4cf4-94ed-5b14745698bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767785517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1767785517
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1733966067
Short name T821
Test name
Test status
Simulation time 655624568 ps
CPU time 0.71 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 200828 kb
Host smart-9e3e0ce8-328b-49d7-8c72-610167bb75dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733966067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1733966067
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2147686383
Short name T814
Test name
Test status
Simulation time 491506140 ps
CPU time 0.92 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 200848 kb
Host smart-9f3087df-0e7c-4450-9ba7-bccbe45f48ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147686383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2147686383
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.945937232
Short name T866
Test name
Test status
Simulation time 352271604 ps
CPU time 0.84 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 200832 kb
Host smart-353c7605-425e-4022-8670-88da10033617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945937232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.945937232
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3804873994
Short name T808
Test name
Test status
Simulation time 340743608 ps
CPU time 1.38 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 200896 kb
Host smart-7555bc74-a8a6-4de7-9a28-0c5d9002df09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804873994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3804873994
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1838208447
Short name T865
Test name
Test status
Simulation time 354090367 ps
CPU time 0.9 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 200832 kb
Host smart-b707ae49-eecf-46eb-a7b7-34dccd2d2a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838208447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1838208447
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.648429085
Short name T801
Test name
Test status
Simulation time 365896641 ps
CPU time 1.49 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 200892 kb
Host smart-be729e63-171f-4cf1-8144-cb7f3fef4f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648429085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.648429085
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1087183051
Short name T842
Test name
Test status
Simulation time 525925054 ps
CPU time 1.8 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200768 kb
Host smart-d3a4c2d9-4b7a-40eb-af74-f170d9176fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087183051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1087183051
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.59934299
Short name T844
Test name
Test status
Simulation time 833061846 ps
CPU time 3.02 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201032 kb
Host smart-a1f867be-a749-423e-9dc2-e7b1ba73cb97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59934299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasi
ng.59934299
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2879468185
Short name T890
Test name
Test status
Simulation time 26778448903 ps
CPU time 60.82 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:35:52 PM PDT 24
Peak memory 201200 kb
Host smart-3884ae94-8e3e-4c81-8344-9ef93920568b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879468185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2879468185
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1464239074
Short name T869
Test name
Test status
Simulation time 756556755 ps
CPU time 1.18 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 200932 kb
Host smart-fb6782ca-8471-41e2-adb7-952373c022fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464239074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1464239074
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2393558774
Short name T800
Test name
Test status
Simulation time 592615378 ps
CPU time 1.31 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:50 PM PDT 24
Peak memory 209428 kb
Host smart-3011d9d5-ea99-4011-9aae-721996b2c650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393558774 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2393558774
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2269387961
Short name T894
Test name
Test status
Simulation time 554374394 ps
CPU time 1.92 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 200932 kb
Host smart-66e5e218-5e6a-4e33-991a-85a757751d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269387961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2269387961
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3994096941
Short name T838
Test name
Test status
Simulation time 345348000 ps
CPU time 1.45 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 200828 kb
Host smart-1547c2f3-02dc-45b5-b96f-ed8ad3bddf3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994096941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3994096941
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2192631580
Short name T904
Test name
Test status
Simulation time 4078173907 ps
CPU time 3.43 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 201244 kb
Host smart-539a243a-ddf4-41f4-9aae-2d64ed98c062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192631580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2192631580
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1087492264
Short name T815
Test name
Test status
Simulation time 493912056 ps
CPU time 2.52 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201184 kb
Host smart-9e246a2c-15f9-43c4-adcb-82c61268f7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087492264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1087492264
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4217634184
Short name T880
Test name
Test status
Simulation time 8801545756 ps
CPU time 7.62 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 201204 kb
Host smart-2e51f488-da2e-4347-9c63-7a2ae624be9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217634184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4217634184
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2445172745
Short name T795
Test name
Test status
Simulation time 474665564 ps
CPU time 1.7 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 200852 kb
Host smart-fd8cfa53-27e2-497f-abbd-f0739a2948e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445172745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2445172745
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2861863433
Short name T799
Test name
Test status
Simulation time 336049442 ps
CPU time 1.36 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 200768 kb
Host smart-0b63f8c3-6586-4935-9498-50c009eaf912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861863433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2861863433
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2788850285
Short name T881
Test name
Test status
Simulation time 481652273 ps
CPU time 0.88 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 200784 kb
Host smart-ad559d79-8be9-4097-afb0-89197ecf51a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788850285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2788850285
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1680371509
Short name T879
Test name
Test status
Simulation time 380057304 ps
CPU time 0.73 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 200872 kb
Host smart-e10e9d9b-5af5-4d0a-8120-12208807bf56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680371509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1680371509
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.255437529
Short name T833
Test name
Test status
Simulation time 474130270 ps
CPU time 1.6 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200892 kb
Host smart-d80731f6-5fe8-453d-8934-c8b4dec5fb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255437529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.255437529
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3238637038
Short name T806
Test name
Test status
Simulation time 492305798 ps
CPU time 1.54 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 200872 kb
Host smart-1377cc69-2560-47d4-ae01-fd508a64a0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238637038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3238637038
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3221704320
Short name T888
Test name
Test status
Simulation time 545314477 ps
CPU time 0.95 seconds
Started Aug 17 06:35:19 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 200880 kb
Host smart-83be7938-9237-4267-92d5-74585515631c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221704320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3221704320
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.785825567
Short name T822
Test name
Test status
Simulation time 476547586 ps
CPU time 1.88 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 200896 kb
Host smart-7dc73b3b-689d-4a49-af1b-972ddd5431a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785825567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.785825567
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1488800257
Short name T877
Test name
Test status
Simulation time 465518586 ps
CPU time 0.91 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 200880 kb
Host smart-17cb654b-34df-4eb9-b54b-abddefe63d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488800257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1488800257
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2953118629
Short name T910
Test name
Test status
Simulation time 417824305 ps
CPU time 1.55 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 200872 kb
Host smart-9821e938-8dd4-42ea-af46-86069f84fc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953118629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2953118629
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.611197518
Short name T872
Test name
Test status
Simulation time 1214748212 ps
CPU time 5.54 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 201156 kb
Host smart-90953df1-e6fa-4702-bc82-d289abaa77b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611197518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.611197518
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2542287518
Short name T73
Test name
Test status
Simulation time 19575288188 ps
CPU time 79.75 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 201136 kb
Host smart-4a1a33fb-3a2a-4813-9d15-330b1913eac0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542287518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2542287518
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.38562639
Short name T142
Test name
Test status
Simulation time 1108954981 ps
CPU time 1.32 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200960 kb
Host smart-7c295aa5-389f-48ec-87bf-a2b6ee82b6bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_res
et.38562639
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1655283923
Short name T861
Test name
Test status
Simulation time 508504820 ps
CPU time 1.5 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:34:58 PM PDT 24
Peak memory 201036 kb
Host smart-55440abc-1100-43fb-b969-d278892a18df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655283923 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1655283923
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.825486883
Short name T130
Test name
Test status
Simulation time 370400093 ps
CPU time 0.93 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 200924 kb
Host smart-09d6fe27-50a2-4f68-9443-79134f2fb765
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825486883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.825486883
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2938852034
Short name T916
Test name
Test status
Simulation time 533731888 ps
CPU time 0.93 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200808 kb
Host smart-33d219ce-ebf4-4820-8636-6f9f5d899891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938852034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2938852034
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.270606970
Short name T905
Test name
Test status
Simulation time 5260294029 ps
CPU time 3.78 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:54 PM PDT 24
Peak memory 201176 kb
Host smart-58dd43d4-af1a-42a9-baf3-c331d6695d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270606970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.270606970
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2984109386
Short name T83
Test name
Test status
Simulation time 332991190 ps
CPU time 2.98 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:59 PM PDT 24
Peak memory 217100 kb
Host smart-3c2862c2-3d74-43e8-8320-9d1b69c4a18c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984109386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2984109386
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.718546302
Short name T820
Test name
Test status
Simulation time 4663390080 ps
CPU time 10.89 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 201192 kb
Host smart-8ad34a38-cb4e-4ccd-a813-1cfdff7e683e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718546302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.718546302
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.310813822
Short name T853
Test name
Test status
Simulation time 369215549 ps
CPU time 0.83 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:34:59 PM PDT 24
Peak memory 200888 kb
Host smart-11a65aac-6383-4c4d-bd88-b8a649c89bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310813822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.310813822
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2508124191
Short name T797
Test name
Test status
Simulation time 492105493 ps
CPU time 1.81 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:35:16 PM PDT 24
Peak memory 200880 kb
Host smart-731f30cc-f7c7-4e98-9a37-29d236ec343f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508124191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2508124191
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1009380289
Short name T868
Test name
Test status
Simulation time 415881917 ps
CPU time 0.83 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 200864 kb
Host smart-b92a996f-574e-47a4-a1f8-9f79612a7073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009380289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1009380289
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2895306401
Short name T804
Test name
Test status
Simulation time 374675905 ps
CPU time 0.84 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200844 kb
Host smart-621ac69b-a580-4925-aa2a-0101330fbafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895306401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2895306401
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3439733906
Short name T875
Test name
Test status
Simulation time 319414676 ps
CPU time 1.33 seconds
Started Aug 17 06:35:23 PM PDT 24
Finished Aug 17 06:35:24 PM PDT 24
Peak memory 200884 kb
Host smart-f4686641-5def-46e5-b47b-16c518a1be54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439733906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3439733906
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3490548254
Short name T903
Test name
Test status
Simulation time 427435287 ps
CPU time 1.55 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200880 kb
Host smart-ef96392c-153e-4b77-894c-6f8e7710da4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490548254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3490548254
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.667006779
Short name T857
Test name
Test status
Simulation time 350304057 ps
CPU time 1.47 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 200896 kb
Host smart-24000529-6d72-44ef-aa26-24ae8559ae77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667006779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.667006779
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3994717608
Short name T828
Test name
Test status
Simulation time 418261629 ps
CPU time 1.35 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 200880 kb
Host smart-2e204890-1c00-4427-a4cf-ebd46043c3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994717608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3994717608
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.361900305
Short name T914
Test name
Test status
Simulation time 549620535 ps
CPU time 0.91 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 200852 kb
Host smart-44316f67-7dd5-4d7e-a562-33c714aaee7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361900305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.361900305
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2747052926
Short name T810
Test name
Test status
Simulation time 405322697 ps
CPU time 0.98 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 200884 kb
Host smart-d7fae1f1-8d1b-4b88-86a4-0ced833578ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747052926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2747052926
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.743634461
Short name T834
Test name
Test status
Simulation time 621327762 ps
CPU time 1.51 seconds
Started Aug 17 06:34:48 PM PDT 24
Finished Aug 17 06:34:50 PM PDT 24
Peak memory 200952 kb
Host smart-0f248b1d-7fe0-4be6-a797-8bffd2f09f76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743634461 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.743634461
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1423250007
Short name T891
Test name
Test status
Simulation time 327810100 ps
CPU time 1.5 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 200968 kb
Host smart-6d1d4bc3-faff-4568-b509-93e49178dbe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423250007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1423250007
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2754711571
Short name T893
Test name
Test status
Simulation time 482267099 ps
CPU time 0.78 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 200892 kb
Host smart-a6677b6a-774c-4ff8-a049-a5e24e01996d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754711571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2754711571
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1751404991
Short name T847
Test name
Test status
Simulation time 5063809235 ps
CPU time 2.68 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 201132 kb
Host smart-235b9fae-4347-43dd-bb5a-b03bca641031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751404991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1751404991
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2081601724
Short name T887
Test name
Test status
Simulation time 8766726610 ps
CPU time 21.52 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:18 PM PDT 24
Peak memory 201180 kb
Host smart-20711536-7f0a-4852-91cf-619756370b12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081601724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2081601724
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2030995147
Short name T101
Test name
Test status
Simulation time 762479764 ps
CPU time 1.25 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 201032 kb
Host smart-fc4b7d3d-7456-433f-882a-be1df58f6dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030995147 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2030995147
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2253436046
Short name T848
Test name
Test status
Simulation time 557742573 ps
CPU time 1.31 seconds
Started Aug 17 06:34:48 PM PDT 24
Finished Aug 17 06:34:50 PM PDT 24
Peak memory 200892 kb
Host smart-9b29d39d-4d02-4cb7-b4bd-8ede55ae8e9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253436046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2253436046
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2076352621
Short name T811
Test name
Test status
Simulation time 314577016 ps
CPU time 1.34 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 200908 kb
Host smart-026bc750-082e-4dfa-86fc-4f1fe5510cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076352621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2076352621
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.463430720
Short name T867
Test name
Test status
Simulation time 2384788230 ps
CPU time 5.92 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 201020 kb
Host smart-aeac2d5a-3223-41d1-99b1-89f8150f42f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463430720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.463430720
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4050957038
Short name T858
Test name
Test status
Simulation time 397206566 ps
CPU time 2.95 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 217560 kb
Host smart-ed5e4017-846b-489a-a66a-9ce5bc8a6d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050957038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.4050957038
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3714276104
Short name T87
Test name
Test status
Simulation time 487056187 ps
CPU time 2.07 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 201000 kb
Host smart-76b89b2f-5776-42e4-8f69-02bda7a39a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714276104 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3714276104
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3331605262
Short name T135
Test name
Test status
Simulation time 563190957 ps
CPU time 2.08 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:55 PM PDT 24
Peak memory 200944 kb
Host smart-dcf8ba4f-a796-48f2-b00b-b4055c03b2c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331605262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3331605262
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3760811826
Short name T798
Test name
Test status
Simulation time 433623757 ps
CPU time 1.54 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200836 kb
Host smart-392ed01f-93b9-4b59-a876-5c2ba58507ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760811826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3760811826
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3359628137
Short name T895
Test name
Test status
Simulation time 2490508270 ps
CPU time 6.27 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 201020 kb
Host smart-ff0e5048-ec3a-4aec-bbb8-acb7a49a585c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359628137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3359628137
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3765336362
Short name T873
Test name
Test status
Simulation time 547116587 ps
CPU time 1.55 seconds
Started Aug 17 06:34:55 PM PDT 24
Finished Aug 17 06:34:57 PM PDT 24
Peak memory 201188 kb
Host smart-71906d58-8803-4735-9f98-ae1db4c7c9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765336362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3765336362
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3403998475
Short name T918
Test name
Test status
Simulation time 9054343530 ps
CPU time 22.13 seconds
Started Aug 17 06:34:53 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 201224 kb
Host smart-556d565c-fb3a-4213-974c-1c2a5fc5ad62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403998475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3403998475
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1847927401
Short name T882
Test name
Test status
Simulation time 556596831 ps
CPU time 1.11 seconds
Started Aug 17 06:35:11 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 201064 kb
Host smart-fcea4b4c-d9f0-4c28-9c9f-892843349bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847927401 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1847927401
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3461847113
Short name T136
Test name
Test status
Simulation time 593706131 ps
CPU time 1.14 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 200940 kb
Host smart-1082ec78-cfef-4919-82b5-717e69d9397f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461847113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3461847113
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3665960741
Short name T841
Test name
Test status
Simulation time 546563909 ps
CPU time 0.96 seconds
Started Aug 17 06:34:52 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 200892 kb
Host smart-bed69518-a229-4d39-8d83-cec609afd6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665960741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3665960741
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3573644292
Short name T72
Test name
Test status
Simulation time 2585170693 ps
CPU time 2.42 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:53 PM PDT 24
Peak memory 200992 kb
Host smart-8e1b15da-cedb-4da2-b842-d2003d7a57c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573644292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3573644292
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2053419044
Short name T854
Test name
Test status
Simulation time 745694447 ps
CPU time 2.34 seconds
Started Aug 17 06:34:49 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 201180 kb
Host smart-4c76d547-bfaa-4586-8ba0-3931993d80a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053419044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2053419044
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1423505968
Short name T832
Test name
Test status
Simulation time 8368120178 ps
CPU time 23.18 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:25 PM PDT 24
Peak memory 201164 kb
Host smart-36d4936b-4d9e-4f91-ad93-e48ebb796dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423505968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1423505968
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3645202083
Short name T908
Test name
Test status
Simulation time 405635564 ps
CPU time 1.76 seconds
Started Aug 17 06:34:46 PM PDT 24
Finished Aug 17 06:34:48 PM PDT 24
Peak memory 201032 kb
Host smart-95480c7a-52cf-4052-9c3c-6b4fbc63cef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645202083 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3645202083
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1164201876
Short name T140
Test name
Test status
Simulation time 351545157 ps
CPU time 1.25 seconds
Started Aug 17 06:34:51 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 200968 kb
Host smart-e2c21756-f116-49e1-ad2f-863b5302225a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164201876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1164201876
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2201880883
Short name T920
Test name
Test status
Simulation time 428355785 ps
CPU time 1.2 seconds
Started Aug 17 06:34:45 PM PDT 24
Finished Aug 17 06:34:47 PM PDT 24
Peak memory 200912 kb
Host smart-9a2a1cfe-4a91-41c4-843f-a31e23b07cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201880883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2201880883
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4054789660
Short name T824
Test name
Test status
Simulation time 3857690753 ps
CPU time 2.16 seconds
Started Aug 17 06:34:54 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201144 kb
Host smart-02ab005c-cbfa-4040-b65f-15d9f0d46229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054789660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4054789660
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2024765011
Short name T886
Test name
Test status
Simulation time 1194239589 ps
CPU time 1.86 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:52 PM PDT 24
Peak memory 201216 kb
Host smart-083928a7-b855-454f-8cb5-57379b84bb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024765011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2024765011
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2423902545
Short name T78
Test name
Test status
Simulation time 7952307144 ps
CPU time 6.11 seconds
Started Aug 17 06:34:50 PM PDT 24
Finished Aug 17 06:34:56 PM PDT 24
Peak memory 201224 kb
Host smart-8d5256b2-a07f-47c9-9af2-24b3a3785396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423902545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2423902545
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2640765593
Short name T478
Test name
Test status
Simulation time 337239131144 ps
CPU time 393.73 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:34:40 PM PDT 24
Peak memory 202120 kb
Host smart-a180b6ad-a372-4f3d-a99f-5cda79b7d96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640765593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2640765593
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4002267379
Short name T575
Test name
Test status
Simulation time 496449632701 ps
CPU time 1194.46 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:47:55 PM PDT 24
Peak memory 202092 kb
Host smart-d76f8fa0-6d39-48fe-8420-2b0722bf2e3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002267379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4002267379
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3590347766
Short name T305
Test name
Test status
Simulation time 491033806053 ps
CPU time 1067.99 seconds
Started Aug 17 05:27:44 PM PDT 24
Finished Aug 17 05:45:33 PM PDT 24
Peak memory 202112 kb
Host smart-99c99b31-51f1-47a2-a223-3cdd74fc8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590347766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3590347766
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.125925023
Short name T488
Test name
Test status
Simulation time 486966396301 ps
CPU time 582.86 seconds
Started Aug 17 05:27:57 PM PDT 24
Finished Aug 17 05:37:40 PM PDT 24
Peak memory 202140 kb
Host smart-57fdda56-ec8c-4236-a76b-e6fca5182178
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=125925023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.125925023
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1547804755
Short name T482
Test name
Test status
Simulation time 597591962122 ps
CPU time 364.49 seconds
Started Aug 17 05:27:47 PM PDT 24
Finished Aug 17 05:33:51 PM PDT 24
Peak memory 202160 kb
Host smart-020cebaa-3b5b-47b6-8754-ceca8cab2a6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547804755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1547804755
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1183653107
Short name T206
Test name
Test status
Simulation time 81365517705 ps
CPU time 277.73 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:32:41 PM PDT 24
Peak memory 202320 kb
Host smart-8c45cf01-6077-452a-9057-2b6113ab2717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183653107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1183653107
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.345950362
Short name T559
Test name
Test status
Simulation time 30662824442 ps
CPU time 21.29 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:21 PM PDT 24
Peak memory 201936 kb
Host smart-4c8d26e2-a671-4191-b0ef-324df6e55146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345950362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.345950362
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3643512130
Short name T368
Test name
Test status
Simulation time 3665063578 ps
CPU time 2.76 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:04 PM PDT 24
Peak memory 201856 kb
Host smart-94642857-1ea7-407e-92bc-6031b4eb5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643512130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3643512130
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1331268042
Short name T81
Test name
Test status
Simulation time 4051959925 ps
CPU time 3.11 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 217484 kb
Host smart-cf99d984-c7c5-4151-805d-7d4506fa147a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331268042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1331268042
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2601806207
Short name T675
Test name
Test status
Simulation time 6128396527 ps
CPU time 4.61 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:06 PM PDT 24
Peak memory 201932 kb
Host smart-a90c7553-d621-4beb-8d69-474f90b5d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601806207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2601806207
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3176926057
Short name T16
Test name
Test status
Simulation time 10138521612 ps
CPU time 26.37 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:28:29 PM PDT 24
Peak memory 210688 kb
Host smart-bf872071-44f8-461d-8749-b34d5eb6e82b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176926057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3176926057
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1342791519
Short name T513
Test name
Test status
Simulation time 452079161 ps
CPU time 1.67 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 201976 kb
Host smart-11e35254-e6c6-4946-ace8-bfacce264b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342791519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1342791519
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2576596238
Short name T111
Test name
Test status
Simulation time 166610126707 ps
CPU time 52.28 seconds
Started Aug 17 05:28:02 PM PDT 24
Finished Aug 17 05:28:55 PM PDT 24
Peak memory 202148 kb
Host smart-181a982f-f61f-4bf9-b8bd-79c99db1bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576596238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2576596238
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3656059491
Short name T605
Test name
Test status
Simulation time 497360070350 ps
CPU time 288.79 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:32:54 PM PDT 24
Peak memory 202072 kb
Host smart-ab09bca7-94e7-4011-8f84-7897c7688c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656059491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3656059491
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4259902463
Short name T393
Test name
Test status
Simulation time 498371243002 ps
CPU time 563.04 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:37:28 PM PDT 24
Peak memory 202108 kb
Host smart-baa74f18-5273-4083-bd1f-b935b8960313
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259902463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4259902463
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2950606393
Short name T432
Test name
Test status
Simulation time 488452241881 ps
CPU time 268.54 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:32:30 PM PDT 24
Peak memory 202116 kb
Host smart-13fc3290-789a-4c01-a17d-fc792f57af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950606393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2950606393
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.493309450
Short name T357
Test name
Test status
Simulation time 496519761352 ps
CPU time 1166.32 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:47:25 PM PDT 24
Peak memory 202100 kb
Host smart-2d05fde0-c705-4502-9c92-9c44969b033d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=493309450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.493309450
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1302097243
Short name T332
Test name
Test status
Simulation time 198442756024 ps
CPU time 235.18 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:31:53 PM PDT 24
Peak memory 202176 kb
Host smart-f00e8ccc-6c14-4100-af5c-4e4c4b01845f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302097243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1302097243
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.790440451
Short name T437
Test name
Test status
Simulation time 388020016077 ps
CPU time 198.95 seconds
Started Aug 17 05:27:52 PM PDT 24
Finished Aug 17 05:31:11 PM PDT 24
Peak memory 202140 kb
Host smart-a02297d3-0512-4fb9-8004-934ce37c092b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790440451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.790440451
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3268961410
Short name T542
Test name
Test status
Simulation time 120853492677 ps
CPU time 370.85 seconds
Started Aug 17 05:28:02 PM PDT 24
Finished Aug 17 05:34:13 PM PDT 24
Peak memory 202416 kb
Host smart-52a128f0-a974-4c6b-8b66-4a0c5c426cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268961410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3268961410
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1690602928
Short name T107
Test name
Test status
Simulation time 45541943275 ps
CPU time 54.33 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:56 PM PDT 24
Peak memory 201956 kb
Host smart-823df909-86af-4fea-9134-587c89f69ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690602928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1690602928
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1110516911
Short name T406
Test name
Test status
Simulation time 4207302404 ps
CPU time 2.26 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:28:07 PM PDT 24
Peak memory 201944 kb
Host smart-92136ff8-931e-44c5-baee-c6d06804ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110516911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1110516911
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3670730669
Short name T628
Test name
Test status
Simulation time 5942154948 ps
CPU time 4.35 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:05 PM PDT 24
Peak memory 201968 kb
Host smart-73a07ecb-59b8-4e85-9f90-100176620105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670730669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3670730669
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3069509956
Short name T422
Test name
Test status
Simulation time 6400749128 ps
CPU time 5.81 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 202320 kb
Host smart-a05a5e3e-43d5-4a58-ad5d-c8a355ab3425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069509956 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3069509956
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2748370391
Short name T721
Test name
Test status
Simulation time 300166266 ps
CPU time 0.96 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:28:13 PM PDT 24
Peak memory 201924 kb
Host smart-13e15b88-54cd-4f92-8bf4-6181131d7028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748370391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2748370391
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.506390033
Short name T615
Test name
Test status
Simulation time 363335428435 ps
CPU time 196.16 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:31:24 PM PDT 24
Peak memory 202020 kb
Host smart-becc1557-3da2-4bf6-a559-14b98fe9f031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506390033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.506390033
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.854192962
Short name T668
Test name
Test status
Simulation time 199782359413 ps
CPU time 82.09 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:29:36 PM PDT 24
Peak memory 202064 kb
Host smart-ab760519-bdb1-4b11-a716-a7ad8017c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854192962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.854192962
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.994378984
Short name T226
Test name
Test status
Simulation time 488876030409 ps
CPU time 1186.67 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:47:59 PM PDT 24
Peak memory 202084 kb
Host smart-0f40a80a-d41c-4664-9e62-9550bdee9f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994378984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.994378984
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2432731301
Short name T683
Test name
Test status
Simulation time 508169911339 ps
CPU time 1201.52 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:48:29 PM PDT 24
Peak memory 202188 kb
Host smart-9f03f28e-e615-4ff4-9f68-a8f9611105a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432731301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2432731301
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2576627186
Short name T634
Test name
Test status
Simulation time 323372952736 ps
CPU time 356.71 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 202128 kb
Host smart-efb0abe0-4369-450c-afce-c8534f17efef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576627186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2576627186
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1965663753
Short name T739
Test name
Test status
Simulation time 490390051364 ps
CPU time 1072.33 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:46:07 PM PDT 24
Peak memory 202148 kb
Host smart-f803e754-9013-4448-8cc4-22bb1a1bedb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965663753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1965663753
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1489068404
Short name T159
Test name
Test status
Simulation time 182869020906 ps
CPU time 425.07 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 202072 kb
Host smart-762727f4-1ba0-471b-82d3-32a21f8834c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489068404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1489068404
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.336736315
Short name T382
Test name
Test status
Simulation time 403152881195 ps
CPU time 847.96 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:42:32 PM PDT 24
Peak memory 202104 kb
Host smart-a51be10c-a68c-46d4-9b3c-a5d1b96b0183
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336736315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.336736315
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.840619544
Short name T679
Test name
Test status
Simulation time 94615269940 ps
CPU time 332.81 seconds
Started Aug 17 05:28:19 PM PDT 24
Finished Aug 17 05:33:52 PM PDT 24
Peak memory 202316 kb
Host smart-4a968fdc-a871-4521-aed2-3abdc2566a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840619544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.840619544
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2872258624
Short name T379
Test name
Test status
Simulation time 33963796785 ps
CPU time 20.99 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:28:35 PM PDT 24
Peak memory 201976 kb
Host smart-0dbda68b-3cc1-46c4-a838-f547eb909277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872258624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2872258624
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1626001936
Short name T520
Test name
Test status
Simulation time 5273060283 ps
CPU time 12.57 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:28:26 PM PDT 24
Peak memory 201928 kb
Host smart-76d0c8ee-3cb9-414f-a213-067586486677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626001936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1626001936
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3747796604
Short name T417
Test name
Test status
Simulation time 6200979141 ps
CPU time 15.24 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:28:27 PM PDT 24
Peak memory 201916 kb
Host smart-2bea1caa-e984-4ae0-ad3f-316481809b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747796604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3747796604
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1805075439
Short name T267
Test name
Test status
Simulation time 435405745326 ps
CPU time 789.26 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:41:27 PM PDT 24
Peak memory 210472 kb
Host smart-a154f247-7fb4-49e6-8917-5107a66cfdbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805075439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1805075439
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.602376861
Short name T237
Test name
Test status
Simulation time 5852166785 ps
CPU time 5.86 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:22 PM PDT 24
Peak memory 202008 kb
Host smart-f1816d65-f8cb-45ec-9b5e-dd5c3a8ae4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602376861 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.602376861
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1066043694
Short name T383
Test name
Test status
Simulation time 316297389 ps
CPU time 0.84 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:28:23 PM PDT 24
Peak memory 201960 kb
Host smart-b6b1dc44-6dce-47e7-8f01-81a78a4a277c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066043694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1066043694
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.894293513
Short name T235
Test name
Test status
Simulation time 334847038108 ps
CPU time 211.46 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:31:46 PM PDT 24
Peak memory 202120 kb
Host smart-5b558556-9690-4a0b-8cc3-2fda129bd1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894293513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.894293513
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.456252457
Short name T503
Test name
Test status
Simulation time 161049723861 ps
CPU time 50.26 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:29:17 PM PDT 24
Peak memory 202112 kb
Host smart-8590a7c8-b77a-498d-8bd3-c6a80e382c18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=456252457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.456252457
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.317483172
Short name T699
Test name
Test status
Simulation time 487971929985 ps
CPU time 534.69 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:37:11 PM PDT 24
Peak memory 202136 kb
Host smart-88a0dec0-2c9f-4b27-995b-617dd70158ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317483172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.317483172
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2613849536
Short name T702
Test name
Test status
Simulation time 489184142933 ps
CPU time 283.42 seconds
Started Aug 17 05:28:30 PM PDT 24
Finished Aug 17 05:33:13 PM PDT 24
Peak memory 202136 kb
Host smart-20eedbe8-9fc3-4028-9db5-6232c38d79e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613849536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2613849536
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1185183064
Short name T438
Test name
Test status
Simulation time 390889426644 ps
CPU time 505.4 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:36:49 PM PDT 24
Peak memory 202296 kb
Host smart-0904c85d-5c1f-407c-9ffa-f8ca8bfd7c44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185183064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1185183064
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.283511332
Short name T117
Test name
Test status
Simulation time 108625572889 ps
CPU time 398.05 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:35:02 PM PDT 24
Peak memory 202424 kb
Host smart-a6874821-c390-4304-aa0a-80e3f4b20c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283511332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.283511332
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2933444866
Short name T532
Test name
Test status
Simulation time 34363699969 ps
CPU time 19.94 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:28:34 PM PDT 24
Peak memory 201856 kb
Host smart-f57c2583-fdb1-49d3-9561-12b9c298cfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933444866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2933444866
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3525092545
Short name T601
Test name
Test status
Simulation time 2714314171 ps
CPU time 2.19 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:28:22 PM PDT 24
Peak memory 200388 kb
Host smart-c06af5d6-ef43-49de-9dcb-2c764904c06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525092545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3525092545
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2250249022
Short name T388
Test name
Test status
Simulation time 6118694517 ps
CPU time 2.34 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:28:13 PM PDT 24
Peak memory 201932 kb
Host smart-fe8d26a6-e297-4565-8c75-76c42c66f9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250249022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2250249022
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3621131552
Short name T211
Test name
Test status
Simulation time 259746855101 ps
CPU time 571.1 seconds
Started Aug 17 05:28:30 PM PDT 24
Finished Aug 17 05:38:02 PM PDT 24
Peak memory 202360 kb
Host smart-f04a0bb8-ac9a-4c17-b011-f6a5d064e2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621131552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3621131552
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2465845829
Short name T754
Test name
Test status
Simulation time 25073586935 ps
CPU time 11.92 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:28:30 PM PDT 24
Peak memory 210512 kb
Host smart-a2986ae7-779c-4f77-87b6-da33f211843b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465845829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2465845829
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.426424110
Short name T672
Test name
Test status
Simulation time 511567388 ps
CPU time 1.67 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:18 PM PDT 24
Peak memory 201968 kb
Host smart-f563b4d0-c14d-4ed3-99d8-197ea16c9a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426424110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.426424110
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3787052819
Short name T239
Test name
Test status
Simulation time 532403864836 ps
CPU time 373.05 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:34:30 PM PDT 24
Peak memory 202052 kb
Host smart-b159d7f9-b80d-4d26-9f45-e1a72c0ad3f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787052819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3787052819
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3276657900
Short name T564
Test name
Test status
Simulation time 166573379607 ps
CPU time 182.91 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:31:28 PM PDT 24
Peak memory 202164 kb
Host smart-7876627c-a3c5-42ac-a201-2ee7761c418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276657900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3276657900
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.835628294
Short name T161
Test name
Test status
Simulation time 332961134574 ps
CPU time 754.78 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:40:59 PM PDT 24
Peak memory 202124 kb
Host smart-9f20f096-73dd-48f8-940e-4d5181946cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835628294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.835628294
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2972860683
Short name T740
Test name
Test status
Simulation time 496204029428 ps
CPU time 1018.66 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:45:22 PM PDT 24
Peak memory 202204 kb
Host smart-388ac3f4-9796-46e4-ad57-1b7813ec2e5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972860683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2972860683
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2457838114
Short name T389
Test name
Test status
Simulation time 162714794868 ps
CPU time 89.21 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:29:46 PM PDT 24
Peak memory 202164 kb
Host smart-beb980d3-a9d9-434d-9d01-c91c46a3c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457838114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2457838114
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3127787963
Short name T723
Test name
Test status
Simulation time 499281174178 ps
CPU time 293.56 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:33:21 PM PDT 24
Peak memory 202168 kb
Host smart-95e2811f-3ce3-4212-a62d-0a58a5f0c782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127787963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3127787963
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.914892041
Short name T277
Test name
Test status
Simulation time 579974539117 ps
CPU time 1259.55 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:49:16 PM PDT 24
Peak memory 202120 kb
Host smart-027db352-d280-48ff-a301-c32b85343db5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914892041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.914892041
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4003865976
Short name T632
Test name
Test status
Simulation time 621934434196 ps
CPU time 1436.81 seconds
Started Aug 17 05:28:19 PM PDT 24
Finished Aug 17 05:52:16 PM PDT 24
Peak memory 202064 kb
Host smart-8c2dc8f8-30c2-48f1-8b49-d7a8bc3b8553
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003865976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4003865976
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4269385057
Short name T743
Test name
Test status
Simulation time 86380461568 ps
CPU time 397.65 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 202364 kb
Host smart-d7517136-db66-4b9f-b4c2-ebfd6a3c3845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269385057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4269385057
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2173121499
Short name T569
Test name
Test status
Simulation time 21432659836 ps
CPU time 51.75 seconds
Started Aug 17 05:28:28 PM PDT 24
Finished Aug 17 05:29:20 PM PDT 24
Peak memory 201956 kb
Host smart-76e30384-4a8c-4bc8-a845-23f48d105d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173121499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2173121499
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2756233155
Short name T106
Test name
Test status
Simulation time 4209534903 ps
CPU time 3.48 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:28:24 PM PDT 24
Peak memory 200392 kb
Host smart-0a76f92e-11a4-4ccc-8cf8-5193acd3136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756233155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2756233155
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2904489957
Short name T424
Test name
Test status
Simulation time 5847562778 ps
CPU time 13.59 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:28:31 PM PDT 24
Peak memory 201908 kb
Host smart-f695e66f-e7c7-42ea-b9aa-62f5c16f57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904489957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2904489957
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3555989875
Short name T346
Test name
Test status
Simulation time 245965522532 ps
CPU time 312.62 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:33:32 PM PDT 24
Peak memory 218752 kb
Host smart-bd8765ec-fd68-4264-b167-7723d83dc861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555989875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3555989875
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3897008620
Short name T249
Test name
Test status
Simulation time 41432291904 ps
CPU time 18.43 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:28:39 PM PDT 24
Peak memory 210428 kb
Host smart-f25b1cec-a0c3-4a66-a61b-3cd758d18b8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897008620 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3897008620
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.382531818
Short name T435
Test name
Test status
Simulation time 518559307 ps
CPU time 1.29 seconds
Started Aug 17 05:28:30 PM PDT 24
Finished Aug 17 05:28:32 PM PDT 24
Peak memory 201944 kb
Host smart-1359b1cc-caf3-46fb-8668-b9a8dd5b2ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382531818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.382531818
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3885643246
Short name T190
Test name
Test status
Simulation time 522826236323 ps
CPU time 50.96 seconds
Started Aug 17 05:28:15 PM PDT 24
Finished Aug 17 05:29:06 PM PDT 24
Peak memory 202112 kb
Host smart-4868e855-2e9e-47c3-b449-a481dbe64da2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885643246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3885643246
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1514640459
Short name T266
Test name
Test status
Simulation time 163504373702 ps
CPU time 197.83 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:31:42 PM PDT 24
Peak memory 202164 kb
Host smart-92fd4ea4-679d-409b-ab6e-9b03b3a27f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514640459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1514640459
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2256424550
Short name T258
Test name
Test status
Simulation time 489272753856 ps
CPU time 1174.41 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:47:52 PM PDT 24
Peak memory 202128 kb
Host smart-498a41eb-1653-4501-aa5d-2f2ef2d75d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256424550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2256424550
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2344501053
Short name T479
Test name
Test status
Simulation time 166011894567 ps
CPU time 406.18 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:35:11 PM PDT 24
Peak memory 202120 kb
Host smart-c0d8d216-470b-44e4-a38e-43e7a1f221fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344501053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2344501053
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1094581425
Short name T126
Test name
Test status
Simulation time 161743925591 ps
CPU time 340.42 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:34:05 PM PDT 24
Peak memory 202120 kb
Host smart-a1da13a4-8d2e-40e8-88f5-c695b18a0912
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094581425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1094581425
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2768862498
Short name T649
Test name
Test status
Simulation time 165597174178 ps
CPU time 234.41 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:32:22 PM PDT 24
Peak memory 202120 kb
Host smart-46a33739-93d5-4d7c-b1bd-5d62911205e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768862498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2768862498
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1305726691
Short name T541
Test name
Test status
Simulation time 605576619212 ps
CPU time 669.61 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:39:29 PM PDT 24
Peak memory 200600 kb
Host smart-1d230f0c-1b11-43e5-9701-ff7de1d045a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305726691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1305726691
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1299292243
Short name T349
Test name
Test status
Simulation time 79405266249 ps
CPU time 308.62 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:33:30 PM PDT 24
Peak memory 202372 kb
Host smart-a9ad7cf1-3a81-4168-b95a-0e88d3499726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299292243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1299292243
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.673318183
Short name T184
Test name
Test status
Simulation time 30089212540 ps
CPU time 64.93 seconds
Started Aug 17 05:28:19 PM PDT 24
Finished Aug 17 05:29:24 PM PDT 24
Peak memory 201944 kb
Host smart-0378c340-4c60-4141-b35d-f2a3cd20ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673318183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.673318183
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.645478103
Short name T546
Test name
Test status
Simulation time 3174798364 ps
CPU time 7.66 seconds
Started Aug 17 05:28:21 PM PDT 24
Finished Aug 17 05:28:29 PM PDT 24
Peak memory 201952 kb
Host smart-c89043eb-a5b0-4d71-94c0-d5b277f67f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645478103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.645478103
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3233001145
Short name T369
Test name
Test status
Simulation time 5945126176 ps
CPU time 7.67 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:24 PM PDT 24
Peak memory 201880 kb
Host smart-c11b891d-50b2-4689-b564-a2f96c1b8f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233001145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3233001145
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.174806837
Short name T448
Test name
Test status
Simulation time 215163160377 ps
CPU time 267.54 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:32:48 PM PDT 24
Peak memory 200616 kb
Host smart-08806b0c-6f67-4abb-90ec-976f16c8d72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174806837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
174806837
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3593950878
Short name T14
Test name
Test status
Simulation time 2272992162 ps
CPU time 7.99 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:28:25 PM PDT 24
Peak memory 210460 kb
Host smart-d578a0dc-dd51-4f55-bfbc-f76298503dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593950878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3593950878
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.933931790
Short name T708
Test name
Test status
Simulation time 463612912 ps
CPU time 1.23 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:18 PM PDT 24
Peak memory 201968 kb
Host smart-7a7da293-8994-46a2-8a4b-17dc8b61a44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933931790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.933931790
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2027115258
Short name T285
Test name
Test status
Simulation time 360555890282 ps
CPU time 326.16 seconds
Started Aug 17 05:28:28 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 202184 kb
Host smart-1719cb37-449d-4182-b457-07ddc2a76c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027115258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2027115258
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2898480382
Short name T273
Test name
Test status
Simulation time 495473464820 ps
CPU time 600.29 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:38:25 PM PDT 24
Peak memory 202168 kb
Host smart-5be65b71-7abf-4ff3-a6a9-9e8786a5d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898480382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2898480382
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3974399441
Short name T529
Test name
Test status
Simulation time 167556380828 ps
CPU time 310.91 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:33:36 PM PDT 24
Peak memory 202140 kb
Host smart-80f2f2b6-dce9-48c3-a206-5311c67c9ab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974399441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3974399441
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4062783362
Short name T167
Test name
Test status
Simulation time 487647495289 ps
CPU time 1185.06 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:48:08 PM PDT 24
Peak memory 202116 kb
Host smart-fce9b54c-3672-413a-b38c-b72d312ce5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062783362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4062783362
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1698846430
Short name T545
Test name
Test status
Simulation time 162347777123 ps
CPU time 82.22 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:29:39 PM PDT 24
Peak memory 201992 kb
Host smart-ed2f4cb5-ea1a-4c19-82b1-0ca27bb463cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698846430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1698846430
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3408998142
Short name T322
Test name
Test status
Simulation time 539758333928 ps
CPU time 1276.72 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:49:35 PM PDT 24
Peak memory 202056 kb
Host smart-d931498e-7973-40c5-b3d3-73bc183ba6bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408998142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3408998142
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1939761148
Short name T160
Test name
Test status
Simulation time 391287957380 ps
CPU time 373.66 seconds
Started Aug 17 05:28:15 PM PDT 24
Finished Aug 17 05:34:29 PM PDT 24
Peak memory 202112 kb
Host smart-34f54126-cba8-4cde-9127-4a82b3344cbf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939761148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1939761148
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2358766505
Short name T784
Test name
Test status
Simulation time 90601127783 ps
CPU time 511.86 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:36:59 PM PDT 24
Peak memory 202368 kb
Host smart-57fa1e79-e579-4d37-9835-4c45657d51ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358766505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2358766505
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1779550042
Short name T380
Test name
Test status
Simulation time 26408487074 ps
CPU time 13.85 seconds
Started Aug 17 05:28:15 PM PDT 24
Finished Aug 17 05:28:29 PM PDT 24
Peak memory 201948 kb
Host smart-6c9e06e0-d068-43fe-a7f5-185c34620b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779550042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1779550042
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3868729655
Short name T391
Test name
Test status
Simulation time 4783078956 ps
CPU time 12.02 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:28 PM PDT 24
Peak memory 201844 kb
Host smart-ee9d882c-bb79-453f-a5de-a9c9dcc9a65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868729655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3868729655
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2077016810
Short name T442
Test name
Test status
Simulation time 5892282580 ps
CPU time 4.07 seconds
Started Aug 17 05:28:21 PM PDT 24
Finished Aug 17 05:28:26 PM PDT 24
Peak memory 201948 kb
Host smart-5a8f1f85-b581-49b4-bda7-7676ed5ee95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077016810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2077016810
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3930576610
Short name T544
Test name
Test status
Simulation time 168472454082 ps
CPU time 98.92 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:29:53 PM PDT 24
Peak memory 202064 kb
Host smart-c503db7e-b1e2-41d2-902b-2cbe44972c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930576610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3930576610
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1929704865
Short name T625
Test name
Test status
Simulation time 304083407 ps
CPU time 0.78 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:28:46 PM PDT 24
Peak memory 201968 kb
Host smart-576f3e2f-e125-4a8f-915a-3d058b69294c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929704865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1929704865
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1047538599
Short name T191
Test name
Test status
Simulation time 333715138382 ps
CPU time 92.34 seconds
Started Aug 17 05:28:19 PM PDT 24
Finished Aug 17 05:29:51 PM PDT 24
Peak memory 202108 kb
Host smart-aaeb06e8-ca37-4551-b1c5-4e2f33c2c7ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047538599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1047538599
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4257688365
Short name T263
Test name
Test status
Simulation time 182373763916 ps
CPU time 114.27 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:30:11 PM PDT 24
Peak memory 202148 kb
Host smart-5f104687-b607-4765-b4ec-a9ebe5acd346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257688365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4257688365
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3133933780
Short name T327
Test name
Test status
Simulation time 492684334677 ps
CPU time 1237.25 seconds
Started Aug 17 05:28:23 PM PDT 24
Finished Aug 17 05:49:00 PM PDT 24
Peak memory 202128 kb
Host smart-bdaceae4-aab0-4873-9e4a-d2bfe9afe100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133933780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3133933780
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1426247567
Short name T620
Test name
Test status
Simulation time 495293426516 ps
CPU time 290.01 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 202140 kb
Host smart-adee372b-8367-4c8f-8b54-9bb1c2cdba9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426247567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1426247567
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4212506310
Short name T660
Test name
Test status
Simulation time 496369023363 ps
CPU time 298.87 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:33:17 PM PDT 24
Peak memory 202084 kb
Host smart-624910a1-f77c-4fde-ba21-76a5a6c7e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212506310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4212506310
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2277669019
Short name T378
Test name
Test status
Simulation time 495528168625 ps
CPU time 536.52 seconds
Started Aug 17 05:28:20 PM PDT 24
Finished Aug 17 05:37:16 PM PDT 24
Peak memory 200564 kb
Host smart-4b56299a-ff8f-4f06-a6e9-d89417397393
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277669019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2277669019
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1185547707
Short name T121
Test name
Test status
Simulation time 521478274621 ps
CPU time 1026.31 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:45:24 PM PDT 24
Peak memory 202128 kb
Host smart-0e74587d-9892-4299-b655-d22ee84023c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185547707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1185547707
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2544532795
Short name T462
Test name
Test status
Simulation time 616444580316 ps
CPU time 367.58 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:34:24 PM PDT 24
Peak memory 202080 kb
Host smart-6cbb18d8-b5ff-4838-80cb-baea7c7ea100
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544532795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2544532795
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1435100917
Short name T419
Test name
Test status
Simulation time 109769592765 ps
CPU time 443.43 seconds
Started Aug 17 05:28:29 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 202348 kb
Host smart-587f8ede-6d2d-409a-9f92-241e8ff74da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435100917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1435100917
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1587874354
Short name T364
Test name
Test status
Simulation time 43231785870 ps
CPU time 26.02 seconds
Started Aug 17 05:28:29 PM PDT 24
Finished Aug 17 05:28:55 PM PDT 24
Peak memory 201956 kb
Host smart-d1be309b-5ee1-4de9-aefc-e861cde41dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587874354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1587874354
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2460682975
Short name T595
Test name
Test status
Simulation time 2846208334 ps
CPU time 2.27 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:28:24 PM PDT 24
Peak memory 201956 kb
Host smart-3ff39607-fdf1-4ad1-af56-de4a227e053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460682975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2460682975
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4116561003
Short name T65
Test name
Test status
Simulation time 6219949682 ps
CPU time 4.3 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:20 PM PDT 24
Peak memory 201940 kb
Host smart-442fb2ac-bb12-4b1e-b7ff-e4204809692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116561003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4116561003
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.720756057
Short name T604
Test name
Test status
Simulation time 7774965511 ps
CPU time 6.62 seconds
Started Aug 17 05:28:31 PM PDT 24
Finished Aug 17 05:28:37 PM PDT 24
Peak memory 202336 kb
Host smart-16c92f8d-1bc4-473c-850c-999faba88d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720756057 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.720756057
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2258521592
Short name T550
Test name
Test status
Simulation time 481378334 ps
CPU time 1.68 seconds
Started Aug 17 05:28:26 PM PDT 24
Finished Aug 17 05:28:28 PM PDT 24
Peak memory 201952 kb
Host smart-d7477fb6-3cd4-4980-ac59-3f20a1011c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258521592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2258521592
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1359383525
Short name T647
Test name
Test status
Simulation time 164233672275 ps
CPU time 45.98 seconds
Started Aug 17 05:28:42 PM PDT 24
Finished Aug 17 05:29:28 PM PDT 24
Peak memory 202112 kb
Host smart-dd04c808-efc6-469a-9bcc-05a873449d22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359383525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1359383525
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4051434649
Short name T181
Test name
Test status
Simulation time 501680965653 ps
CPU time 1152.45 seconds
Started Aug 17 05:28:41 PM PDT 24
Finished Aug 17 05:47:54 PM PDT 24
Peak memory 202120 kb
Host smart-c662036d-1f67-4d97-9fec-115b6d08d31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051434649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4051434649
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3399834814
Short name T681
Test name
Test status
Simulation time 168986599331 ps
CPU time 395.37 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:35:02 PM PDT 24
Peak memory 202128 kb
Host smart-1f05b24e-48ab-4623-bd4d-f4894f03e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399834814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3399834814
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1629037068
Short name T726
Test name
Test status
Simulation time 489496480233 ps
CPU time 221.62 seconds
Started Aug 17 05:28:34 PM PDT 24
Finished Aug 17 05:32:15 PM PDT 24
Peak memory 202124 kb
Host smart-571ce499-cb27-4524-a904-214e738a9b31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629037068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1629037068
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3256393567
Short name T102
Test name
Test status
Simulation time 493700226601 ps
CPU time 424.48 seconds
Started Aug 17 05:28:30 PM PDT 24
Finished Aug 17 05:35:35 PM PDT 24
Peak memory 202128 kb
Host smart-1217fa6c-70ee-4d9c-b074-b1e981739751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256393567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3256393567
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.255820633
Short name T405
Test name
Test status
Simulation time 163023228712 ps
CPU time 57.7 seconds
Started Aug 17 05:28:26 PM PDT 24
Finished Aug 17 05:29:24 PM PDT 24
Peak memory 202092 kb
Host smart-e0eeb3bf-74fe-4ff6-a809-613914fed4f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=255820633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.255820633
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.788913029
Short name T300
Test name
Test status
Simulation time 520450661975 ps
CPU time 290.19 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:33:38 PM PDT 24
Peak memory 202108 kb
Host smart-6ddb9bf6-543c-4a0f-a126-eb87fe38d16e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788913029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.788913029
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.806851095
Short name T644
Test name
Test status
Simulation time 200782024513 ps
CPU time 237.25 seconds
Started Aug 17 05:28:32 PM PDT 24
Finished Aug 17 05:32:29 PM PDT 24
Peak memory 202064 kb
Host smart-d40ab63a-c120-40e0-9383-7860ce303db7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806851095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.806851095
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1113000376
Short name T599
Test name
Test status
Simulation time 81024242249 ps
CPU time 268.53 seconds
Started Aug 17 05:28:29 PM PDT 24
Finished Aug 17 05:32:58 PM PDT 24
Peak memory 202352 kb
Host smart-113729b4-5510-40b5-8475-6c75aa32142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113000376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1113000376
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2098376919
Short name T783
Test name
Test status
Simulation time 26204644247 ps
CPU time 15.45 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:29:01 PM PDT 24
Peak memory 201896 kb
Host smart-41f90224-c0bf-41e7-bef9-966ec0bc8cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098376919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2098376919
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3489897344
Short name T648
Test name
Test status
Simulation time 4998786347 ps
CPU time 12.25 seconds
Started Aug 17 05:28:27 PM PDT 24
Finished Aug 17 05:28:39 PM PDT 24
Peak memory 201876 kb
Host smart-4a40866d-104f-44f8-91d2-5c242ac8463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489897344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3489897344
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3800773243
Short name T374
Test name
Test status
Simulation time 5982382119 ps
CPU time 12.73 seconds
Started Aug 17 05:28:35 PM PDT 24
Finished Aug 17 05:28:48 PM PDT 24
Peak memory 201936 kb
Host smart-11371359-6b07-4bb8-bab4-6b9b9f5ee4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800773243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3800773243
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1679030174
Short name T307
Test name
Test status
Simulation time 343291836929 ps
CPU time 204.06 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:32:08 PM PDT 24
Peak memory 202100 kb
Host smart-92e7c53d-28e7-44e3-ac40-ca548f9efee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679030174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1679030174
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.523411567
Short name T20
Test name
Test status
Simulation time 1981232676 ps
CPU time 13.66 seconds
Started Aug 17 05:28:28 PM PDT 24
Finished Aug 17 05:28:42 PM PDT 24
Peak memory 210676 kb
Host smart-7548e768-3f48-4681-9c4b-e505f89c7d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523411567 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.523411567
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2823567377
Short name T778
Test name
Test status
Simulation time 528974387 ps
CPU time 1.16 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:28:44 PM PDT 24
Peak memory 201956 kb
Host smart-093bd4b8-9a5b-4ffa-8ad3-d161e8729061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823567377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2823567377
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3667807526
Short name T29
Test name
Test status
Simulation time 166888267109 ps
CPU time 107.74 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:30:12 PM PDT 24
Peak memory 202032 kb
Host smart-15b177f7-0891-457c-814c-7340135e4d41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667807526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3667807526
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2955977821
Short name T152
Test name
Test status
Simulation time 330096851095 ps
CPU time 186.71 seconds
Started Aug 17 05:28:31 PM PDT 24
Finished Aug 17 05:31:38 PM PDT 24
Peak memory 202124 kb
Host smart-b6601e95-65a9-45a1-bd74-4e46477b7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955977821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2955977821
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4192886033
Short name T282
Test name
Test status
Simulation time 327770516495 ps
CPU time 776.18 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:41:21 PM PDT 24
Peak memory 202068 kb
Host smart-6b610780-75b8-4d43-b827-f00bcef155da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192886033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4192886033
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2981816985
Short name T703
Test name
Test status
Simulation time 493331460880 ps
CPU time 288.99 seconds
Started Aug 17 05:28:35 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 202152 kb
Host smart-619a491b-d864-4d02-b3bf-3df02f25dcf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981816985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2981816985
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.856985660
Short name T538
Test name
Test status
Simulation time 321919842129 ps
CPU time 116.08 seconds
Started Aug 17 05:28:29 PM PDT 24
Finished Aug 17 05:30:25 PM PDT 24
Peak memory 202192 kb
Host smart-5098b32e-6a05-4c63-b362-2ac0620ee96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856985660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.856985660
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3660606856
Short name T742
Test name
Test status
Simulation time 167008509441 ps
CPU time 94.71 seconds
Started Aug 17 05:28:34 PM PDT 24
Finished Aug 17 05:30:09 PM PDT 24
Peak memory 202012 kb
Host smart-88d82c45-f16b-4103-ac60-a3e16ab664ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660606856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3660606856
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1541986145
Short name T296
Test name
Test status
Simulation time 374883966395 ps
CPU time 222.46 seconds
Started Aug 17 05:28:36 PM PDT 24
Finished Aug 17 05:32:19 PM PDT 24
Peak memory 202140 kb
Host smart-f0c5f061-b4e0-4781-b04d-a6eab46f4cc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541986145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1541986145
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3899273731
Short name T764
Test name
Test status
Simulation time 76442794354 ps
CPU time 256.66 seconds
Started Aug 17 05:28:32 PM PDT 24
Finished Aug 17 05:32:49 PM PDT 24
Peak memory 202344 kb
Host smart-2a9fb974-fb81-4385-8d33-c4edee3ab872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899273731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3899273731
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3497424199
Short name T606
Test name
Test status
Simulation time 23970503301 ps
CPU time 55.38 seconds
Started Aug 17 05:28:26 PM PDT 24
Finished Aug 17 05:29:22 PM PDT 24
Peak memory 201944 kb
Host smart-712ab9c4-32cc-44f0-86de-dd75578611f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497424199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3497424199
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1406612750
Short name T38
Test name
Test status
Simulation time 4049782328 ps
CPU time 10.18 seconds
Started Aug 17 05:28:37 PM PDT 24
Finished Aug 17 05:28:48 PM PDT 24
Peak memory 201928 kb
Host smart-fa577c61-6b33-442c-bf8b-ab1ef9e8ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406612750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1406612750
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3294807919
Short name T97
Test name
Test status
Simulation time 6002581178 ps
CPU time 13.42 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:28:56 PM PDT 24
Peak memory 201912 kb
Host smart-d338ae25-5eac-44d6-baf1-9697a9ddf49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294807919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3294807919
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3303706893
Short name T276
Test name
Test status
Simulation time 337882870280 ps
CPU time 223.81 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:32:27 PM PDT 24
Peak memory 202036 kb
Host smart-df4f79ff-3ad3-407c-8af4-7fed4d926680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303706893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3303706893
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1239783410
Short name T733
Test name
Test status
Simulation time 299465273 ps
CPU time 0.97 seconds
Started Aug 17 05:28:33 PM PDT 24
Finished Aug 17 05:28:34 PM PDT 24
Peak memory 201964 kb
Host smart-b48939d0-6fdc-4e8c-80eb-e0d2811e80a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239783410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1239783410
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2772490072
Short name T299
Test name
Test status
Simulation time 515971554813 ps
CPU time 47.59 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:29:25 PM PDT 24
Peak memory 202112 kb
Host smart-87b2c030-3ade-452a-a6ae-90c6cdef0775
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772490072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2772490072
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1262685797
Short name T654
Test name
Test status
Simulation time 329185968288 ps
CPU time 52.4 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:29:37 PM PDT 24
Peak memory 202112 kb
Host smart-8b2baa1f-0a9f-4e53-a462-e659d0d090ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262685797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1262685797
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.877181241
Short name T386
Test name
Test status
Simulation time 325599350584 ps
CPU time 380.02 seconds
Started Aug 17 05:28:41 PM PDT 24
Finished Aug 17 05:35:01 PM PDT 24
Peak memory 202112 kb
Host smart-fcbefe75-1c2c-40ec-9f70-0f1144e2adbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=877181241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.877181241
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2893613027
Short name T411
Test name
Test status
Simulation time 503514928326 ps
CPU time 190.76 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:31:50 PM PDT 24
Peak memory 202144 kb
Host smart-dc932fbd-af0b-40a9-849c-30c938ff184d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893613027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2893613027
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2130703534
Short name T284
Test name
Test status
Simulation time 183533094624 ps
CPU time 405.02 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:35:31 PM PDT 24
Peak memory 202124 kb
Host smart-f4ef8aa6-a878-489d-93c7-426de3301470
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130703534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2130703534
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2318298499
Short name T491
Test name
Test status
Simulation time 612147690268 ps
CPU time 378.07 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 202132 kb
Host smart-b89c87e2-bd97-4c05-93a7-70d58b7c5a65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318298499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2318298499
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1256593652
Short name T753
Test name
Test status
Simulation time 34907038108 ps
CPU time 70.64 seconds
Started Aug 17 05:28:32 PM PDT 24
Finished Aug 17 05:29:42 PM PDT 24
Peak memory 201960 kb
Host smart-797b27c8-b60f-4d73-bbda-a5151b10ebfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256593652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1256593652
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.7429066
Short name T697
Test name
Test status
Simulation time 5755083416 ps
CPU time 7.32 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:28:53 PM PDT 24
Peak memory 201944 kb
Host smart-ec5b6916-47ba-4b68-b1da-07fd36bc948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7429066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.7429066
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3854545675
Short name T602
Test name
Test status
Simulation time 5659208554 ps
CPU time 4.16 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:28:51 PM PDT 24
Peak memory 201920 kb
Host smart-5f6ab9e7-9bd1-492a-95d0-de74e6eea689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854545675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3854545675
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3208030587
Short name T748
Test name
Test status
Simulation time 305937723714 ps
CPU time 540.02 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:37:40 PM PDT 24
Peak memory 210564 kb
Host smart-cadda6ac-bc38-447c-9279-badc69489dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208030587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3208030587
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.420026016
Short name T560
Test name
Test status
Simulation time 3481362645 ps
CPU time 7.53 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:28:46 PM PDT 24
Peak memory 202024 kb
Host smart-6c411c94-6992-4c01-9b2d-fbf6063fb5d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420026016 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.420026016
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.547230441
Short name T122
Test name
Test status
Simulation time 341224443 ps
CPU time 0.81 seconds
Started Aug 17 05:28:49 PM PDT 24
Finished Aug 17 05:28:50 PM PDT 24
Peak memory 201948 kb
Host smart-2f45f2ce-1460-42cc-869e-1cfe4e70f1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547230441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.547230441
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3182196703
Short name T260
Test name
Test status
Simulation time 584792606015 ps
CPU time 326.36 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:34:06 PM PDT 24
Peak memory 202196 kb
Host smart-938cf00f-4f28-4d37-9df5-3ac0bb808203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182196703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3182196703
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2303458427
Short name T109
Test name
Test status
Simulation time 331337057668 ps
CPU time 704.77 seconds
Started Aug 17 05:28:34 PM PDT 24
Finished Aug 17 05:40:19 PM PDT 24
Peak memory 202124 kb
Host smart-5c6eeb86-d382-4f50-bad6-33a2ac098c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303458427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2303458427
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2111261470
Short name T232
Test name
Test status
Simulation time 161700282287 ps
CPU time 351.62 seconds
Started Aug 17 05:28:37 PM PDT 24
Finished Aug 17 05:34:29 PM PDT 24
Peak memory 202084 kb
Host smart-31f326d0-5f81-454c-9f22-46bdd8303c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111261470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2111261470
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1116782565
Short name T399
Test name
Test status
Simulation time 164721317645 ps
CPU time 354.42 seconds
Started Aug 17 05:28:41 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 202044 kb
Host smart-0837037a-0151-42b3-b777-92669eca1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116782565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1116782565
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2326293186
Short name T453
Test name
Test status
Simulation time 334141539406 ps
CPU time 788.54 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:41:49 PM PDT 24
Peak memory 202168 kb
Host smart-86620188-9de5-4777-8745-457c740b6372
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326293186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2326293186
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.982460005
Short name T151
Test name
Test status
Simulation time 631100026464 ps
CPU time 438.01 seconds
Started Aug 17 05:28:42 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 202192 kb
Host smart-bd4efe96-10a5-4b6a-bc24-ebeb6e28b2b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982460005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.982460005
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.742475386
Short name T526
Test name
Test status
Simulation time 599562142675 ps
CPU time 637.93 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:39:25 PM PDT 24
Peak memory 202088 kb
Host smart-f99de7bb-0fa5-43fa-ae7e-830ae98aad20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742475386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.742475386
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.830835406
Short name T348
Test name
Test status
Simulation time 90786409067 ps
CPU time 370.92 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 202396 kb
Host smart-8dca6b55-56de-4e37-b691-92d6b81d32aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830835406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.830835406
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.302570249
Short name T789
Test name
Test status
Simulation time 28941903748 ps
CPU time 33.12 seconds
Started Aug 17 05:28:36 PM PDT 24
Finished Aug 17 05:29:09 PM PDT 24
Peak memory 201880 kb
Host smart-1cc8f54d-aed8-4487-b3f0-b6cfeab97fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302570249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.302570249
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1311536999
Short name T474
Test name
Test status
Simulation time 3092640104 ps
CPU time 1.36 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:28:49 PM PDT 24
Peak memory 201948 kb
Host smart-4bdea09f-18b2-452e-b88a-644a3895f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311536999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1311536999
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2155319002
Short name T496
Test name
Test status
Simulation time 6059060588 ps
CPU time 15.12 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:28:59 PM PDT 24
Peak memory 201936 kb
Host smart-7c963829-ceb8-4ad0-88fe-aacfdb0eac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155319002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2155319002
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1110820993
Short name T99
Test name
Test status
Simulation time 243865498124 ps
CPU time 552.99 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:38:00 PM PDT 24
Peak memory 202072 kb
Host smart-fd6e8796-9cd8-48c6-b119-bd7a4e5124bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110820993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1110820993
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1057202038
Short name T469
Test name
Test status
Simulation time 491206629 ps
CPU time 1.79 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:28:08 PM PDT 24
Peak memory 201492 kb
Host smart-edc84a0c-95ce-4014-920e-e44d74ece846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057202038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1057202038
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2095664200
Short name T531
Test name
Test status
Simulation time 359103699489 ps
CPU time 217.85 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:31:43 PM PDT 24
Peak memory 202132 kb
Host smart-c83350f5-2e51-449e-9f7a-f7e9d45304aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095664200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2095664200
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4192555490
Short name T292
Test name
Test status
Simulation time 165124934520 ps
CPU time 132.63 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:30:25 PM PDT 24
Peak memory 202208 kb
Host smart-2ed3087d-de8f-4800-9e25-bc34c2708b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192555490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4192555490
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2835680865
Short name T367
Test name
Test status
Simulation time 325115942365 ps
CPU time 194.49 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:31:29 PM PDT 24
Peak memory 202232 kb
Host smart-f682ee1c-bd5c-4277-8ec1-8d6593b75ea2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835680865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2835680865
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.4080617049
Short name T468
Test name
Test status
Simulation time 163944749366 ps
CPU time 41.62 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:28:48 PM PDT 24
Peak memory 202172 kb
Host smart-bcaca887-a371-43f0-a87f-34ca0b653e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080617049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4080617049
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1640503588
Short name T584
Test name
Test status
Simulation time 499185396263 ps
CPU time 396.66 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:34:41 PM PDT 24
Peak memory 202092 kb
Host smart-3f3e8cb0-5b41-490f-8c92-3bd257acac3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640503588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1640503588
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.192753579
Short name T392
Test name
Test status
Simulation time 417013881851 ps
CPU time 146.94 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:30:31 PM PDT 24
Peak memory 202128 kb
Host smart-67593963-6d29-4dbf-b131-752b8f6d35cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192753579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.192753579
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.56641229
Short name T556
Test name
Test status
Simulation time 110561756079 ps
CPU time 358.27 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:34:07 PM PDT 24
Peak memory 202392 kb
Host smart-5235df67-56f4-4235-a671-d8747eba3ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56641229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.56641229
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1842670624
Short name T98
Test name
Test status
Simulation time 25787550967 ps
CPU time 28.18 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:28:34 PM PDT 24
Peak memory 201944 kb
Host smart-32317558-110d-4479-bf40-5afc6fe0846a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842670624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1842670624
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1319246382
Short name T659
Test name
Test status
Simulation time 5069345629 ps
CPU time 12.55 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:28:25 PM PDT 24
Peak memory 201952 kb
Host smart-37dc0294-beb3-47ef-af91-1d509474e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319246382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1319246382
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3418160170
Short name T80
Test name
Test status
Simulation time 7807580165 ps
CPU time 9.55 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:18 PM PDT 24
Peak memory 218668 kb
Host smart-1ab88135-3d27-4bd1-bdcd-792498da523c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418160170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3418160170
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2321647322
Short name T430
Test name
Test status
Simulation time 5992671054 ps
CPU time 13.28 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:28:22 PM PDT 24
Peak memory 201880 kb
Host smart-f75a5d6d-fef7-4fa1-a582-3482f470fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321647322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2321647322
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3287388318
Short name T676
Test name
Test status
Simulation time 777998233467 ps
CPU time 1626.86 seconds
Started Aug 17 05:28:21 PM PDT 24
Finished Aug 17 05:55:28 PM PDT 24
Peak memory 202208 kb
Host smart-f9ee6bcf-d1e7-469e-a61c-11f879a3178c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287388318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3287388318
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2740354650
Short name T44
Test name
Test status
Simulation time 69042780305 ps
CPU time 38.42 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:28:48 PM PDT 24
Peak memory 210708 kb
Host smart-3708418f-75e1-4fa6-a3b4-6a16df18b896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740354650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2740354650
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2135677572
Short name T366
Test name
Test status
Simulation time 349100902 ps
CPU time 1 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:28:44 PM PDT 24
Peak memory 202016 kb
Host smart-bda36317-f1a9-4ef9-bd81-15424ee1c551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135677572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2135677572
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2761941139
Short name T39
Test name
Test status
Simulation time 385085633531 ps
CPU time 432.11 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 202032 kb
Host smart-2676a3ec-0d85-4990-9368-aa8c317f2e07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761941139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2761941139
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.836018894
Short name T236
Test name
Test status
Simulation time 377759784462 ps
CPU time 929.57 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:44:08 PM PDT 24
Peak memory 202140 kb
Host smart-7f71e836-a8b5-4c62-aa05-ad50d08a025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836018894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.836018894
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1797344920
Short name T770
Test name
Test status
Simulation time 163675785256 ps
CPU time 119.55 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:30:40 PM PDT 24
Peak memory 202144 kb
Host smart-0babe090-9171-43f7-94cc-bb5afbdc5e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797344920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1797344920
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3275116120
Short name T537
Test name
Test status
Simulation time 330338934193 ps
CPU time 179.86 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:31:40 PM PDT 24
Peak memory 202184 kb
Host smart-2eec562d-9b5b-420b-9e5c-095cc24c1c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275116120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3275116120
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2917147276
Short name T511
Test name
Test status
Simulation time 334365035728 ps
CPU time 392.14 seconds
Started Aug 17 05:28:36 PM PDT 24
Finished Aug 17 05:35:08 PM PDT 24
Peak memory 202124 kb
Host smart-253009ab-ab50-4ecd-8de3-956dcdc95618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917147276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2917147276
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4195184187
Short name T404
Test name
Test status
Simulation time 490097655539 ps
CPU time 1120.97 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:47:20 PM PDT 24
Peak memory 202128 kb
Host smart-3e9e7c1e-55c0-495b-b56c-f9436af9dd59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195184187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4195184187
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.267770382
Short name T56
Test name
Test status
Simulation time 188791559628 ps
CPU time 55.89 seconds
Started Aug 17 05:28:41 PM PDT 24
Finished Aug 17 05:29:37 PM PDT 24
Peak memory 202080 kb
Host smart-9008d6a1-a39c-41ea-a42a-52d5011f4a94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267770382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.267770382
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.203222314
Short name T361
Test name
Test status
Simulation time 603339690648 ps
CPU time 1270.2 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:49:57 PM PDT 24
Peak memory 202196 kb
Host smart-7f1b8c30-8a71-4026-a3a8-ba0ff8b6a09a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203222314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.203222314
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1721458630
Short name T674
Test name
Test status
Simulation time 32350695895 ps
CPU time 71.87 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:29:57 PM PDT 24
Peak memory 201956 kb
Host smart-f110ae64-b068-46a6-b8a1-2a0ddda64c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721458630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1721458630
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2738098697
Short name T695
Test name
Test status
Simulation time 3848328918 ps
CPU time 2.94 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:28:43 PM PDT 24
Peak memory 201940 kb
Host smart-da97fe78-3847-4b01-8bc7-65e9c6eac7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738098697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2738098697
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.810998271
Short name T750
Test name
Test status
Simulation time 5787543981 ps
CPU time 14.69 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:29:02 PM PDT 24
Peak memory 201968 kb
Host smart-b4ba8c0c-9723-4a03-8211-75bad7c060d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810998271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.810998271
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1461540349
Short name T643
Test name
Test status
Simulation time 380534627930 ps
CPU time 243.4 seconds
Started Aug 17 05:28:42 PM PDT 24
Finished Aug 17 05:32:46 PM PDT 24
Peak memory 202064 kb
Host smart-db121df9-9bcc-4c55-b7c6-67fdd716915c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461540349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1461540349
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2776483266
Short name T687
Test name
Test status
Simulation time 418432334 ps
CPU time 0.74 seconds
Started Aug 17 05:28:49 PM PDT 24
Finished Aug 17 05:28:49 PM PDT 24
Peak memory 201968 kb
Host smart-a5ba5001-b13b-4041-81b7-57d4cfc22b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776483266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2776483266
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2085809395
Short name T787
Test name
Test status
Simulation time 368787277522 ps
CPU time 397.24 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 202072 kb
Host smart-5d23da0a-4492-4e27-9c46-458e895a281e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085809395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2085809395
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.333072149
Short name T221
Test name
Test status
Simulation time 326215524519 ps
CPU time 178.48 seconds
Started Aug 17 05:28:54 PM PDT 24
Finished Aug 17 05:31:52 PM PDT 24
Peak memory 202148 kb
Host smart-75e4ddbc-fe22-4952-a6cf-ccad37cc0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333072149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.333072149
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2827239435
Short name T729
Test name
Test status
Simulation time 326265723180 ps
CPU time 178.03 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:31:51 PM PDT 24
Peak memory 202148 kb
Host smart-1d5a51a0-3c4b-4e1e-94a7-02430bb6b69e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827239435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2827239435
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3717155084
Short name T1
Test name
Test status
Simulation time 487989916823 ps
CPU time 523.09 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:37:23 PM PDT 24
Peak memory 202152 kb
Host smart-e1df5e3d-6428-42a4-86f0-22fc1583ab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717155084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3717155084
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1280138354
Short name T115
Test name
Test status
Simulation time 167416958163 ps
CPU time 361.13 seconds
Started Aug 17 05:28:49 PM PDT 24
Finished Aug 17 05:34:50 PM PDT 24
Peak memory 202032 kb
Host smart-067804b0-85e3-4cf6-b0a3-2ff46c666ee2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280138354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1280138354
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.84053528
Short name T454
Test name
Test status
Simulation time 199041147695 ps
CPU time 446.46 seconds
Started Aug 17 05:28:51 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 202168 kb
Host smart-6c242f91-0f22-4d6b-b4ba-858160cb83f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84053528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.a
dc_ctrl_filters_wakeup_fixed.84053528
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.168448460
Short name T510
Test name
Test status
Simulation time 131298887910 ps
CPU time 496.63 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:37:10 PM PDT 24
Peak memory 202392 kb
Host smart-958f1786-2d0f-4304-a2cf-7bc50f7eb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168448460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.168448460
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3099544422
Short name T782
Test name
Test status
Simulation time 23107333377 ps
CPU time 9.46 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:28:54 PM PDT 24
Peak memory 201944 kb
Host smart-52a11a5a-5bc0-4e83-bde2-5457f76de26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099544422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3099544422
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1226690080
Short name T418
Test name
Test status
Simulation time 5081906545 ps
CPU time 13.24 seconds
Started Aug 17 05:28:40 PM PDT 24
Finished Aug 17 05:28:53 PM PDT 24
Peak memory 201952 kb
Host smart-58787b69-c3cb-4704-af2e-33b5a62a9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226690080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1226690080
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.462854595
Short name T492
Test name
Test status
Simulation time 5907266986 ps
CPU time 4.05 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:28:49 PM PDT 24
Peak memory 201936 kb
Host smart-f346acf2-73db-4336-b1a6-6cda6ae91c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462854595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.462854595
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3016928150
Short name T623
Test name
Test status
Simulation time 340423134518 ps
CPU time 780.32 seconds
Started Aug 17 05:28:43 PM PDT 24
Finished Aug 17 05:41:43 PM PDT 24
Peak memory 202112 kb
Host smart-0b0f2ffe-bbef-4e33-b2f9-dda21be92448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016928150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3016928150
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4077361331
Short name T781
Test name
Test status
Simulation time 19645366096 ps
CPU time 32.38 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:29:20 PM PDT 24
Peak memory 210664 kb
Host smart-511e39c0-a003-4a5f-b338-fbabb71f31ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077361331 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4077361331
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3855222214
Short name T381
Test name
Test status
Simulation time 424016561 ps
CPU time 1.54 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:28:48 PM PDT 24
Peak memory 201948 kb
Host smart-4fea53a6-74b2-4209-9557-0f0cfa9df6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855222214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3855222214
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1489273321
Short name T500
Test name
Test status
Simulation time 327498008306 ps
CPU time 788.74 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:41:57 PM PDT 24
Peak memory 202012 kb
Host smart-6a287609-eeaf-4bba-ab6c-cfc2f3f0ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489273321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1489273321
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4231943835
Short name T718
Test name
Test status
Simulation time 331639099173 ps
CPU time 764.21 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:41:37 PM PDT 24
Peak memory 202120 kb
Host smart-6a31e316-258c-4764-bf2d-8cde0026d001
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231943835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4231943835
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3708051726
Short name T222
Test name
Test status
Simulation time 502335424506 ps
CPU time 559.81 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:38:07 PM PDT 24
Peak memory 202048 kb
Host smart-173e2eb7-119c-4a75-bdd9-6eaea4eb4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708051726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3708051726
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1843117121
Short name T552
Test name
Test status
Simulation time 162836913161 ps
CPU time 329.52 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 201904 kb
Host smart-9864566c-990c-4f34-bb9b-5de67ee12a85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843117121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1843117121
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2996134272
Short name T170
Test name
Test status
Simulation time 175591512342 ps
CPU time 412.02 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:35:44 PM PDT 24
Peak memory 202040 kb
Host smart-da415401-f533-4611-afb0-dc3027425652
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996134272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2996134272
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4119263929
Short name T629
Test name
Test status
Simulation time 198680004396 ps
CPU time 114.11 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:30:41 PM PDT 24
Peak memory 202104 kb
Host smart-0e670e7c-23eb-437e-9026-69095a99c8be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119263929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.4119263929
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2349354851
Short name T528
Test name
Test status
Simulation time 111263997582 ps
CPU time 473.5 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:36:49 PM PDT 24
Peak memory 202360 kb
Host smart-453a504b-85fe-4d4d-bec2-408515cabfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349354851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2349354851
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.49212498
Short name T626
Test name
Test status
Simulation time 34152262755 ps
CPU time 39.49 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:29:35 PM PDT 24
Peak memory 201928 kb
Host smart-4f071cbe-df98-439b-b142-b274476388b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49212498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.49212498
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2098264196
Short name T751
Test name
Test status
Simulation time 2734563370 ps
CPU time 2.32 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:28:54 PM PDT 24
Peak memory 201928 kb
Host smart-65e88b18-c0ad-4b11-94ed-b00324230565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098264196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2098264196
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.614769711
Short name T763
Test name
Test status
Simulation time 5990582277 ps
CPU time 4.28 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:28:42 PM PDT 24
Peak memory 201952 kb
Host smart-7741e17a-b059-4853-bf35-a66617f5ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614769711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.614769711
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2626552567
Short name T788
Test name
Test status
Simulation time 442984796781 ps
CPU time 465.25 seconds
Started Aug 17 05:28:37 PM PDT 24
Finished Aug 17 05:36:23 PM PDT 24
Peak memory 202404 kb
Host smart-9010f442-69d2-45b1-82c1-3070bd9996c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626552567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2626552567
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2075309733
Short name T21
Test name
Test status
Simulation time 16129214592 ps
CPU time 7.39 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:28:55 PM PDT 24
Peak memory 210688 kb
Host smart-4f8f2aa6-4da3-4b6c-aa18-2293c01b194e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075309733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2075309733
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2560358078
Short name T396
Test name
Test status
Simulation time 305421926 ps
CPU time 1.29 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:28:50 PM PDT 24
Peak memory 201940 kb
Host smart-07be4b09-a42a-484c-a5db-240bc02fc85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560358078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2560358078
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.20551940
Short name T715
Test name
Test status
Simulation time 177323505601 ps
CPU time 54.91 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:29:48 PM PDT 24
Peak memory 202084 kb
Host smart-8eff2316-10b4-4022-ac5a-536521612c30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gatin
g.20551940
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1281941420
Short name T259
Test name
Test status
Simulation time 162247323342 ps
CPU time 93.73 seconds
Started Aug 17 05:28:49 PM PDT 24
Finished Aug 17 05:30:23 PM PDT 24
Peak memory 202004 kb
Host smart-ffbea9a9-e088-4d7d-a7fc-138096dc32b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281941420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1281941420
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1163781197
Short name T611
Test name
Test status
Simulation time 164169846194 ps
CPU time 360.93 seconds
Started Aug 17 05:28:51 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 202180 kb
Host smart-89efe0eb-53b1-49a5-9ebe-8a1266eb839b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163781197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1163781197
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.338421775
Short name T519
Test name
Test status
Simulation time 328139638956 ps
CPU time 738.32 seconds
Started Aug 17 05:28:38 PM PDT 24
Finished Aug 17 05:40:56 PM PDT 24
Peak memory 202076 kb
Host smart-e99f4810-f360-4799-ad03-961a1a2da885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338421775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.338421775
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2040516702
Short name T185
Test name
Test status
Simulation time 323856381111 ps
CPU time 763.05 seconds
Started Aug 17 05:28:47 PM PDT 24
Finished Aug 17 05:41:30 PM PDT 24
Peak memory 202080 kb
Host smart-37affb68-90e7-4375-94f0-f064da2091ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040516702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2040516702
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2237102373
Short name T621
Test name
Test status
Simulation time 195304854913 ps
CPU time 105.51 seconds
Started Aug 17 05:28:39 PM PDT 24
Finished Aug 17 05:30:24 PM PDT 24
Peak memory 202108 kb
Host smart-2c121ffd-c682-46c0-a4d4-f378482503e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237102373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2237102373
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.403066017
Short name T28
Test name
Test status
Simulation time 601803441141 ps
CPU time 1403.78 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:52:16 PM PDT 24
Peak memory 202052 kb
Host smart-14ab9007-4748-457e-80a1-64b254ca7441
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403066017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.403066017
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.420579071
Short name T208
Test name
Test status
Simulation time 76560517325 ps
CPU time 444.55 seconds
Started Aug 17 05:28:54 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 202344 kb
Host smart-29cd8539-ad6d-4a7d-a49c-dbe0d760fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420579071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.420579071
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.73297068
Short name T105
Test name
Test status
Simulation time 24755739283 ps
CPU time 14.94 seconds
Started Aug 17 05:28:45 PM PDT 24
Finished Aug 17 05:29:00 PM PDT 24
Peak memory 201920 kb
Host smart-4de1d56f-bdfa-4b3e-b2d3-3828ccb8d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73297068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.73297068
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1872830781
Short name T565
Test name
Test status
Simulation time 2773293403 ps
CPU time 7.92 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:29:01 PM PDT 24
Peak memory 201928 kb
Host smart-a14d4527-d3cd-4973-8da5-86aab4d47338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872830781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1872830781
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3290844910
Short name T407
Test name
Test status
Simulation time 5698617270 ps
CPU time 6.41 seconds
Started Aug 17 05:28:49 PM PDT 24
Finished Aug 17 05:28:55 PM PDT 24
Peak memory 201952 kb
Host smart-c73320e9-647d-4506-9807-6a8f844c5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290844910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3290844910
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2291073025
Short name T506
Test name
Test status
Simulation time 336593934718 ps
CPU time 732.67 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:40:58 PM PDT 24
Peak memory 202108 kb
Host smart-785bda0e-414b-47f6-964a-72a807329cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291073025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2291073025
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2002670618
Short name T48
Test name
Test status
Simulation time 3962160747 ps
CPU time 15.46 seconds
Started Aug 17 05:28:44 PM PDT 24
Finished Aug 17 05:28:59 PM PDT 24
Peak memory 210748 kb
Host smart-b2ec2d9f-318c-4bdb-a722-e427f49d604e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002670618 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2002670618
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3368533515
Short name T549
Test name
Test status
Simulation time 507657488 ps
CPU time 0.91 seconds
Started Aug 17 05:29:00 PM PDT 24
Finished Aug 17 05:29:01 PM PDT 24
Peak memory 201912 kb
Host smart-9cb1f64e-1bd3-4545-ae63-c985bc46ca22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368533515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3368533515
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1722815512
Short name T600
Test name
Test status
Simulation time 334248399667 ps
CPU time 741.65 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:41:18 PM PDT 24
Peak memory 202188 kb
Host smart-b44895cd-a014-4853-ac93-3bb94dd0db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722815512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1722815512
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1912921035
Short name T570
Test name
Test status
Simulation time 169296016605 ps
CPU time 370.91 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:35:03 PM PDT 24
Peak memory 202036 kb
Host smart-abd2cb34-2a99-4548-b154-72cb284d98e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912921035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1912921035
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.779556900
Short name T26
Test name
Test status
Simulation time 168900617038 ps
CPU time 200.45 seconds
Started Aug 17 05:28:46 PM PDT 24
Finished Aug 17 05:32:07 PM PDT 24
Peak memory 202052 kb
Host smart-a2d6c083-3d26-405a-bbd3-f7a9e30c8b84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=779556900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.779556900
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3743191648
Short name T194
Test name
Test status
Simulation time 327946843258 ps
CPU time 388.77 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 202096 kb
Host smart-954fdc72-fa72-4a7b-a627-c657a4921a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743191648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3743191648
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.84679539
Short name T735
Test name
Test status
Simulation time 164828497178 ps
CPU time 150.38 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:31:25 PM PDT 24
Peak memory 202112 kb
Host smart-3a257818-3cd7-4e95-a30a-ae9d36671c8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=84679539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed
.84679539
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3491613340
Short name T539
Test name
Test status
Simulation time 574016492483 ps
CPU time 1302.43 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:50:36 PM PDT 24
Peak memory 202136 kb
Host smart-d4a11ee1-b922-4601-87f7-b9940eb5fb1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491613340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3491613340
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3238645320
Short name T2
Test name
Test status
Simulation time 75461718725 ps
CPU time 317.18 seconds
Started Aug 17 05:28:51 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 202400 kb
Host smart-bf68efc3-1c0e-4e1f-9e38-3e7c60eb3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238645320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3238645320
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1114350998
Short name T728
Test name
Test status
Simulation time 41217166411 ps
CPU time 49.6 seconds
Started Aug 17 05:29:00 PM PDT 24
Finished Aug 17 05:29:50 PM PDT 24
Peak memory 201900 kb
Host smart-b3f3db68-efa4-4c28-9ebb-37f4058b7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114350998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1114350998
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2291077244
Short name T477
Test name
Test status
Simulation time 2979554692 ps
CPU time 2.43 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:28:54 PM PDT 24
Peak memory 201948 kb
Host smart-cf1bc41c-efe1-4505-9bf9-3a8129707cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291077244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2291077244
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3020897983
Short name T429
Test name
Test status
Simulation time 5656193880 ps
CPU time 7.54 seconds
Started Aug 17 05:28:48 PM PDT 24
Finished Aug 17 05:28:55 PM PDT 24
Peak memory 201928 kb
Host smart-ced3a265-0e80-43fc-a6c5-8d995ce126e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020897983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3020897983
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2671482861
Short name T210
Test name
Test status
Simulation time 3243195604594 ps
CPU time 114.67 seconds
Started Aug 17 05:28:52 PM PDT 24
Finished Aug 17 05:30:47 PM PDT 24
Peak memory 210740 kb
Host smart-9cd4bbe4-b29d-4485-9584-23e18042b3ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671482861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2671482861
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1928464870
Short name T427
Test name
Test status
Simulation time 442096451 ps
CPU time 0.9 seconds
Started Aug 17 05:28:59 PM PDT 24
Finished Aug 17 05:29:00 PM PDT 24
Peak memory 201888 kb
Host smart-c2a6bcf1-d479-4274-8efb-664d2df1c20d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928464870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1928464870
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2409049423
Short name T182
Test name
Test status
Simulation time 537100104097 ps
CPU time 202.23 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:32:18 PM PDT 24
Peak memory 202128 kb
Host smart-a38176d6-e507-457e-b518-ed53624c99a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409049423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2409049423
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2930966393
Short name T261
Test name
Test status
Simulation time 333309561335 ps
CPU time 678.21 seconds
Started Aug 17 05:28:54 PM PDT 24
Finished Aug 17 05:40:13 PM PDT 24
Peak memory 202016 kb
Host smart-c1424627-a724-4f7d-8309-2011c2ae4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930966393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2930966393
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2281481285
Short name T669
Test name
Test status
Simulation time 325471997606 ps
CPU time 573.7 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:38:27 PM PDT 24
Peak memory 202140 kb
Host smart-155aee04-74e2-4eeb-b1c9-219d193c5492
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281481285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2281481285
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.561979171
Short name T328
Test name
Test status
Simulation time 333126632635 ps
CPU time 792.42 seconds
Started Aug 17 05:28:51 PM PDT 24
Finished Aug 17 05:42:04 PM PDT 24
Peak memory 202116 kb
Host smart-61907010-d23e-4098-924b-848da21fe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561979171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.561979171
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3604640084
Short name T737
Test name
Test status
Simulation time 485789755113 ps
CPU time 204.86 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:32:18 PM PDT 24
Peak memory 202108 kb
Host smart-65e1922d-8231-4de7-a476-6e48fb4bb367
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604640084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3604640084
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2765088884
Short name T651
Test name
Test status
Simulation time 579250497864 ps
CPU time 1233.51 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:49:28 PM PDT 24
Peak memory 202268 kb
Host smart-63031cc7-6943-480f-a11c-a6bfa181d499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765088884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2765088884
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.93200954
Short name T95
Test name
Test status
Simulation time 605749309725 ps
CPU time 1253.25 seconds
Started Aug 17 05:28:59 PM PDT 24
Finished Aug 17 05:49:53 PM PDT 24
Peak memory 202108 kb
Host smart-f5532e9b-9d77-4fcd-8f28-0128afd4b3a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93200954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.a
dc_ctrl_filters_wakeup_fixed.93200954
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3084727280
Short name T597
Test name
Test status
Simulation time 127790858213 ps
CPU time 452.55 seconds
Started Aug 17 05:29:02 PM PDT 24
Finished Aug 17 05:36:35 PM PDT 24
Peak memory 202420 kb
Host smart-3de9ad28-206b-4331-a67b-8d6063e9bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084727280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3084727280
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1193376288
Short name T376
Test name
Test status
Simulation time 38432457410 ps
CPU time 33.92 seconds
Started Aug 17 05:28:59 PM PDT 24
Finished Aug 17 05:29:33 PM PDT 24
Peak memory 201952 kb
Host smart-87964849-65d6-49ba-83dd-3f0a19579b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193376288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1193376288
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2523562339
Short name T395
Test name
Test status
Simulation time 5274696216 ps
CPU time 11.43 seconds
Started Aug 17 05:29:01 PM PDT 24
Finished Aug 17 05:29:13 PM PDT 24
Peak memory 201900 kb
Host smart-17231fe8-af76-4c6f-ae0b-2fbd4a10d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523562339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2523562339
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3457834769
Short name T607
Test name
Test status
Simulation time 6167641258 ps
CPU time 3.81 seconds
Started Aug 17 05:28:53 PM PDT 24
Finished Aug 17 05:28:57 PM PDT 24
Peak memory 201968 kb
Host smart-e75e9e30-0760-400a-bc9a-fcfdd0e7b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457834769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3457834769
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1447659362
Short name T793
Test name
Test status
Simulation time 542398844111 ps
CPU time 229.58 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 202088 kb
Host smart-c0a672ff-cea0-484c-8acb-6dff81cc6efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447659362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1447659362
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1729094089
Short name T779
Test name
Test status
Simulation time 516788154 ps
CPU time 1.74 seconds
Started Aug 17 05:29:02 PM PDT 24
Finished Aug 17 05:29:04 PM PDT 24
Peak memory 201968 kb
Host smart-95e42b5d-63e0-429e-991b-7131c86d5cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729094089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1729094089
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1760593204
Short name T619
Test name
Test status
Simulation time 504050408799 ps
CPU time 770.93 seconds
Started Aug 17 05:29:02 PM PDT 24
Finished Aug 17 05:41:53 PM PDT 24
Peak memory 202116 kb
Host smart-0fc8fab4-ab54-4219-9117-a238f4bc5a6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760593204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1760593204
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3791542808
Short name T333
Test name
Test status
Simulation time 163610166716 ps
CPU time 108.99 seconds
Started Aug 17 05:28:59 PM PDT 24
Finished Aug 17 05:30:49 PM PDT 24
Peak memory 202176 kb
Host smart-18e36ae0-a7c7-4af2-a466-0cb5ef57ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791542808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3791542808
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.994068549
Short name T745
Test name
Test status
Simulation time 479686223949 ps
CPU time 546.72 seconds
Started Aug 17 05:29:00 PM PDT 24
Finished Aug 17 05:38:07 PM PDT 24
Peak memory 202168 kb
Host smart-243586c5-43db-4b75-a662-ec3c77f3ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994068549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.994068549
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3114437682
Short name T540
Test name
Test status
Simulation time 487432334469 ps
CPU time 281.47 seconds
Started Aug 17 05:28:57 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 202048 kb
Host smart-ac384a76-ba25-4c5d-b495-a95843bf8104
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114437682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3114437682
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.75008506
Short name T193
Test name
Test status
Simulation time 488501912962 ps
CPU time 323.54 seconds
Started Aug 17 05:29:01 PM PDT 24
Finished Aug 17 05:34:24 PM PDT 24
Peak memory 202072 kb
Host smart-bf295f89-a86d-49d8-9a7e-fa2972862cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75008506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.75008506
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3340333771
Short name T22
Test name
Test status
Simulation time 163058114812 ps
CPU time 348.49 seconds
Started Aug 17 05:29:01 PM PDT 24
Finished Aug 17 05:34:49 PM PDT 24
Peak memory 202096 kb
Host smart-51c98e7c-2f05-490a-9bc4-d25ad08e4acf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340333771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3340333771
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.569962191
Short name T658
Test name
Test status
Simulation time 393971604931 ps
CPU time 217.01 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:32:33 PM PDT 24
Peak memory 202100 kb
Host smart-c2e0e0fa-adda-446c-8a48-75f0ddf310b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569962191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.569962191
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2210604197
Short name T485
Test name
Test status
Simulation time 26846754688 ps
CPU time 31.58 seconds
Started Aug 17 05:29:00 PM PDT 24
Finished Aug 17 05:29:32 PM PDT 24
Peak memory 201940 kb
Host smart-7f4412eb-9893-4199-afb1-9799df1798e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210604197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2210604197
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1587159209
Short name T373
Test name
Test status
Simulation time 4286782336 ps
CPU time 2.99 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:29:00 PM PDT 24
Peak memory 201944 kb
Host smart-97cb4f55-d2f9-4dd5-86ab-250cc88e4aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587159209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1587159209
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1474235489
Short name T716
Test name
Test status
Simulation time 5996812325 ps
CPU time 4.49 seconds
Started Aug 17 05:29:03 PM PDT 24
Finished Aug 17 05:29:08 PM PDT 24
Peak memory 201944 kb
Host smart-af4f163e-5636-4f19-bacd-225bb70258d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474235489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1474235489
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1944401241
Short name T329
Test name
Test status
Simulation time 168771555966 ps
CPU time 189.48 seconds
Started Aug 17 05:28:56 PM PDT 24
Finished Aug 17 05:32:06 PM PDT 24
Peak memory 202140 kb
Host smart-2f523d98-6731-42e1-9d0c-212c502a607e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944401241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1944401241
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2626172104
Short name T499
Test name
Test status
Simulation time 1869674374 ps
CPU time 5.28 seconds
Started Aug 17 05:29:01 PM PDT 24
Finished Aug 17 05:29:06 PM PDT 24
Peak memory 201992 kb
Host smart-196f3c50-e34d-4d29-b5b2-8c8d839dfbd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626172104 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2626172104
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1837849025
Short name T547
Test name
Test status
Simulation time 481291483 ps
CPU time 0.9 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:29:11 PM PDT 24
Peak memory 201888 kb
Host smart-bd3ff720-40a9-4853-891e-5a178823c3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837849025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1837849025
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.886749958
Short name T677
Test name
Test status
Simulation time 197109045083 ps
CPU time 27.16 seconds
Started Aug 17 05:29:12 PM PDT 24
Finished Aug 17 05:29:39 PM PDT 24
Peak memory 202152 kb
Host smart-091fbe7f-68e0-4fcb-9c28-f64688804506
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886749958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.886749958
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3527680358
Short name T257
Test name
Test status
Simulation time 529992851094 ps
CPU time 338.71 seconds
Started Aug 17 05:29:08 PM PDT 24
Finished Aug 17 05:34:47 PM PDT 24
Peak memory 202180 kb
Host smart-572bfdc6-19d2-41ad-80bd-ffdfcb701053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527680358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3527680358
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3177307389
Short name T673
Test name
Test status
Simulation time 324870030915 ps
CPU time 83.34 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:30:18 PM PDT 24
Peak memory 202120 kb
Host smart-fbc1c0f5-3ca6-4d9a-a77c-e98b2f302a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177307389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3177307389
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2764041091
Short name T120
Test name
Test status
Simulation time 494472510555 ps
CPU time 1179.55 seconds
Started Aug 17 05:29:14 PM PDT 24
Finished Aug 17 05:48:54 PM PDT 24
Peak memory 202168 kb
Host smart-2322f7cf-7d29-41e4-b1fc-b534a7026f9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764041091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2764041091
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1426097135
Short name T252
Test name
Test status
Simulation time 325774895524 ps
CPU time 763.44 seconds
Started Aug 17 05:29:04 PM PDT 24
Finished Aug 17 05:41:47 PM PDT 24
Peak memory 202068 kb
Host smart-69b0e476-5a2f-4a24-b3e2-ac3e2cf2e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426097135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1426097135
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2211814846
Short name T188
Test name
Test status
Simulation time 160010920100 ps
CPU time 22.23 seconds
Started Aug 17 05:28:55 PM PDT 24
Finished Aug 17 05:29:17 PM PDT 24
Peak memory 202108 kb
Host smart-d3c54622-a751-42b5-b0d6-9ad973899a34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211814846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2211814846
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.231129690
Short name T24
Test name
Test status
Simulation time 373456066874 ps
CPU time 776.4 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:42:07 PM PDT 24
Peak memory 202108 kb
Host smart-741ef9b3-5a0e-4986-9222-e8bebe025600
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231129690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.231129690
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1595946378
Short name T59
Test name
Test status
Simulation time 201368132292 ps
CPU time 231.48 seconds
Started Aug 17 05:29:12 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 202072 kb
Host smart-e7455103-3506-4583-b7a5-df4a4a2c2ff4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595946378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1595946378
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1199420883
Short name T351
Test name
Test status
Simulation time 90742456331 ps
CPU time 402.49 seconds
Started Aug 17 05:29:08 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 202428 kb
Host smart-eca38387-a859-4551-b723-cd109da6ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199420883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1199420883
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3786475529
Short name T354
Test name
Test status
Simulation time 40639376802 ps
CPU time 23.56 seconds
Started Aug 17 05:29:11 PM PDT 24
Finished Aug 17 05:29:35 PM PDT 24
Peak memory 201948 kb
Host smart-3645b186-b191-49ef-ada4-c4d8da1b914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786475529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3786475529
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4268223965
Short name T487
Test name
Test status
Simulation time 5012434026 ps
CPU time 10 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:29:19 PM PDT 24
Peak memory 201944 kb
Host smart-7e9775b2-7012-4b8a-b1ac-aee21a775767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268223965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4268223965
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2988039297
Short name T574
Test name
Test status
Simulation time 5569891523 ps
CPU time 4.08 seconds
Started Aug 17 05:29:02 PM PDT 24
Finished Aug 17 05:29:06 PM PDT 24
Peak memory 201944 kb
Host smart-b2380a9e-df77-46bc-93a1-0d434a4ce16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988039297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2988039297
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1889420033
Short name T50
Test name
Test status
Simulation time 7435159847 ps
CPU time 12.14 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:29:21 PM PDT 24
Peak memory 210684 kb
Host smart-03722279-5ffe-4de5-90c8-6a490350c40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889420033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1889420033
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.183034317
Short name T125
Test name
Test status
Simulation time 362257475 ps
CPU time 1.39 seconds
Started Aug 17 05:29:13 PM PDT 24
Finished Aug 17 05:29:14 PM PDT 24
Peak memory 201972 kb
Host smart-b92bd052-2ab3-4a34-b45f-651dfcc91c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183034317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.183034317
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3741036548
Short name T614
Test name
Test status
Simulation time 164735958239 ps
CPU time 29.42 seconds
Started Aug 17 05:29:11 PM PDT 24
Finished Aug 17 05:29:41 PM PDT 24
Peak memory 202088 kb
Host smart-bff0894e-2f86-4c6b-b60d-fb0c9ab2cbaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741036548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3741036548
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3235618793
Short name T756
Test name
Test status
Simulation time 496184491812 ps
CPU time 614.2 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:39:23 PM PDT 24
Peak memory 202080 kb
Host smart-849e5321-35de-43ac-a44a-99e50f2725a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235618793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3235618793
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2444338104
Short name T689
Test name
Test status
Simulation time 500581520428 ps
CPU time 1067.13 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:46:57 PM PDT 24
Peak memory 202132 kb
Host smart-07c1195c-7faf-483d-bff6-7e7f0375ff40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444338104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2444338104
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1428736894
Short name T791
Test name
Test status
Simulation time 326455770443 ps
CPU time 368.83 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:35:19 PM PDT 24
Peak memory 202112 kb
Host smart-fd36f5d5-8adb-4dd8-968a-e2bf7cc1d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428736894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1428736894
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3738707196
Short name T408
Test name
Test status
Simulation time 501255469816 ps
CPU time 1120.88 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:47:50 PM PDT 24
Peak memory 202100 kb
Host smart-3d0d4036-9f71-452b-8933-88c5f40ab221
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738707196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3738707196
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2726588842
Short name T174
Test name
Test status
Simulation time 747995970893 ps
CPU time 389.54 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 202016 kb
Host smart-e5631144-98f8-4e7b-b1dc-1c9b80ff67b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726588842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2726588842
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2832737434
Short name T785
Test name
Test status
Simulation time 405688888204 ps
CPU time 506.56 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:37:36 PM PDT 24
Peak memory 202064 kb
Host smart-b0c37490-fbac-4281-a95b-e55754bdf7d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832737434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2832737434
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.421979001
Short name T207
Test name
Test status
Simulation time 79276614726 ps
CPU time 301.88 seconds
Started Aug 17 05:29:08 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 202388 kb
Host smart-74a9c600-2083-4708-89ac-b19e462368f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421979001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.421979001
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1376453103
Short name T717
Test name
Test status
Simulation time 24890970916 ps
CPU time 59.5 seconds
Started Aug 17 05:29:11 PM PDT 24
Finished Aug 17 05:30:10 PM PDT 24
Peak memory 201968 kb
Host smart-88497a74-93f1-4813-a161-12e2147cef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376453103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1376453103
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3530216282
Short name T362
Test name
Test status
Simulation time 5508204765 ps
CPU time 12.16 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:29:21 PM PDT 24
Peak memory 201944 kb
Host smart-79fe9fac-c136-42c1-8764-110271883596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530216282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3530216282
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1696237690
Short name T483
Test name
Test status
Simulation time 5646299959 ps
CPU time 3.87 seconds
Started Aug 17 05:29:07 PM PDT 24
Finished Aug 17 05:29:11 PM PDT 24
Peak memory 201940 kb
Host smart-24efad89-f0af-4cc3-b38a-a393c6d039ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696237690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1696237690
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3726137622
Short name T589
Test name
Test status
Simulation time 8943769744 ps
CPU time 20.85 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:29:31 PM PDT 24
Peak memory 201936 kb
Host smart-8e581692-5bae-4529-8349-85e51337c728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726137622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3726137622
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2893532777
Short name T710
Test name
Test status
Simulation time 13320580742 ps
CPU time 21.39 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:29:30 PM PDT 24
Peak memory 210628 kb
Host smart-4b506bb5-be61-4460-b5aa-565363c9d8d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893532777 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2893532777
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4136682456
Short name T363
Test name
Test status
Simulation time 535367883 ps
CPU time 0.76 seconds
Started Aug 17 05:29:14 PM PDT 24
Finished Aug 17 05:29:15 PM PDT 24
Peak memory 201972 kb
Host smart-ebffeb43-2ddd-4751-83cc-7699206316eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136682456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4136682456
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3363895836
Short name T752
Test name
Test status
Simulation time 671957234295 ps
CPU time 740.01 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:41:30 PM PDT 24
Peak memory 202184 kb
Host smart-d099df9f-a07f-4d4d-a116-384e3ce294ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363895836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3363895836
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1039384002
Short name T657
Test name
Test status
Simulation time 327109046058 ps
CPU time 53.33 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:30:03 PM PDT 24
Peak memory 202152 kb
Host smart-f2fe1808-b507-41f5-bb71-8f0dd698cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039384002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1039384002
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1928010610
Short name T652
Test name
Test status
Simulation time 162677362755 ps
CPU time 192.03 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:32:22 PM PDT 24
Peak memory 202108 kb
Host smart-f980da3b-f1a0-4c34-9374-51fd72f9111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928010610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1928010610
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.229133333
Short name T451
Test name
Test status
Simulation time 492310992823 ps
CPU time 328.11 seconds
Started Aug 17 05:29:12 PM PDT 24
Finished Aug 17 05:34:40 PM PDT 24
Peak memory 202112 kb
Host smart-a45cfa25-4878-43ae-805a-f3ef9bc103e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=229133333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.229133333
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2837685311
Short name T774
Test name
Test status
Simulation time 160334927444 ps
CPU time 378.42 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:35:28 PM PDT 24
Peak memory 202116 kb
Host smart-b9f43967-9bfa-4c8d-98a0-e4b0180a376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837685311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2837685311
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2575834989
Short name T603
Test name
Test status
Simulation time 333713359757 ps
CPU time 743.15 seconds
Started Aug 17 05:29:10 PM PDT 24
Finished Aug 17 05:41:34 PM PDT 24
Peak memory 202116 kb
Host smart-2850e201-82d8-452c-a932-d3cfe9bf9e31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575834989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2575834989
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4134113531
Short name T521
Test name
Test status
Simulation time 397817122842 ps
CPU time 179.86 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:32:10 PM PDT 24
Peak memory 202104 kb
Host smart-d6353277-ff37-45ae-82ff-c4ebb8d95a7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134113531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4134113531
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3863617659
Short name T463
Test name
Test status
Simulation time 98784184934 ps
CPU time 487.92 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:37:23 PM PDT 24
Peak memory 202416 kb
Host smart-eebf014f-dbe5-41c4-b6db-26cf2a763534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863617659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3863617659
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1974727596
Short name T402
Test name
Test status
Simulation time 36314352906 ps
CPU time 21.4 seconds
Started Aug 17 05:29:12 PM PDT 24
Finished Aug 17 05:29:33 PM PDT 24
Peak memory 201868 kb
Host smart-4336b0fd-1bed-4b8e-9d38-c6980f41b22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974727596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1974727596
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3321325820
Short name T433
Test name
Test status
Simulation time 4269902346 ps
CPU time 3.42 seconds
Started Aug 17 05:29:08 PM PDT 24
Finished Aug 17 05:29:11 PM PDT 24
Peak memory 201924 kb
Host smart-5643cea3-35b7-4692-a675-46cd6bdf95d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321325820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3321325820
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1398570991
Short name T94
Test name
Test status
Simulation time 5872732386 ps
CPU time 4.61 seconds
Started Aug 17 05:29:11 PM PDT 24
Finished Aug 17 05:29:16 PM PDT 24
Peak memory 201976 kb
Host smart-0db87fdc-6741-4d25-a2fb-9f8e462a7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398570991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1398570991
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2584155286
Short name T308
Test name
Test status
Simulation time 387195418229 ps
CPU time 147.9 seconds
Started Aug 17 05:29:09 PM PDT 24
Finished Aug 17 05:31:37 PM PDT 24
Peak memory 202068 kb
Host smart-05e83bbb-825b-47b0-aaa0-9b3547245028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584155286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2584155286
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.340243213
Short name T535
Test name
Test status
Simulation time 35024583429 ps
CPU time 6.88 seconds
Started Aug 17 05:29:11 PM PDT 24
Finished Aug 17 05:29:18 PM PDT 24
Peak memory 210524 kb
Host smart-bbdea5c7-c4ce-4f05-9d74-8b4a78325e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340243213 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.340243213
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.924346706
Short name T110
Test name
Test status
Simulation time 460178011 ps
CPU time 0.79 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:08 PM PDT 24
Peak memory 201896 kb
Host smart-ec119f33-2480-404b-b7bd-dd441a044e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924346706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.924346706
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2165880760
Short name T637
Test name
Test status
Simulation time 548357157629 ps
CPU time 108.44 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:29:53 PM PDT 24
Peak memory 202136 kb
Host smart-1c814399-6fe3-4bcc-af7e-4e6466f3c303
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165880760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2165880760
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2529337189
Short name T767
Test name
Test status
Simulation time 533824888480 ps
CPU time 135.37 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:30:20 PM PDT 24
Peak memory 202048 kb
Host smart-115f347f-c199-497a-adfe-d79c3b2acfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529337189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2529337189
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1848803057
Short name T55
Test name
Test status
Simulation time 485581498392 ps
CPU time 1162.33 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:47:30 PM PDT 24
Peak memory 202136 kb
Host smart-170b38e9-8204-474b-9563-869c565e6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848803057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1848803057
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.404166881
Short name T9
Test name
Test status
Simulation time 165762501088 ps
CPU time 101.91 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:29:51 PM PDT 24
Peak memory 202132 kb
Host smart-bc030e02-4735-430b-80a4-972e8394ad7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=404166881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.404166881
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2450297877
Short name T425
Test name
Test status
Simulation time 489021747370 ps
CPU time 318.48 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:33:30 PM PDT 24
Peak memory 202104 kb
Host smart-91c471f8-bfdb-46de-9b8b-53f242358c2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450297877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2450297877
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3227269093
Short name T274
Test name
Test status
Simulation time 353442618042 ps
CPU time 201.29 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:31:25 PM PDT 24
Peak memory 202088 kb
Host smart-aefb7799-e19f-4f68-9fcd-d793c7a4224a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227269093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3227269093
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1683027888
Short name T633
Test name
Test status
Simulation time 413241575424 ps
CPU time 74.2 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:29:20 PM PDT 24
Peak memory 201508 kb
Host smart-b1fac23f-baca-4d32-96f4-83315fc62f74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683027888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1683027888
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3131227837
Short name T68
Test name
Test status
Simulation time 141666480748 ps
CPU time 723.07 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:40:07 PM PDT 24
Peak memory 202364 kb
Host smart-e0582811-9573-4362-9a79-c1b417ebfd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131227837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3131227837
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2790032697
Short name T730
Test name
Test status
Simulation time 37456549182 ps
CPU time 20.12 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:28 PM PDT 24
Peak memory 201940 kb
Host smart-a385c1c9-830a-477d-a774-df9bb35b8dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790032697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2790032697
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2803100270
Short name T664
Test name
Test status
Simulation time 3169484257 ps
CPU time 8.43 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:17 PM PDT 24
Peak memory 201944 kb
Host smart-0af8afb3-4c68-4914-96b0-d4e0d603ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803100270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2803100270
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3487919116
Short name T91
Test name
Test status
Simulation time 4096507688 ps
CPU time 10.41 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:28:20 PM PDT 24
Peak memory 217392 kb
Host smart-0623589e-9f46-4500-9f13-8b1f96705da2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487919116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3487919116
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.389973771
Short name T118
Test name
Test status
Simulation time 5712546409 ps
CPU time 14.22 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:25 PM PDT 24
Peak memory 201932 kb
Host smart-ad5e175a-fdeb-4640-869d-5f1ac0c49f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389973771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.389973771
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.884094403
Short name T505
Test name
Test status
Simulation time 11318309747 ps
CPU time 10.01 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:22 PM PDT 24
Peak memory 201936 kb
Host smart-7c1e75a5-c2a0-416a-89ce-3e5d2aa19e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884094403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.884094403
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.586320744
Short name T46
Test name
Test status
Simulation time 2048540497 ps
CPU time 7.88 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:19 PM PDT 24
Peak memory 202032 kb
Host smart-24b93090-6a62-4a25-b503-f57ed5142a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586320744 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.586320744
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3361137321
Short name T613
Test name
Test status
Simulation time 332027834 ps
CPU time 1.31 seconds
Started Aug 17 05:29:24 PM PDT 24
Finished Aug 17 05:29:26 PM PDT 24
Peak memory 202016 kb
Host smart-0cdba72f-c18b-4a5b-9260-9757c7bac1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361137321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3361137321
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4022626761
Short name T334
Test name
Test status
Simulation time 174775393409 ps
CPU time 101.93 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:30:57 PM PDT 24
Peak memory 202156 kb
Host smart-9a41e0ee-32c7-4346-b26b-c76a9a7520cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022626761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4022626761
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1973638559
Short name T304
Test name
Test status
Simulation time 494947382625 ps
CPU time 495.09 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:37:30 PM PDT 24
Peak memory 202108 kb
Host smart-4e285773-5c16-4970-a9bc-186d4c52c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973638559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1973638559
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1666226358
Short name T502
Test name
Test status
Simulation time 168761468340 ps
CPU time 201.4 seconds
Started Aug 17 05:29:17 PM PDT 24
Finished Aug 17 05:32:38 PM PDT 24
Peak memory 202112 kb
Host smart-84a8cd15-e452-4a36-9532-47eea66b684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666226358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1666226358
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4293273866
Short name T360
Test name
Test status
Simulation time 503490132437 ps
CPU time 537.44 seconds
Started Aug 17 05:29:16 PM PDT 24
Finished Aug 17 05:38:14 PM PDT 24
Peak memory 202136 kb
Host smart-504b4a9f-1785-4ef2-a270-a71beeb4eba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293273866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4293273866
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.949100251
Short name T177
Test name
Test status
Simulation time 167837713099 ps
CPU time 183.25 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:32:18 PM PDT 24
Peak memory 202028 kb
Host smart-73271fcb-b9f4-4bf2-a16a-9bac69438128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949100251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.949100251
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1707144885
Short name T495
Test name
Test status
Simulation time 163856845707 ps
CPU time 111.64 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:31:07 PM PDT 24
Peak memory 202036 kb
Host smart-d97806f7-72fd-4ac5-83e7-e87dbef2ad79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707144885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1707144885
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1213399423
Short name T35
Test name
Test status
Simulation time 185150121937 ps
CPU time 212.67 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:32:48 PM PDT 24
Peak memory 202100 kb
Host smart-6a251c0e-9afe-4a72-b321-bc110af8e992
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213399423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1213399423
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3719916338
Short name T4
Test name
Test status
Simulation time 399313558408 ps
CPU time 267.17 seconds
Started Aug 17 05:29:16 PM PDT 24
Finished Aug 17 05:33:43 PM PDT 24
Peak memory 202108 kb
Host smart-dcd627b7-17b9-4c1d-85f4-20e041890aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719916338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3719916338
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.175183056
Short name T209
Test name
Test status
Simulation time 105985701172 ps
CPU time 413.03 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 202376 kb
Host smart-145c3f58-b66b-4bf3-95a0-af2dd7413bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175183056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.175183056
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2392644581
Short name T423
Test name
Test status
Simulation time 28714762159 ps
CPU time 18.69 seconds
Started Aug 17 05:29:15 PM PDT 24
Finished Aug 17 05:29:34 PM PDT 24
Peak memory 201960 kb
Host smart-b11e2d7a-ef63-4035-851a-b44486239546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392644581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2392644581
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3717823574
Short name T655
Test name
Test status
Simulation time 4513377282 ps
CPU time 3.45 seconds
Started Aug 17 05:29:16 PM PDT 24
Finished Aug 17 05:29:20 PM PDT 24
Peak memory 201948 kb
Host smart-45a616c2-1db8-4f79-854d-b51e4b3179a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717823574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3717823574
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2680333443
Short name T686
Test name
Test status
Simulation time 5647430003 ps
CPU time 4.47 seconds
Started Aug 17 05:29:18 PM PDT 24
Finished Aug 17 05:29:23 PM PDT 24
Peak memory 201940 kb
Host smart-d1b98ebd-5260-4a96-b11a-34b6fb07bcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680333443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2680333443
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.121314318
Short name T18
Test name
Test status
Simulation time 8554089886 ps
CPU time 11.66 seconds
Started Aug 17 05:29:24 PM PDT 24
Finished Aug 17 05:29:36 PM PDT 24
Peak memory 210380 kb
Host smart-7515485e-e9bf-48b8-97b6-9914f1b3acba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121314318 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.121314318
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3010351015
Short name T661
Test name
Test status
Simulation time 340805475 ps
CPU time 1.33 seconds
Started Aug 17 05:29:33 PM PDT 24
Finished Aug 17 05:29:35 PM PDT 24
Peak memory 201884 kb
Host smart-ea87511b-69fd-4ae0-b719-9992d9949733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010351015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3010351015
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1079823226
Short name T63
Test name
Test status
Simulation time 228191360173 ps
CPU time 176.23 seconds
Started Aug 17 05:29:24 PM PDT 24
Finished Aug 17 05:32:21 PM PDT 24
Peak memory 202160 kb
Host smart-69ad959b-30c2-41e5-b3cf-87b8f38096bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079823226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1079823226
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1507881427
Short name T298
Test name
Test status
Simulation time 532109729733 ps
CPU time 1212.24 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:49:38 PM PDT 24
Peak memory 202152 kb
Host smart-520ea8ad-1920-467a-92b9-410cccee250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507881427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1507881427
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.671228704
Short name T233
Test name
Test status
Simulation time 507183910545 ps
CPU time 1225.82 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:49:52 PM PDT 24
Peak memory 202096 kb
Host smart-f7f0d975-785c-4e27-97db-bd0af9665c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671228704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.671228704
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3342160232
Short name T766
Test name
Test status
Simulation time 328867327583 ps
CPU time 728.18 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:41:34 PM PDT 24
Peak memory 202164 kb
Host smart-ca447be8-4252-474f-8858-59a1e0388497
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342160232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3342160232
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1901164214
Short name T444
Test name
Test status
Simulation time 484660324412 ps
CPU time 1056.65 seconds
Started Aug 17 05:29:25 PM PDT 24
Finished Aug 17 05:47:02 PM PDT 24
Peak memory 202108 kb
Host smart-7a354289-5ada-42fd-a5c7-4711370e6f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901164214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1901164214
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2905585936
Short name T590
Test name
Test status
Simulation time 493402612537 ps
CPU time 1063.54 seconds
Started Aug 17 05:29:23 PM PDT 24
Finished Aug 17 05:47:07 PM PDT 24
Peak memory 202032 kb
Host smart-9b0033c4-40f1-4456-913d-1541a56c20d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905585936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2905585936
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2443675281
Short name T555
Test name
Test status
Simulation time 261661904251 ps
CPU time 148.03 seconds
Started Aug 17 05:29:23 PM PDT 24
Finished Aug 17 05:31:51 PM PDT 24
Peak memory 202144 kb
Host smart-e436ea7d-1455-4e67-a5be-27e21127d13b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443675281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2443675281
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1091854875
Short name T777
Test name
Test status
Simulation time 588707162554 ps
CPU time 1352.94 seconds
Started Aug 17 05:29:23 PM PDT 24
Finished Aug 17 05:51:56 PM PDT 24
Peak memory 202124 kb
Host smart-14efe6ac-70d8-4b15-a022-4914da021c6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091854875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1091854875
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1494420434
Short name T220
Test name
Test status
Simulation time 75644043336 ps
CPU time 321.95 seconds
Started Aug 17 05:29:25 PM PDT 24
Finished Aug 17 05:34:47 PM PDT 24
Peak memory 202384 kb
Host smart-396122f0-2572-4488-ae99-8c67c934fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494420434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1494420434
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2868239488
Short name T466
Test name
Test status
Simulation time 31523608677 ps
CPU time 20.15 seconds
Started Aug 17 05:29:23 PM PDT 24
Finished Aug 17 05:29:44 PM PDT 24
Peak memory 201900 kb
Host smart-333ad9d2-e8a7-4873-b8fc-f4594b18d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868239488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2868239488
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4062802779
Short name T112
Test name
Test status
Simulation time 5322679865 ps
CPU time 14.41 seconds
Started Aug 17 05:29:26 PM PDT 24
Finished Aug 17 05:29:40 PM PDT 24
Peak memory 201944 kb
Host smart-cc76c127-8320-449c-a42c-90e5c0fe2be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062802779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4062802779
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1806629249
Short name T712
Test name
Test status
Simulation time 5700611268 ps
CPU time 2.28 seconds
Started Aug 17 05:29:25 PM PDT 24
Finished Aug 17 05:29:27 PM PDT 24
Peak memory 201832 kb
Host smart-7e484db1-e632-4e1b-8cd3-d66cfecb6f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806629249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1806629249
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2452314834
Short name T587
Test name
Test status
Simulation time 13343608838 ps
CPU time 16.79 seconds
Started Aug 17 05:29:30 PM PDT 24
Finished Aug 17 05:29:47 PM PDT 24
Peak memory 218596 kb
Host smart-bc5d4647-b6a6-45f6-9f7c-cce13e541ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452314834 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2452314834
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.802327231
Short name T691
Test name
Test status
Simulation time 289961133 ps
CPU time 1.26 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:29:33 PM PDT 24
Peak memory 201960 kb
Host smart-a8d212aa-f996-4bc3-9882-b65095cb9f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802327231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.802327231
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.518074015
Short name T241
Test name
Test status
Simulation time 505670852334 ps
CPU time 1083.75 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:47:36 PM PDT 24
Peak memory 202164 kb
Host smart-93d46aec-4229-4b69-a19c-b3e6080eb761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518074015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.518074015
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1514226844
Short name T228
Test name
Test status
Simulation time 168346007417 ps
CPU time 99.87 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:31:12 PM PDT 24
Peak memory 202144 kb
Host smart-a736b23f-7418-442d-aa66-3a58c84fe169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514226844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1514226844
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3097192696
Short name T755
Test name
Test status
Simulation time 162402638711 ps
CPU time 96.9 seconds
Started Aug 17 05:29:30 PM PDT 24
Finished Aug 17 05:31:07 PM PDT 24
Peak memory 202140 kb
Host smart-2bee0d2b-3c1b-454e-89e9-6fb020816923
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097192696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3097192696
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.111097816
Short name T127
Test name
Test status
Simulation time 165599382941 ps
CPU time 120.5 seconds
Started Aug 17 05:29:34 PM PDT 24
Finished Aug 17 05:31:34 PM PDT 24
Peak memory 202048 kb
Host smart-cd45f5c5-abea-48e5-b32d-fa8d76a24b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111097816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.111097816
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.890283314
Short name T353
Test name
Test status
Simulation time 159301558311 ps
CPU time 325.86 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 202092 kb
Host smart-2bd26730-2026-46a8-983e-e5b47efed4f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=890283314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.890283314
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1572309455
Short name T725
Test name
Test status
Simulation time 206161694855 ps
CPU time 471.42 seconds
Started Aug 17 05:29:31 PM PDT 24
Finished Aug 17 05:37:22 PM PDT 24
Peak memory 202084 kb
Host smart-e0fc202c-bbb8-4fb1-8b28-dcce78e416b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572309455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1572309455
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1400874477
Short name T217
Test name
Test status
Simulation time 98087796195 ps
CPU time 386.7 seconds
Started Aug 17 05:29:34 PM PDT 24
Finished Aug 17 05:36:00 PM PDT 24
Peak memory 202288 kb
Host smart-dad2e861-84d3-4aec-a4d6-5ace4db19168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400874477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1400874477
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4096944693
Short name T459
Test name
Test status
Simulation time 37952198660 ps
CPU time 9.88 seconds
Started Aug 17 05:29:34 PM PDT 24
Finished Aug 17 05:29:44 PM PDT 24
Peak memory 201408 kb
Host smart-3890dcac-1666-4377-a875-9aaf2462f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096944693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4096944693
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1778883737
Short name T124
Test name
Test status
Simulation time 3680907551 ps
CPU time 9.03 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:29:41 PM PDT 24
Peak memory 201952 kb
Host smart-cfca4050-48e9-48cc-aa41-d0ef58b97c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778883737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1778883737
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.4235569305
Short name T436
Test name
Test status
Simulation time 5966544318 ps
CPU time 14.56 seconds
Started Aug 17 05:29:33 PM PDT 24
Finished Aug 17 05:29:47 PM PDT 24
Peak memory 201920 kb
Host smart-923aca00-2322-4ba3-be77-4ac0fac148d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235569305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4235569305
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3523553977
Short name T92
Test name
Test status
Simulation time 348699959372 ps
CPU time 726.66 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:41:38 PM PDT 24
Peak memory 202108 kb
Host smart-a37bb41a-38a3-4dd8-b609-fc8e99444081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523553977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3523553977
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2382328838
Short name T313
Test name
Test status
Simulation time 170082297866 ps
CPU time 21.89 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:29:54 PM PDT 24
Peak memory 210724 kb
Host smart-792642da-19d6-4323-8cf9-ae07c53a342a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382328838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2382328838
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4194181527
Short name T85
Test name
Test status
Simulation time 325534618 ps
CPU time 0.83 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:29:39 PM PDT 24
Peak memory 201904 kb
Host smart-c852df5f-99d6-4061-95f6-d7cc81c9191e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194181527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4194181527
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4180981022
Short name T303
Test name
Test status
Simulation time 330341152207 ps
CPU time 364.72 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 202172 kb
Host smart-5f0e4bec-f918-4e9f-af52-798ea3cc43fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180981022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4180981022
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.550531574
Short name T523
Test name
Test status
Simulation time 327897020636 ps
CPU time 196.28 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:32:48 PM PDT 24
Peak memory 202100 kb
Host smart-50fc7559-e83e-43a6-a420-d8711a563c5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=550531574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.550531574
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2531661083
Short name T577
Test name
Test status
Simulation time 323768175814 ps
CPU time 208.86 seconds
Started Aug 17 05:29:32 PM PDT 24
Finished Aug 17 05:33:01 PM PDT 24
Peak memory 202092 kb
Host smart-ae57708c-1ba9-43f3-a14a-a21234e61818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531661083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2531661083
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3377720708
Short name T377
Test name
Test status
Simulation time 492118725581 ps
CPU time 599.5 seconds
Started Aug 17 05:29:31 PM PDT 24
Finished Aug 17 05:39:30 PM PDT 24
Peak memory 202148 kb
Host smart-763db4c1-559b-49cd-860f-7708e2e326ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377720708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3377720708
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.784552174
Short name T741
Test name
Test status
Simulation time 195232353814 ps
CPU time 106.8 seconds
Started Aug 17 05:29:36 PM PDT 24
Finished Aug 17 05:31:23 PM PDT 24
Peak memory 202108 kb
Host smart-69226c5a-d883-43df-b433-15e5b3bccd41
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784552174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.784552174
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.782038852
Short name T205
Test name
Test status
Simulation time 128719776038 ps
CPU time 429.21 seconds
Started Aug 17 05:29:37 PM PDT 24
Finished Aug 17 05:36:46 PM PDT 24
Peak memory 202364 kb
Host smart-696bd82c-4734-4b21-8dcf-3cf6ec9596e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782038852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.782038852
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.386034388
Short name T571
Test name
Test status
Simulation time 35866997863 ps
CPU time 37.44 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:30:16 PM PDT 24
Peak memory 201972 kb
Host smart-fde7f6f7-23c1-4181-968c-1d022710d150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386034388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.386034388
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1064613955
Short name T371
Test name
Test status
Simulation time 4915545820 ps
CPU time 11.86 seconds
Started Aug 17 05:29:37 PM PDT 24
Finished Aug 17 05:29:49 PM PDT 24
Peak memory 201972 kb
Host smart-1f9ea548-3d09-4166-80a6-cc0f58e0787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064613955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1064613955
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3237962534
Short name T638
Test name
Test status
Simulation time 5759894915 ps
CPU time 4.01 seconds
Started Aug 17 05:29:31 PM PDT 24
Finished Aug 17 05:29:35 PM PDT 24
Peak memory 201956 kb
Host smart-0c408b96-7623-4731-89ad-9c5cae9cea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237962534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3237962534
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.334513942
Short name T27
Test name
Test status
Simulation time 361311432662 ps
CPU time 972.03 seconds
Started Aug 17 05:29:37 PM PDT 24
Finished Aug 17 05:45:49 PM PDT 24
Peak memory 212304 kb
Host smart-56a45b8a-d47b-4ee7-8eb2-19698cc73644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334513942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
334513942
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1312348046
Short name T40
Test name
Test status
Simulation time 4812430788 ps
CPU time 11.24 seconds
Started Aug 17 05:29:39 PM PDT 24
Finished Aug 17 05:29:50 PM PDT 24
Peak memory 210440 kb
Host smart-ad71df95-e787-4c4d-82f5-c4731da43b51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312348046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1312348046
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2618026653
Short name T714
Test name
Test status
Simulation time 402836565 ps
CPU time 1.18 seconds
Started Aug 17 05:29:45 PM PDT 24
Finished Aug 17 05:29:47 PM PDT 24
Peak memory 201884 kb
Host smart-7154878f-6b2a-4b23-8de1-1ef525001337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618026653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2618026653
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1434248090
Short name T242
Test name
Test status
Simulation time 487443018570 ps
CPU time 1127.57 seconds
Started Aug 17 05:29:46 PM PDT 24
Finished Aug 17 05:48:34 PM PDT 24
Peak memory 202116 kb
Host smart-db8eaa42-4c7c-46e5-a3ae-e6875f57f9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434248090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1434248090
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3219383846
Short name T688
Test name
Test status
Simulation time 326784096323 ps
CPU time 360.88 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 202140 kb
Host smart-8c9a8c04-f078-4d13-b89b-a35f5218b56c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219383846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3219383846
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1525277775
Short name T53
Test name
Test status
Simulation time 334379790349 ps
CPU time 200.98 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:32:59 PM PDT 24
Peak memory 202096 kb
Host smart-f756ffd3-9be2-4149-b84e-841e7ee9aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525277775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1525277775
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3592640826
Short name T711
Test name
Test status
Simulation time 167321126291 ps
CPU time 201.86 seconds
Started Aug 17 05:29:36 PM PDT 24
Finished Aug 17 05:32:58 PM PDT 24
Peak memory 202096 kb
Host smart-08a4d59b-b96c-4630-b2c7-1fd8111ab180
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592640826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3592640826
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.4253719906
Short name T515
Test name
Test status
Simulation time 339917146968 ps
CPU time 164.06 seconds
Started Aug 17 05:29:47 PM PDT 24
Finished Aug 17 05:32:31 PM PDT 24
Peak memory 202108 kb
Host smart-0ea1bcfb-5277-4897-8dd0-c27f59092dce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253719906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.4253719906
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2231907379
Short name T472
Test name
Test status
Simulation time 596643781535 ps
CPU time 1272.85 seconds
Started Aug 17 05:29:46 PM PDT 24
Finished Aug 17 05:50:59 PM PDT 24
Peak memory 202124 kb
Host smart-270626a5-dec0-4115-a940-649477d45c98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231907379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2231907379
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.158256642
Short name T530
Test name
Test status
Simulation time 91661368165 ps
CPU time 343.28 seconds
Started Aug 17 05:29:47 PM PDT 24
Finished Aug 17 05:35:31 PM PDT 24
Peak memory 202400 kb
Host smart-34d613cc-7146-4cd9-a510-f32f72904d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158256642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.158256642
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3687481111
Short name T617
Test name
Test status
Simulation time 44588916849 ps
CPU time 54.78 seconds
Started Aug 17 05:29:47 PM PDT 24
Finished Aug 17 05:30:42 PM PDT 24
Peak memory 201940 kb
Host smart-9d4465b9-a4ef-4e9a-be0e-ddbcec100285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687481111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3687481111
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3865163846
Short name T486
Test name
Test status
Simulation time 2852164299 ps
CPU time 6.71 seconds
Started Aug 17 05:29:45 PM PDT 24
Finished Aug 17 05:29:52 PM PDT 24
Peak memory 201904 kb
Host smart-d4e000ee-c043-49bc-bd54-17fa4242ff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865163846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3865163846
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2947505691
Short name T400
Test name
Test status
Simulation time 6043843329 ps
CPU time 4.5 seconds
Started Aug 17 05:29:38 PM PDT 24
Finished Aug 17 05:29:42 PM PDT 24
Peak memory 201920 kb
Host smart-d85391a1-75b0-4d8f-9761-eba835d98b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947505691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2947505691
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1244724479
Short name T768
Test name
Test status
Simulation time 325791477047 ps
CPU time 1060.17 seconds
Started Aug 17 05:29:47 PM PDT 24
Finished Aug 17 05:47:28 PM PDT 24
Peak memory 212824 kb
Host smart-10ce1f5b-28f3-4457-8edc-18a8b0c97497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244724479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1244724479
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1059470209
Short name T666
Test name
Test status
Simulation time 1976510911 ps
CPU time 8.99 seconds
Started Aug 17 05:29:46 PM PDT 24
Finished Aug 17 05:29:55 PM PDT 24
Peak memory 202044 kb
Host smart-3e64c144-6cd7-4e7d-a6bc-b2a85d871f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059470209 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1059470209
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1969708331
Short name T470
Test name
Test status
Simulation time 352488041 ps
CPU time 1.42 seconds
Started Aug 17 05:30:01 PM PDT 24
Finished Aug 17 05:30:02 PM PDT 24
Peak memory 201972 kb
Host smart-5ede5d45-fc40-4fd6-ac49-01925e20b3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969708331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1969708331
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2149461610
Short name T198
Test name
Test status
Simulation time 519810575924 ps
CPU time 158.15 seconds
Started Aug 17 05:29:51 PM PDT 24
Finished Aug 17 05:32:30 PM PDT 24
Peak memory 202116 kb
Host smart-5c7b5e1c-6ffe-442b-8ef0-e206860adbe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149461610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2149461610
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3850070641
Short name T321
Test name
Test status
Simulation time 519658691653 ps
CPU time 257.07 seconds
Started Aug 17 05:29:53 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 202084 kb
Host smart-5ad1c222-dada-45d5-b198-a0f7e0efef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850070641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3850070641
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3801520055
Short name T517
Test name
Test status
Simulation time 489125365168 ps
CPU time 607.06 seconds
Started Aug 17 05:29:52 PM PDT 24
Finished Aug 17 05:40:00 PM PDT 24
Peak memory 202188 kb
Host smart-2091909b-ecb8-4278-9921-7574c1e60c6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801520055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3801520055
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4191517246
Short name T573
Test name
Test status
Simulation time 335690135957 ps
CPU time 166.16 seconds
Started Aug 17 05:29:50 PM PDT 24
Finished Aug 17 05:32:37 PM PDT 24
Peak memory 202116 kb
Host smart-c2d5c992-c983-4f62-b24a-7626e69959d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191517246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4191517246
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3426344015
Short name T701
Test name
Test status
Simulation time 160370915494 ps
CPU time 377.37 seconds
Started Aug 17 05:29:55 PM PDT 24
Finished Aug 17 05:36:12 PM PDT 24
Peak memory 202144 kb
Host smart-4d144306-341a-4fc9-995a-0e07240dc2bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426344015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3426344015
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3951786342
Short name T747
Test name
Test status
Simulation time 567953778288 ps
CPU time 172.43 seconds
Started Aug 17 05:29:51 PM PDT 24
Finished Aug 17 05:32:44 PM PDT 24
Peak memory 202172 kb
Host smart-c6c7ae7d-9444-4d85-933d-742154958399
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951786342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3951786342
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2941668050
Short name T10
Test name
Test status
Simulation time 204445047730 ps
CPU time 285.23 seconds
Started Aug 17 05:29:56 PM PDT 24
Finished Aug 17 05:34:41 PM PDT 24
Peak memory 202124 kb
Host smart-957fd552-0cf7-4e66-a82c-e7e96bb94609
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941668050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2941668050
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2275643718
Short name T347
Test name
Test status
Simulation time 107525592797 ps
CPU time 546.35 seconds
Started Aug 17 05:29:53 PM PDT 24
Finished Aug 17 05:38:59 PM PDT 24
Peak memory 202396 kb
Host smart-3f6c56d0-0331-4962-9602-107cea918aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275643718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2275643718
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2744035741
Short name T352
Test name
Test status
Simulation time 36647519016 ps
CPU time 23.96 seconds
Started Aug 17 05:29:55 PM PDT 24
Finished Aug 17 05:30:19 PM PDT 24
Peak memory 201944 kb
Host smart-a3492a05-a44f-4e94-8dd6-b9249dd5b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744035741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2744035741
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2618918099
Short name T786
Test name
Test status
Simulation time 4201530400 ps
CPU time 3.19 seconds
Started Aug 17 05:29:52 PM PDT 24
Finished Aug 17 05:29:55 PM PDT 24
Peak memory 201916 kb
Host smart-2d2dd839-fb79-4f9b-a301-3bafd82dc3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618918099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2618918099
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.791532100
Short name T370
Test name
Test status
Simulation time 5701761356 ps
CPU time 14.86 seconds
Started Aug 17 05:29:55 PM PDT 24
Finished Aug 17 05:30:10 PM PDT 24
Peak memory 201900 kb
Host smart-bf274c79-764b-4497-af51-b9154f3542b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791532100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.791532100
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1849655048
Short name T31
Test name
Test status
Simulation time 325411412957 ps
CPU time 173.93 seconds
Started Aug 17 05:29:59 PM PDT 24
Finished Aug 17 05:32:53 PM PDT 24
Peak memory 202108 kb
Host smart-57873ae7-bdbc-4291-b9ff-62de0e8ccb23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849655048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1849655048
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3480834345
Short name T494
Test name
Test status
Simulation time 5162397410 ps
CPU time 19.13 seconds
Started Aug 17 05:29:52 PM PDT 24
Finished Aug 17 05:30:11 PM PDT 24
Peak memory 210716 kb
Host smart-027ab18d-5680-4978-a78e-0d333b39deb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480834345 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3480834345
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2483357357
Short name T624
Test name
Test status
Simulation time 334153717 ps
CPU time 0.75 seconds
Started Aug 17 05:30:07 PM PDT 24
Finished Aug 17 05:30:08 PM PDT 24
Peak memory 201860 kb
Host smart-f5792626-933b-40f3-9c41-0456fe5b573b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483357357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2483357357
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3492265254
Short name T736
Test name
Test status
Simulation time 342447657715 ps
CPU time 31.76 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:30:32 PM PDT 24
Peak memory 202164 kb
Host smart-98aca451-6b19-4f28-80d7-515e60abfdf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492265254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3492265254
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1667993673
Short name T162
Test name
Test status
Simulation time 163332178822 ps
CPU time 179.14 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:33:00 PM PDT 24
Peak memory 202132 kb
Host smart-dde7db2f-3fb6-4efa-9ac5-07e266a1fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667993673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1667993673
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1745731531
Short name T312
Test name
Test status
Simulation time 327527969071 ps
CPU time 666.59 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:41:07 PM PDT 24
Peak memory 202108 kb
Host smart-c1189c13-100d-4bb8-a4e0-5716ce5631ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745731531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1745731531
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1276619481
Short name T119
Test name
Test status
Simulation time 331548780136 ps
CPU time 712.94 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:41:53 PM PDT 24
Peak memory 202104 kb
Host smart-2fbff40d-1ddd-46db-94f1-816a83df0414
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276619481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1276619481
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2159391996
Short name T765
Test name
Test status
Simulation time 325853829904 ps
CPU time 184.33 seconds
Started Aug 17 05:30:01 PM PDT 24
Finished Aug 17 05:33:05 PM PDT 24
Peak memory 202024 kb
Host smart-c3431427-2a6f-431d-a478-05c3d0815d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159391996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2159391996
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.296985210
Short name T684
Test name
Test status
Simulation time 329848351868 ps
CPU time 349.52 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:35:49 PM PDT 24
Peak memory 202064 kb
Host smart-e24983a1-1ec9-4aaa-8a6e-87a01a8b32be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=296985210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.296985210
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.623580911
Short name T156
Test name
Test status
Simulation time 380838355377 ps
CPU time 913.33 seconds
Started Aug 17 05:29:59 PM PDT 24
Finished Aug 17 05:45:13 PM PDT 24
Peak memory 202076 kb
Host smart-e3f19956-349f-4ae5-9d12-729d696e806d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623580911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.623580911
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2059589301
Short name T775
Test name
Test status
Simulation time 603846040792 ps
CPU time 146.97 seconds
Started Aug 17 05:30:01 PM PDT 24
Finished Aug 17 05:32:28 PM PDT 24
Peak memory 202036 kb
Host smart-84ce3c8a-4671-4ff3-88c6-d77afcf3c44e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059589301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2059589301
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3048502639
Short name T218
Test name
Test status
Simulation time 80288793019 ps
CPU time 328.94 seconds
Started Aug 17 05:29:58 PM PDT 24
Finished Aug 17 05:35:27 PM PDT 24
Peak memory 202372 kb
Host smart-4a60bd97-5e36-4d34-868c-265853b337c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048502639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3048502639
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.4058665432
Short name T128
Test name
Test status
Simulation time 42562513694 ps
CPU time 46.03 seconds
Started Aug 17 05:30:02 PM PDT 24
Finished Aug 17 05:30:48 PM PDT 24
Peak memory 201896 kb
Host smart-24e1426f-03de-49a6-a601-3c03c13656ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058665432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4058665432
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1735923869
Short name T563
Test name
Test status
Simulation time 3891265140 ps
CPU time 4.86 seconds
Started Aug 17 05:29:59 PM PDT 24
Finished Aug 17 05:30:03 PM PDT 24
Peak memory 201936 kb
Host smart-d081c48a-0bad-42db-bca0-fa511d6f4a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735923869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1735923869
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2499214444
Short name T440
Test name
Test status
Simulation time 6167436952 ps
CPU time 4.28 seconds
Started Aug 17 05:30:00 PM PDT 24
Finished Aug 17 05:30:04 PM PDT 24
Peak memory 201944 kb
Host smart-ec1d1e31-9576-40d9-8923-a1f9219ab56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499214444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2499214444
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4059938261
Short name T762
Test name
Test status
Simulation time 169498789532 ps
CPU time 207.24 seconds
Started Aug 17 05:30:08 PM PDT 24
Finished Aug 17 05:33:35 PM PDT 24
Peak memory 202092 kb
Host smart-bec5d6bb-04b1-4ec5-9469-211dae8d99e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059938261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4059938261
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.816790233
Short name T522
Test name
Test status
Simulation time 405825886 ps
CPU time 0.85 seconds
Started Aug 17 05:30:17 PM PDT 24
Finished Aug 17 05:30:18 PM PDT 24
Peak memory 201972 kb
Host smart-bc88a8ec-6b8d-497e-9778-4e9e68a84858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816790233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.816790233
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2159069738
Short name T746
Test name
Test status
Simulation time 422749276951 ps
CPU time 472.33 seconds
Started Aug 17 05:30:17 PM PDT 24
Finished Aug 17 05:38:10 PM PDT 24
Peak memory 202136 kb
Host smart-bdbdbcd2-229b-42eb-8737-f7371d91a638
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159069738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2159069738
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3384929951
Short name T155
Test name
Test status
Simulation time 201146032417 ps
CPU time 478.53 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:38:11 PM PDT 24
Peak memory 202100 kb
Host smart-b013ffb4-6afc-40c4-bc9c-5e039e32127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384929951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3384929951
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1587952093
Short name T449
Test name
Test status
Simulation time 162631900408 ps
CPU time 205.85 seconds
Started Aug 17 05:30:09 PM PDT 24
Finished Aug 17 05:33:35 PM PDT 24
Peak memory 202048 kb
Host smart-fd2effe2-9aff-4bbf-a645-8402d91fc357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587952093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1587952093
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.156783347
Short name T420
Test name
Test status
Simulation time 498160254985 ps
CPU time 308.29 seconds
Started Aug 17 05:30:08 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 202036 kb
Host smart-a40efdd3-7e31-4184-b8fb-cb5aa758ab25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=156783347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.156783347
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3595126420
Short name T317
Test name
Test status
Simulation time 332568271830 ps
CPU time 69.17 seconds
Started Aug 17 05:30:08 PM PDT 24
Finished Aug 17 05:31:18 PM PDT 24
Peak memory 202052 kb
Host smart-9a7697cd-5072-4aac-8c12-514b4404200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595126420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3595126420
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2893083244
Short name T596
Test name
Test status
Simulation time 326374695617 ps
CPU time 181.61 seconds
Started Aug 17 05:30:08 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 202092 kb
Host smart-f895f4a6-d407-4e96-93b4-999bc46228ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893083244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2893083244
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1753798930
Short name T175
Test name
Test status
Simulation time 369810215145 ps
CPU time 457.35 seconds
Started Aug 17 05:30:12 PM PDT 24
Finished Aug 17 05:37:50 PM PDT 24
Peak memory 202144 kb
Host smart-72d09cef-6c4f-4a73-8429-58a04b641d3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753798930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1753798930
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2327839032
Short name T25
Test name
Test status
Simulation time 197952260837 ps
CPU time 118.56 seconds
Started Aug 17 05:30:12 PM PDT 24
Finished Aug 17 05:32:11 PM PDT 24
Peak memory 202080 kb
Host smart-91473daa-7e69-4fb9-aa79-2b9f4c9a70d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327839032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2327839032
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3180708372
Short name T202
Test name
Test status
Simulation time 105264293825 ps
CPU time 339.66 seconds
Started Aug 17 05:30:12 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 202304 kb
Host smart-e4d841b4-4089-46d4-9fd0-be25365f2b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180708372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3180708372
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3080116231
Short name T671
Test name
Test status
Simulation time 41627534931 ps
CPU time 95.06 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:31:48 PM PDT 24
Peak memory 201944 kb
Host smart-a7d707e0-1329-44ce-8f99-e2c90ce4987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080116231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3080116231
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3658249702
Short name T431
Test name
Test status
Simulation time 5453960746 ps
CPU time 3.81 seconds
Started Aug 17 05:30:14 PM PDT 24
Finished Aug 17 05:30:18 PM PDT 24
Peak memory 201892 kb
Host smart-a90e7936-54c9-4e6b-a57a-2f88875df842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658249702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3658249702
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3088987933
Short name T390
Test name
Test status
Simulation time 6140932628 ps
CPU time 8.06 seconds
Started Aug 17 05:30:07 PM PDT 24
Finished Aug 17 05:30:16 PM PDT 24
Peak memory 201952 kb
Host smart-564c4085-8655-4df6-9878-985ef8bfc9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088987933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3088987933
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3709356279
Short name T641
Test name
Test status
Simulation time 9251811910 ps
CPU time 5.27 seconds
Started Aug 17 05:30:25 PM PDT 24
Finished Aug 17 05:30:30 PM PDT 24
Peak memory 202264 kb
Host smart-d8460e10-ec25-43b5-b80a-44d55600298b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709356279 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3709356279
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1483704865
Short name T108
Test name
Test status
Simulation time 436941603 ps
CPU time 1.17 seconds
Started Aug 17 05:30:20 PM PDT 24
Finished Aug 17 05:30:21 PM PDT 24
Peak memory 201964 kb
Host smart-9aced528-3a74-4bd6-bb3c-69fadca4e80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483704865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1483704865
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3435051600
Short name T713
Test name
Test status
Simulation time 362727470178 ps
CPU time 726.89 seconds
Started Aug 17 05:30:25 PM PDT 24
Finished Aug 17 05:42:32 PM PDT 24
Peak memory 202100 kb
Host smart-d333d65f-1ff6-45d7-a3cd-1a8b055c795e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435051600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3435051600
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.427031856
Short name T230
Test name
Test status
Simulation time 373619380189 ps
CPU time 812.49 seconds
Started Aug 17 05:30:14 PM PDT 24
Finished Aug 17 05:43:46 PM PDT 24
Peak memory 202136 kb
Host smart-32e4ae96-dd9c-4157-ba7c-13d37b41a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427031856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.427031856
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3123363664
Short name T622
Test name
Test status
Simulation time 163371503444 ps
CPU time 385.12 seconds
Started Aug 17 05:30:25 PM PDT 24
Finished Aug 17 05:36:50 PM PDT 24
Peak memory 202088 kb
Host smart-6d0912c8-233e-4e5f-a878-4099dec48383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123363664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3123363664
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.488150786
Short name T646
Test name
Test status
Simulation time 327666224186 ps
CPU time 744.6 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:42:37 PM PDT 24
Peak memory 202232 kb
Host smart-fdfe91a4-e746-4670-be97-904159ab361d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=488150786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.488150786
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.670370364
Short name T338
Test name
Test status
Simulation time 491446858174 ps
CPU time 244.96 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 202116 kb
Host smart-90252c32-c988-43df-a8dd-3fb23dc62900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670370364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.670370364
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1169649519
Short name T509
Test name
Test status
Simulation time 169271241895 ps
CPU time 325.54 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 202128 kb
Host smart-633ec13d-9894-49ee-8f25-da0575f36cbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169649519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1169649519
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1450298205
Short name T583
Test name
Test status
Simulation time 202409469799 ps
CPU time 25.38 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:30:38 PM PDT 24
Peak memory 202060 kb
Host smart-27b0ca08-e5f8-483e-942f-51b33bfc172b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450298205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1450298205
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2038170836
Short name T508
Test name
Test status
Simulation time 396699180119 ps
CPU time 234.99 seconds
Started Aug 17 05:30:17 PM PDT 24
Finished Aug 17 05:34:12 PM PDT 24
Peak memory 202120 kb
Host smart-d649727b-416c-4809-b5d0-0d4d5caf6ff6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038170836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2038170836
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2043150097
Short name T216
Test name
Test status
Simulation time 125618758810 ps
CPU time 689.46 seconds
Started Aug 17 05:30:20 PM PDT 24
Finished Aug 17 05:41:50 PM PDT 24
Peak memory 202384 kb
Host smart-21899f38-bbae-4679-a868-a6fe7bea014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043150097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2043150097
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.130052373
Short name T426
Test name
Test status
Simulation time 35770470492 ps
CPU time 82.45 seconds
Started Aug 17 05:30:21 PM PDT 24
Finished Aug 17 05:31:44 PM PDT 24
Peak memory 201940 kb
Host smart-5f24bc87-548f-4951-929a-0e9280af7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130052373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.130052373
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4258162690
Short name T553
Test name
Test status
Simulation time 4260644646 ps
CPU time 3.63 seconds
Started Aug 17 05:30:20 PM PDT 24
Finished Aug 17 05:30:24 PM PDT 24
Peak memory 201924 kb
Host smart-5644a5c9-31f0-4c8a-a928-1ac082b83d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258162690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4258162690
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1106574437
Short name T365
Test name
Test status
Simulation time 5926317343 ps
CPU time 13.17 seconds
Started Aug 17 05:30:13 PM PDT 24
Finished Aug 17 05:30:27 PM PDT 24
Peak memory 201932 kb
Host smart-af99a8c3-1d4f-45a5-8fd7-d1d3bdf11a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106574437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1106574437
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1064322140
Short name T203
Test name
Test status
Simulation time 569150506175 ps
CPU time 621.49 seconds
Started Aug 17 05:30:21 PM PDT 24
Finished Aug 17 05:40:42 PM PDT 24
Peak memory 210472 kb
Host smart-7d3d150d-06ee-475c-be45-64b701f5207c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064322140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1064322140
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.775923306
Short name T769
Test name
Test status
Simulation time 21628097399 ps
CPU time 20.19 seconds
Started Aug 17 05:30:27 PM PDT 24
Finished Aug 17 05:30:47 PM PDT 24
Peak memory 210648 kb
Host smart-4e666ac1-95ff-4f67-bb00-b2b36035f1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775923306 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.775923306
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2784228344
Short name T414
Test name
Test status
Simulation time 311580169 ps
CPU time 0.8 seconds
Started Aug 17 05:30:40 PM PDT 24
Finished Aug 17 05:30:41 PM PDT 24
Peak memory 201924 kb
Host smart-fc50d360-fc6d-4702-8b07-69d8a36083ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784228344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2784228344
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.309940249
Short name T497
Test name
Test status
Simulation time 166380368950 ps
CPU time 398.07 seconds
Started Aug 17 05:30:22 PM PDT 24
Finished Aug 17 05:37:01 PM PDT 24
Peak memory 202132 kb
Host smart-7824ef0c-3c3e-4c84-a808-bb4303770969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309940249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.309940249
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3187380713
Short name T501
Test name
Test status
Simulation time 161652236348 ps
CPU time 200.71 seconds
Started Aug 17 05:30:27 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 202128 kb
Host smart-0babe871-a506-4e7a-811c-39de37955af2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187380713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3187380713
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.643035244
Short name T265
Test name
Test status
Simulation time 166843700179 ps
CPU time 45.62 seconds
Started Aug 17 05:30:19 PM PDT 24
Finished Aug 17 05:31:05 PM PDT 24
Peak memory 202108 kb
Host smart-0d947899-e463-47da-a352-7c0f6999479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643035244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.643035244
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1513837907
Short name T667
Test name
Test status
Simulation time 489513457234 ps
CPU time 1200.47 seconds
Started Aug 17 05:30:21 PM PDT 24
Finished Aug 17 05:50:21 PM PDT 24
Peak memory 202124 kb
Host smart-9fcccfbe-2252-4335-b0ea-4f986f12eb75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513837907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1513837907
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3876042115
Short name T246
Test name
Test status
Simulation time 514681046034 ps
CPU time 577.6 seconds
Started Aug 17 05:30:21 PM PDT 24
Finished Aug 17 05:39:59 PM PDT 24
Peak memory 202136 kb
Host smart-1a89d6a5-27ca-4699-89f5-0ae65fe69fd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876042115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3876042115
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.189605777
Short name T61
Test name
Test status
Simulation time 595111103415 ps
CPU time 1326.77 seconds
Started Aug 17 05:30:22 PM PDT 24
Finished Aug 17 05:52:29 PM PDT 24
Peak memory 202044 kb
Host smart-95d92223-0e88-4d6e-9d07-3c06b1e2412f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189605777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.189605777
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2313367438
Short name T204
Test name
Test status
Simulation time 131235938933 ps
CPU time 432.05 seconds
Started Aug 17 05:30:34 PM PDT 24
Finished Aug 17 05:37:46 PM PDT 24
Peak memory 202384 kb
Host smart-86ef8b25-d00b-416b-adfd-5d3bdf3903e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313367438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2313367438
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.474783343
Short name T387
Test name
Test status
Simulation time 24639472404 ps
CPU time 3.59 seconds
Started Aug 17 05:30:32 PM PDT 24
Finished Aug 17 05:30:36 PM PDT 24
Peak memory 201940 kb
Host smart-c1ab2adc-d50f-4b79-a4f1-56700c0ffe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474783343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.474783343
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2128531011
Short name T439
Test name
Test status
Simulation time 3564957371 ps
CPU time 8.71 seconds
Started Aug 17 05:30:40 PM PDT 24
Finished Aug 17 05:30:49 PM PDT 24
Peak memory 201912 kb
Host smart-badb0b38-6904-4dd5-a70a-6af81a34b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128531011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2128531011
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2220608822
Short name T113
Test name
Test status
Simulation time 5673116893 ps
CPU time 7.68 seconds
Started Aug 17 05:30:27 PM PDT 24
Finished Aug 17 05:30:35 PM PDT 24
Peak memory 201916 kb
Host smart-105fff71-849d-47ef-bead-ecfae7c3fb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220608822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2220608822
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2816925981
Short name T627
Test name
Test status
Simulation time 175119738210 ps
CPU time 39.56 seconds
Started Aug 17 05:30:34 PM PDT 24
Finished Aug 17 05:31:13 PM PDT 24
Peak memory 202136 kb
Host smart-1abc38c2-faa9-4057-81e4-bdf20f6a99f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816925981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2816925981
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1109086755
Short name T199
Test name
Test status
Simulation time 5209104945 ps
CPU time 16.05 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:30:56 PM PDT 24
Peak memory 210644 kb
Host smart-54250364-37b9-4319-9cc7-8e88e7eb7151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109086755 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1109086755
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2140166164
Short name T445
Test name
Test status
Simulation time 477840520 ps
CPU time 1.42 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:12 PM PDT 24
Peak memory 201972 kb
Host smart-51b95922-6021-4fd8-bf4c-0815d53194d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140166164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2140166164
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4074258362
Short name T581
Test name
Test status
Simulation time 165359696401 ps
CPU time 364.06 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 202192 kb
Host smart-e56ee67a-7b2e-4456-9653-4ba3b21b20a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074258362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4074258362
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.826073606
Short name T30
Test name
Test status
Simulation time 503655367899 ps
CPU time 238.25 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:32:08 PM PDT 24
Peak memory 202188 kb
Host smart-a5ea1ca2-3ab9-4db1-bc2b-93e264029cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826073606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.826073606
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3317894849
Short name T324
Test name
Test status
Simulation time 493676227990 ps
CPU time 559.05 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:37:43 PM PDT 24
Peak memory 202136 kb
Host smart-5ab92b4c-73fa-4dfb-bcf1-bee0889e18dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317894849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3317894849
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2252811949
Short name T473
Test name
Test status
Simulation time 492494377708 ps
CPU time 1097.2 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:46:29 PM PDT 24
Peak memory 202172 kb
Host smart-29e48293-8029-4fef-b46a-6b306920038e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252811949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2252811949
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1220293850
Short name T441
Test name
Test status
Simulation time 321783172396 ps
CPU time 721.09 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:40:12 PM PDT 24
Peak memory 202148 kb
Host smart-d1bca975-e109-4ac2-8ffe-03d5392a5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220293850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1220293850
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2734060970
Short name T731
Test name
Test status
Simulation time 320784813817 ps
CPU time 174.29 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:31:04 PM PDT 24
Peak memory 202092 kb
Host smart-d7970975-be87-4f40-b1f8-3a9a9e7cbb72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734060970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2734060970
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1392876758
Short name T744
Test name
Test status
Simulation time 560072103276 ps
CPU time 312.26 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:33:20 PM PDT 24
Peak memory 202040 kb
Host smart-c1198cf9-1f47-443b-bd93-4ce04759c933
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392876758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1392876758
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3869722071
Short name T724
Test name
Test status
Simulation time 193715485505 ps
CPU time 123.33 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:30:13 PM PDT 24
Peak memory 202124 kb
Host smart-9241b3c3-7ff2-42e0-b9c0-b924809606bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869722071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3869722071
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1728704483
Short name T680
Test name
Test status
Simulation time 23015782698 ps
CPU time 48.98 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:29:00 PM PDT 24
Peak memory 201952 kb
Host smart-d5472090-87f3-48d3-84eb-0db6d45c321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728704483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1728704483
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3755898410
Short name T566
Test name
Test status
Simulation time 5299249418 ps
CPU time 3.67 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 201868 kb
Host smart-2324cd2b-a8f0-45f2-b51c-e95ef5fe7ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755898410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3755898410
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.884063446
Short name T90
Test name
Test status
Simulation time 3841818402 ps
CPU time 10.18 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:28:21 PM PDT 24
Peak memory 217480 kb
Host smart-c7f32160-f424-4927-a96b-d69e7bb86416
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884063446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.884063446
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3808208426
Short name T608
Test name
Test status
Simulation time 5712579306 ps
CPU time 14.1 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:28:23 PM PDT 24
Peak memory 201956 kb
Host smart-0342b215-00db-4451-8619-4b4eef3c1306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808208426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3808208426
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2713396864
Short name T662
Test name
Test status
Simulation time 470642186949 ps
CPU time 896.39 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:43:04 PM PDT 24
Peak memory 213448 kb
Host smart-797015d5-738b-4931-87d0-104e098b9209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713396864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2713396864
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2270384136
Short name T200
Test name
Test status
Simulation time 2327427081 ps
CPU time 7.78 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:28:13 PM PDT 24
Peak memory 202276 kb
Host smart-2fbb338b-748f-4b47-b487-a134ba9a97eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270384136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2270384136
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3168410413
Short name T516
Test name
Test status
Simulation time 452236648 ps
CPU time 0.85 seconds
Started Aug 17 05:30:40 PM PDT 24
Finished Aug 17 05:30:41 PM PDT 24
Peak memory 201968 kb
Host smart-cc86321f-ad1e-46e7-a685-d0b6a6c043e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168410413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3168410413
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1093195025
Short name T645
Test name
Test status
Simulation time 328675338057 ps
CPU time 789.3 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:44:04 PM PDT 24
Peak memory 202188 kb
Host smart-a0b0df53-51c1-414a-a1e4-40fe85d7e797
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093195025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1093195025
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.561147463
Short name T598
Test name
Test status
Simulation time 166636672210 ps
CPU time 103.32 seconds
Started Aug 17 05:30:40 PM PDT 24
Finished Aug 17 05:32:23 PM PDT 24
Peak memory 202108 kb
Host smart-c5fe23e4-5198-4a38-8bf6-183074bbaa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561147463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.561147463
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4233773373
Short name T548
Test name
Test status
Simulation time 324767343385 ps
CPU time 162.53 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:33:22 PM PDT 24
Peak memory 202108 kb
Host smart-753c089c-2597-4158-8b04-f69b53bf952c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233773373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4233773373
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3152257439
Short name T476
Test name
Test status
Simulation time 333215424384 ps
CPU time 69.84 seconds
Started Aug 17 05:30:33 PM PDT 24
Finished Aug 17 05:31:43 PM PDT 24
Peak memory 202112 kb
Host smart-7aba5680-62c5-4ff6-af28-9e0ffaf95994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152257439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3152257439
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2531267453
Short name T639
Test name
Test status
Simulation time 494106212425 ps
CPU time 1126.03 seconds
Started Aug 17 05:30:33 PM PDT 24
Finished Aug 17 05:49:20 PM PDT 24
Peak memory 202016 kb
Host smart-4645819e-18f3-4217-9fcc-cf2bd3a77f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531267453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2531267453
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3990722402
Short name T591
Test name
Test status
Simulation time 390133168228 ps
CPU time 948.19 seconds
Started Aug 17 05:30:31 PM PDT 24
Finished Aug 17 05:46:20 PM PDT 24
Peak memory 202088 kb
Host smart-f748919a-d989-41ab-93af-aec03b967f41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990722402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3990722402
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2866902841
Short name T461
Test name
Test status
Simulation time 207764731755 ps
CPU time 490.13 seconds
Started Aug 17 05:30:33 PM PDT 24
Finished Aug 17 05:38:43 PM PDT 24
Peak memory 202124 kb
Host smart-bb1f20bd-9251-4f95-9b71-bf093b7af594
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866902841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2866902841
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1621655666
Short name T663
Test name
Test status
Simulation time 72463434014 ps
CPU time 371.08 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:36:51 PM PDT 24
Peak memory 202356 kb
Host smart-3ca3b6b9-2650-49b4-9ae3-1bff604e0a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621655666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1621655666
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2998243162
Short name T446
Test name
Test status
Simulation time 45525470029 ps
CPU time 104.51 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:32:24 PM PDT 24
Peak memory 201968 kb
Host smart-b7cdbcab-29f6-4790-9231-530fc1ce04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998243162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2998243162
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.499518976
Short name T93
Test name
Test status
Simulation time 4441372711 ps
CPU time 10.08 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:31:05 PM PDT 24
Peak memory 201952 kb
Host smart-ec622560-d7cb-4678-8ffe-938ae32ad771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499518976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.499518976
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3783118719
Short name T356
Test name
Test status
Simulation time 5770518779 ps
CPU time 4.1 seconds
Started Aug 17 05:30:33 PM PDT 24
Finished Aug 17 05:30:37 PM PDT 24
Peak memory 201976 kb
Host smart-87b94b2a-d16d-4a26-8a4c-d27a8270d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783118719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3783118719
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1863857645
Short name T337
Test name
Test status
Simulation time 668794681521 ps
CPU time 293.92 seconds
Started Aug 17 05:30:40 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 202060 kb
Host smart-fe369117-1002-4d7f-9ec2-d5c63e62ace9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863857645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1863857645
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.879190171
Short name T47
Test name
Test status
Simulation time 6350014987 ps
CPU time 3.69 seconds
Started Aug 17 05:30:42 PM PDT 24
Finished Aug 17 05:30:46 PM PDT 24
Peak memory 202104 kb
Host smart-2d19a408-f6d8-4675-891b-f96356e119c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879190171 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.879190171
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.94576338
Short name T514
Test name
Test status
Simulation time 364595756 ps
CPU time 0.82 seconds
Started Aug 17 05:30:46 PM PDT 24
Finished Aug 17 05:30:47 PM PDT 24
Peak memory 201896 kb
Host smart-5176721c-b4a8-4b9a-85b6-be0b46dd4ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94576338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.94576338
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3034854317
Short name T272
Test name
Test status
Simulation time 338194840094 ps
CPU time 398.38 seconds
Started Aug 17 05:30:41 PM PDT 24
Finished Aug 17 05:37:19 PM PDT 24
Peak memory 202036 kb
Host smart-25280623-3437-4b24-989a-d9ea056e1b9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034854317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3034854317
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2404796668
Short name T283
Test name
Test status
Simulation time 166227380309 ps
CPU time 400.61 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:37:20 PM PDT 24
Peak memory 202180 kb
Host smart-6078288e-edfd-4fe3-9b35-f63509fb8bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404796668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2404796668
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1581837515
Short name T256
Test name
Test status
Simulation time 326712851043 ps
CPU time 684.03 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:42:19 PM PDT 24
Peak memory 202124 kb
Host smart-cf5f2d99-3a3c-487a-aff5-1626438192b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581837515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1581837515
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2422455903
Short name T64
Test name
Test status
Simulation time 492311256713 ps
CPU time 315.32 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:35:54 PM PDT 24
Peak memory 202124 kb
Host smart-1b5dafd3-0b78-4cec-ab71-7dba31e11bd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422455903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2422455903
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.678943771
Short name T295
Test name
Test status
Simulation time 333882880921 ps
CPU time 595.58 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:40:50 PM PDT 24
Peak memory 202124 kb
Host smart-7e2bb6b0-5a57-4012-8c84-d780bbaa7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678943771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.678943771
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2719466924
Short name T504
Test name
Test status
Simulation time 156812765541 ps
CPU time 89.64 seconds
Started Aug 17 05:30:41 PM PDT 24
Finished Aug 17 05:32:10 PM PDT 24
Peak memory 202120 kb
Host smart-a0f874e2-1ef8-4b54-9903-e8f07c670777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719466924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2719466924
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.66689613
Short name T580
Test name
Test status
Simulation time 350276666752 ps
CPU time 857.33 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:45:12 PM PDT 24
Peak memory 202124 kb
Host smart-53b98fb3-970d-48b3-a5d6-462080da7937
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66689613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_w
akeup.66689613
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3863388323
Short name T104
Test name
Test status
Simulation time 404037427966 ps
CPU time 463.02 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:38:22 PM PDT 24
Peak memory 202060 kb
Host smart-e11cb58e-804b-4b48-94b1-938c105c931b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863388323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3863388323
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.442780351
Short name T593
Test name
Test status
Simulation time 90800090396 ps
CPU time 472.54 seconds
Started Aug 17 05:30:46 PM PDT 24
Finished Aug 17 05:38:38 PM PDT 24
Peak memory 202384 kb
Host smart-751cfd58-fc1e-436b-b359-9a3b5adc37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442780351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.442780351
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1804600347
Short name T562
Test name
Test status
Simulation time 41641257263 ps
CPU time 50.86 seconds
Started Aug 17 05:30:46 PM PDT 24
Finished Aug 17 05:31:37 PM PDT 24
Peak memory 201948 kb
Host smart-daf3853d-4c36-437b-90a1-93983860c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804600347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1804600347
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2234342885
Short name T534
Test name
Test status
Simulation time 3521440474 ps
CPU time 2 seconds
Started Aug 17 05:30:45 PM PDT 24
Finished Aug 17 05:30:47 PM PDT 24
Peak memory 201936 kb
Host smart-437bfaff-8ba6-434c-8a88-57bbe68983ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234342885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2234342885
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1338715982
Short name T428
Test name
Test status
Simulation time 5922681990 ps
CPU time 7.74 seconds
Started Aug 17 05:30:39 PM PDT 24
Finished Aug 17 05:30:47 PM PDT 24
Peak memory 201916 kb
Host smart-e1d9c2d7-9a10-4caa-bae6-b60d3faed133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338715982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1338715982
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2410176577
Short name T289
Test name
Test status
Simulation time 632584310216 ps
CPU time 936.98 seconds
Started Aug 17 05:30:46 PM PDT 24
Finished Aug 17 05:46:23 PM PDT 24
Peak memory 210604 kb
Host smart-f6e1cd9f-4771-4f58-b78f-fc78b26008a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410176577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2410176577
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1737596340
Short name T279
Test name
Test status
Simulation time 16248564996 ps
CPU time 9.13 seconds
Started Aug 17 05:30:47 PM PDT 24
Finished Aug 17 05:30:56 PM PDT 24
Peak memory 210432 kb
Host smart-68216e36-e966-48ea-816d-98c2ea6d2375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737596340 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1737596340
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2190802871
Short name T467
Test name
Test status
Simulation time 380985404 ps
CPU time 0.86 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:30:54 PM PDT 24
Peak memory 201972 kb
Host smart-2c6f9a18-e4f4-466f-b7d8-0fe42a1c92af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190802871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2190802871
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3731428260
Short name T533
Test name
Test status
Simulation time 177551672037 ps
CPU time 64.88 seconds
Started Aug 17 05:30:52 PM PDT 24
Finished Aug 17 05:31:57 PM PDT 24
Peak memory 202176 kb
Host smart-c339a66e-3f76-487a-90ea-9cc14145afc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731428260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3731428260
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1074192083
Short name T331
Test name
Test status
Simulation time 556734778137 ps
CPU time 112.94 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:32:46 PM PDT 24
Peak memory 202120 kb
Host smart-eb752c33-6836-43cd-9612-d7ae54c42fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074192083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1074192083
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3361661598
Short name T558
Test name
Test status
Simulation time 324076125462 ps
CPU time 290.44 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 202140 kb
Host smart-07f979c4-5426-4c05-b21d-3ff6ec5e7e8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361661598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3361661598
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3329698703
Short name T288
Test name
Test status
Simulation time 167958603265 ps
CPU time 201.73 seconds
Started Aug 17 05:30:47 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 202008 kb
Host smart-6861484d-a7aa-40c6-b4d9-ff3774d235dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329698703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3329698703
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2523397860
Short name T481
Test name
Test status
Simulation time 166730087880 ps
CPU time 395.63 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:37:31 PM PDT 24
Peak memory 202128 kb
Host smart-9f922f50-6f41-4d69-9999-c772aab25ab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523397860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2523397860
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.729693000
Short name T224
Test name
Test status
Simulation time 177872170052 ps
CPU time 392.39 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:37:27 PM PDT 24
Peak memory 202136 kb
Host smart-bb4b88a3-c5ba-41c2-88d5-1922bea4a048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729693000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.729693000
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3186780703
Short name T761
Test name
Test status
Simulation time 401108456703 ps
CPU time 848.4 seconds
Started Aug 17 05:30:54 PM PDT 24
Finished Aug 17 05:45:02 PM PDT 24
Peak memory 202076 kb
Host smart-8ef99567-16f0-485a-b9cd-e634ce241080
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186780703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3186780703
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.32069158
Short name T543
Test name
Test status
Simulation time 107649621865 ps
CPU time 431.52 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:38:05 PM PDT 24
Peak memory 202360 kb
Host smart-75a1a2b7-dd53-4ec6-a7c1-75ef70f2391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32069158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.32069158
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2760636940
Short name T507
Test name
Test status
Simulation time 37887783919 ps
CPU time 21.47 seconds
Started Aug 17 05:30:55 PM PDT 24
Finished Aug 17 05:31:16 PM PDT 24
Peak memory 201968 kb
Host smart-525546a8-9bbc-4a72-90a6-3a2752c7a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760636940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2760636940
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2210184896
Short name T372
Test name
Test status
Simulation time 5285139448 ps
CPU time 9.25 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:31:03 PM PDT 24
Peak memory 201860 kb
Host smart-1071d260-0e43-4dc3-a126-a0f91fe6059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210184896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2210184896
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1987468133
Short name T780
Test name
Test status
Simulation time 5956816256 ps
CPU time 7.04 seconds
Started Aug 17 05:30:46 PM PDT 24
Finished Aug 17 05:30:53 PM PDT 24
Peak memory 201944 kb
Host smart-2b34b9a3-6401-456a-a0fb-f4fc3b3e97d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987468133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1987468133
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1687061988
Short name T455
Test name
Test status
Simulation time 5130682177 ps
CPU time 7.78 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:31:01 PM PDT 24
Peak memory 210464 kb
Host smart-ee6645d9-d815-43ab-b4fb-8dc67c82c05f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687061988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1687061988
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4283697042
Short name T698
Test name
Test status
Simulation time 507370872 ps
CPU time 0.97 seconds
Started Aug 17 05:31:01 PM PDT 24
Finished Aug 17 05:31:02 PM PDT 24
Peak memory 201968 kb
Host smart-0e38e026-549f-4539-b9e0-34cf942c6a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283697042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4283697042
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3884315906
Short name T685
Test name
Test status
Simulation time 498647792976 ps
CPU time 1096.83 seconds
Started Aug 17 05:31:02 PM PDT 24
Finished Aug 17 05:49:19 PM PDT 24
Peak memory 202092 kb
Host smart-02169a2e-fe4d-4c09-bbfc-4fd8252acef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884315906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3884315906
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.397998920
Short name T656
Test name
Test status
Simulation time 487195122921 ps
CPU time 290.05 seconds
Started Aug 17 05:31:02 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 202092 kb
Host smart-142c1fa4-31d4-44ce-8875-cd00d2875ac2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=397998920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.397998920
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1465124937
Short name T8
Test name
Test status
Simulation time 162074672369 ps
CPU time 97.93 seconds
Started Aug 17 05:31:10 PM PDT 24
Finished Aug 17 05:32:48 PM PDT 24
Peak memory 202128 kb
Host smart-866366a4-adac-4407-80f4-69310747446b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465124937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1465124937
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1083056267
Short name T51
Test name
Test status
Simulation time 627800366573 ps
CPU time 371.72 seconds
Started Aug 17 05:31:00 PM PDT 24
Finished Aug 17 05:37:12 PM PDT 24
Peak memory 202092 kb
Host smart-fe4d88c3-8ca1-4eb9-b237-77ffff1a24ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083056267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1083056267
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1809675905
Short name T413
Test name
Test status
Simulation time 382604844749 ps
CPU time 853.41 seconds
Started Aug 17 05:31:00 PM PDT 24
Finished Aug 17 05:45:14 PM PDT 24
Peak memory 202028 kb
Host smart-1d713dbc-b525-4da0-ab46-81c2522e9016
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809675905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1809675905
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2881882479
Short name T350
Test name
Test status
Simulation time 118197875070 ps
CPU time 440.15 seconds
Started Aug 17 05:31:01 PM PDT 24
Finished Aug 17 05:38:21 PM PDT 24
Peak memory 202380 kb
Host smart-a68775d6-f96d-4b18-9832-337c6bc4501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881882479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2881882479
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1263893360
Short name T561
Test name
Test status
Simulation time 38211073026 ps
CPU time 11.49 seconds
Started Aug 17 05:31:01 PM PDT 24
Finished Aug 17 05:31:12 PM PDT 24
Peak memory 201916 kb
Host smart-de1f8160-4369-4f1a-888a-e13c7d8660d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263893360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1263893360
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1337618140
Short name T465
Test name
Test status
Simulation time 2676755950 ps
CPU time 1.65 seconds
Started Aug 17 05:31:00 PM PDT 24
Finished Aug 17 05:31:02 PM PDT 24
Peak memory 201944 kb
Host smart-9c4c1e66-cb95-4ecb-984f-79fcb01e8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337618140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1337618140
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3272032967
Short name T650
Test name
Test status
Simulation time 5740294437 ps
CPU time 7.2 seconds
Started Aug 17 05:30:53 PM PDT 24
Finished Aug 17 05:31:00 PM PDT 24
Peak memory 201952 kb
Host smart-6a05296c-687c-48b0-a503-1360499043fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272032967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3272032967
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.277920385
Short name T165
Test name
Test status
Simulation time 502568472625 ps
CPU time 1186.08 seconds
Started Aug 17 05:31:02 PM PDT 24
Finished Aug 17 05:50:48 PM PDT 24
Peak memory 202064 kb
Host smart-3d65acde-65a9-428f-a935-193faf90b3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277920385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
277920385
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3677425921
Short name T460
Test name
Test status
Simulation time 339873060 ps
CPU time 1.32 seconds
Started Aug 17 05:31:17 PM PDT 24
Finished Aug 17 05:31:19 PM PDT 24
Peak memory 201992 kb
Host smart-0afe0d45-16ec-4629-800c-162dab7285b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677425921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3677425921
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2052481926
Short name T164
Test name
Test status
Simulation time 161718101217 ps
CPU time 60.26 seconds
Started Aug 17 05:31:08 PM PDT 24
Finished Aug 17 05:32:08 PM PDT 24
Peak memory 202140 kb
Host smart-d5f00cf0-7adf-4c63-8585-3cba52db7028
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052481926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2052481926
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.855552325
Short name T287
Test name
Test status
Simulation time 557538685289 ps
CPU time 109.13 seconds
Started Aug 17 05:31:17 PM PDT 24
Finished Aug 17 05:33:06 PM PDT 24
Peak memory 202064 kb
Host smart-1d1bf878-731a-4603-a266-55d58efe289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855552325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.855552325
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1477718187
Short name T158
Test name
Test status
Simulation time 490977957163 ps
CPU time 276.99 seconds
Started Aug 17 05:31:08 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 202212 kb
Host smart-f5553bb5-6737-4662-8096-4e53abf05c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477718187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1477718187
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2409985997
Short name T758
Test name
Test status
Simulation time 163068477076 ps
CPU time 181.01 seconds
Started Aug 17 05:31:07 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 202180 kb
Host smart-9cf3cd1d-4ff2-4833-86e6-dfac161fcb9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409985997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2409985997
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4030793644
Short name T163
Test name
Test status
Simulation time 158428212146 ps
CPU time 174.21 seconds
Started Aug 17 05:31:08 PM PDT 24
Finished Aug 17 05:34:02 PM PDT 24
Peak memory 202120 kb
Host smart-3597fb5a-30ca-46eb-b793-e500eb57f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030793644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4030793644
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1439267507
Short name T412
Test name
Test status
Simulation time 158060606077 ps
CPU time 338.93 seconds
Started Aug 17 05:31:07 PM PDT 24
Finished Aug 17 05:36:46 PM PDT 24
Peak memory 202104 kb
Host smart-da2431a8-3b78-44aa-b708-79f5c6dc6a10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439267507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1439267507
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2818303062
Short name T3
Test name
Test status
Simulation time 341769634994 ps
CPU time 202.08 seconds
Started Aug 17 05:31:08 PM PDT 24
Finished Aug 17 05:34:30 PM PDT 24
Peak memory 202112 kb
Host smart-752c5515-07e2-4900-8d61-70d58dc7de39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818303062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2818303062
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.36089369
Short name T692
Test name
Test status
Simulation time 602265857752 ps
CPU time 701.59 seconds
Started Aug 17 05:31:08 PM PDT 24
Finished Aug 17 05:42:50 PM PDT 24
Peak memory 202128 kb
Host smart-b07f3329-58e1-4ca2-83b1-168eb808f0df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36089369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.a
dc_ctrl_filters_wakeup_fixed.36089369
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.668070255
Short name T696
Test name
Test status
Simulation time 101035531139 ps
CPU time 413.07 seconds
Started Aug 17 05:31:17 PM PDT 24
Finished Aug 17 05:38:10 PM PDT 24
Peak memory 202384 kb
Host smart-bd94b9c7-cd18-453d-a19b-5bcef705ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668070255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.668070255
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.196652836
Short name T612
Test name
Test status
Simulation time 22867448632 ps
CPU time 3.96 seconds
Started Aug 17 05:31:15 PM PDT 24
Finished Aug 17 05:31:19 PM PDT 24
Peak memory 201876 kb
Host smart-77cad4ba-1a22-4126-bbac-b9c4ae0d73d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196652836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.196652836
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.624083693
Short name T576
Test name
Test status
Simulation time 3061553673 ps
CPU time 2.43 seconds
Started Aug 17 05:31:15 PM PDT 24
Finished Aug 17 05:31:17 PM PDT 24
Peak memory 202008 kb
Host smart-2e06fa35-2c44-4837-9d32-b0c7828c7324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624083693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.624083693
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1807578571
Short name T375
Test name
Test status
Simulation time 5922728403 ps
CPU time 13.64 seconds
Started Aug 17 05:31:10 PM PDT 24
Finished Aug 17 05:31:24 PM PDT 24
Peak memory 201916 kb
Host smart-ac61c922-0aed-4dd0-b313-6ae421c5aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807578571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1807578571
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1083559796
Short name T568
Test name
Test status
Simulation time 168793808206 ps
CPU time 203.65 seconds
Started Aug 17 05:31:17 PM PDT 24
Finished Aug 17 05:34:41 PM PDT 24
Peak memory 202068 kb
Host smart-b6df3c17-c897-4299-815d-71f2e314c21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083559796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1083559796
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2676515073
Short name T421
Test name
Test status
Simulation time 2663778836 ps
CPU time 6.37 seconds
Started Aug 17 05:31:16 PM PDT 24
Finished Aug 17 05:31:23 PM PDT 24
Peak memory 202008 kb
Host smart-e4dcc1d8-ba3e-4068-bfbd-236c3ce620f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676515073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2676515073
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.931449524
Short name T719
Test name
Test status
Simulation time 455302035 ps
CPU time 0.85 seconds
Started Aug 17 05:31:22 PM PDT 24
Finished Aug 17 05:31:23 PM PDT 24
Peak memory 201868 kb
Host smart-0a98d0d8-f2b8-45c3-90a4-3b18ffacf238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931449524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.931449524
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3256863962
Short name T154
Test name
Test status
Simulation time 183976540766 ps
CPU time 422.92 seconds
Started Aug 17 05:31:24 PM PDT 24
Finished Aug 17 05:38:27 PM PDT 24
Peak memory 202064 kb
Host smart-fe00e738-767e-49df-9a63-ec70a165475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256863962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3256863962
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3310480455
Short name T480
Test name
Test status
Simulation time 164611356578 ps
CPU time 306.65 seconds
Started Aug 17 05:31:24 PM PDT 24
Finished Aug 17 05:36:31 PM PDT 24
Peak memory 202108 kb
Host smart-9be37ed4-20e2-472f-9970-fa364a68477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310480455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3310480455
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.258484825
Short name T397
Test name
Test status
Simulation time 163009242419 ps
CPU time 394.18 seconds
Started Aug 17 05:31:23 PM PDT 24
Finished Aug 17 05:37:57 PM PDT 24
Peak memory 202160 kb
Host smart-b8e02709-5ddd-4a38-ac92-ae7b0d61636a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=258484825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.258484825
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.948247685
Short name T302
Test name
Test status
Simulation time 327173340213 ps
CPU time 138.31 seconds
Started Aug 17 05:31:15 PM PDT 24
Finished Aug 17 05:33:33 PM PDT 24
Peak memory 202124 kb
Host smart-b38d99f9-e566-4b97-b68b-4c9aae52522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948247685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.948247685
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1456321147
Short name T554
Test name
Test status
Simulation time 489934886508 ps
CPU time 572.56 seconds
Started Aug 17 05:31:23 PM PDT 24
Finished Aug 17 05:40:55 PM PDT 24
Peak memory 202100 kb
Host smart-1e168c51-a09c-4215-9b66-fcd3004a7eb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456321147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1456321147
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.738506266
Short name T336
Test name
Test status
Simulation time 209943630702 ps
CPU time 96.01 seconds
Started Aug 17 05:31:22 PM PDT 24
Finished Aug 17 05:32:58 PM PDT 24
Peak memory 202116 kb
Host smart-3ffb4912-2511-4d58-871b-4df78415a540
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738506266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.738506266
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1153880339
Short name T586
Test name
Test status
Simulation time 597101272750 ps
CPU time 205.61 seconds
Started Aug 17 05:31:24 PM PDT 24
Finished Aug 17 05:34:50 PM PDT 24
Peak memory 202084 kb
Host smart-a9f71d05-78a4-4d0c-8e71-858cfae8e8be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153880339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1153880339
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.372353317
Short name T572
Test name
Test status
Simulation time 84784577900 ps
CPU time 311.77 seconds
Started Aug 17 05:31:22 PM PDT 24
Finished Aug 17 05:36:34 PM PDT 24
Peak memory 202388 kb
Host smart-c71ed24f-c664-41e3-8286-eba99bfdf706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372353317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.372353317
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2621564533
Short name T536
Test name
Test status
Simulation time 27199554745 ps
CPU time 62.04 seconds
Started Aug 17 05:31:24 PM PDT 24
Finished Aug 17 05:32:26 PM PDT 24
Peak memory 201972 kb
Host smart-ae0e4b97-b816-4b68-8e7a-50cb05e44bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621564533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2621564533
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3723260099
Short name T527
Test name
Test status
Simulation time 2853023590 ps
CPU time 2.33 seconds
Started Aug 17 05:31:23 PM PDT 24
Finished Aug 17 05:31:25 PM PDT 24
Peak memory 201940 kb
Host smart-54f2d876-b0af-4932-a836-e976fa44aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723260099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3723260099
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1697721068
Short name T636
Test name
Test status
Simulation time 5816555821 ps
CPU time 3.81 seconds
Started Aug 17 05:31:16 PM PDT 24
Finished Aug 17 05:31:20 PM PDT 24
Peak memory 201916 kb
Host smart-4ba23911-6870-4d2f-b403-c55ee64172e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697721068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1697721068
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2470873914
Short name T32
Test name
Test status
Simulation time 205464979793 ps
CPU time 403.13 seconds
Started Aug 17 05:31:26 PM PDT 24
Finished Aug 17 05:38:09 PM PDT 24
Peak memory 202104 kb
Host smart-99bffaed-bbfd-4f4b-a734-826060208f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470873914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2470873914
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1398815753
Short name T340
Test name
Test status
Simulation time 5472218877 ps
CPU time 9.71 seconds
Started Aug 17 05:31:24 PM PDT 24
Finished Aug 17 05:31:34 PM PDT 24
Peak memory 210376 kb
Host smart-c819d7d4-25bf-44bd-96b8-9cbf90bbe01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398815753 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1398815753
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3930231939
Short name T86
Test name
Test status
Simulation time 383085831 ps
CPU time 0.75 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:31:39 PM PDT 24
Peak memory 201944 kb
Host smart-55b59a82-39f8-46ae-98c1-443e326a7375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930231939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3930231939
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.613139560
Short name T114
Test name
Test status
Simulation time 192898082994 ps
CPU time 364.28 seconds
Started Aug 17 05:31:30 PM PDT 24
Finished Aug 17 05:37:35 PM PDT 24
Peak memory 202140 kb
Host smart-af6cc271-f4b3-40a9-8bf9-ca28795847c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613139560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.613139560
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3011645453
Short name T609
Test name
Test status
Simulation time 162276678537 ps
CPU time 191.64 seconds
Started Aug 17 05:31:31 PM PDT 24
Finished Aug 17 05:34:42 PM PDT 24
Peak memory 202140 kb
Host smart-20782f49-2bb5-41fa-ad2b-5fd5601d3b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011645453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3011645453
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3381689345
Short name T760
Test name
Test status
Simulation time 166908428999 ps
CPU time 99.15 seconds
Started Aug 17 05:31:31 PM PDT 24
Finished Aug 17 05:33:10 PM PDT 24
Peak memory 202120 kb
Host smart-6793bc0a-db57-4e2b-bdcf-ce935803f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381689345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3381689345
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3153364953
Short name T456
Test name
Test status
Simulation time 326270039856 ps
CPU time 628.1 seconds
Started Aug 17 05:31:33 PM PDT 24
Finished Aug 17 05:42:01 PM PDT 24
Peak memory 201984 kb
Host smart-47322dd7-04a1-47de-a3a6-9fdeebcaa821
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153364953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3153364953
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2172559809
Short name T618
Test name
Test status
Simulation time 488564038496 ps
CPU time 288.66 seconds
Started Aug 17 05:31:30 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 202292 kb
Host smart-622acaaf-e477-489d-9303-64651d96aecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172559809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2172559809
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1794152415
Short name T450
Test name
Test status
Simulation time 328772037045 ps
CPU time 97.4 seconds
Started Aug 17 05:31:30 PM PDT 24
Finished Aug 17 05:33:07 PM PDT 24
Peak memory 202084 kb
Host smart-27551e7e-d361-40d3-a237-1146ab973ebd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794152415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1794152415
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1973167739
Short name T326
Test name
Test status
Simulation time 572144995838 ps
CPU time 1304.51 seconds
Started Aug 17 05:31:31 PM PDT 24
Finished Aug 17 05:53:16 PM PDT 24
Peak memory 202116 kb
Host smart-61a23879-6cbd-4e97-bad6-4b71ca10c8a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973167739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1973167739
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2034297816
Short name T665
Test name
Test status
Simulation time 583266936510 ps
CPU time 199.17 seconds
Started Aug 17 05:31:30 PM PDT 24
Finished Aug 17 05:34:49 PM PDT 24
Peak memory 202124 kb
Host smart-67d0b6c9-b65a-434f-9742-226374fa1d60
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034297816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2034297816
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.818951726
Short name T732
Test name
Test status
Simulation time 74344485338 ps
CPU time 245.04 seconds
Started Aug 17 05:31:31 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 202432 kb
Host smart-669829fd-ec05-4cfa-9aff-d6d5af6a02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818951726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.818951726
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.658381572
Short name T171
Test name
Test status
Simulation time 36480645485 ps
CPU time 14.85 seconds
Started Aug 17 05:31:31 PM PDT 24
Finished Aug 17 05:31:46 PM PDT 24
Peak memory 201912 kb
Host smart-f7fe03fc-0300-498e-911b-3eb8b9cce978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658381572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.658381572
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1953942483
Short name T410
Test name
Test status
Simulation time 3379375136 ps
CPU time 4.73 seconds
Started Aug 17 05:31:32 PM PDT 24
Finished Aug 17 05:31:36 PM PDT 24
Peak memory 201904 kb
Host smart-0dd5d21f-f642-45ea-b3c4-c49e4f46b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953942483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1953942483
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1278531795
Short name T616
Test name
Test status
Simulation time 6130408176 ps
CPU time 7.63 seconds
Started Aug 17 05:31:30 PM PDT 24
Finished Aug 17 05:31:38 PM PDT 24
Peak memory 201940 kb
Host smart-ff6fad16-2856-458f-93ca-560234a99624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278531795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1278531795
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.683164823
Short name T60
Test name
Test status
Simulation time 238216772683 ps
CPU time 449.65 seconds
Started Aug 17 05:31:40 PM PDT 24
Finished Aug 17 05:39:10 PM PDT 24
Peak memory 202096 kb
Host smart-6fc2b007-c132-4e37-b1e5-19249a87018b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683164823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
683164823
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.883366683
Short name T12
Test name
Test status
Simulation time 7385979568 ps
CPU time 5.08 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:31:43 PM PDT 24
Peak memory 202116 kb
Host smart-f0a85e58-8c3a-41a9-a67c-946999ffc581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883366683 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.883366683
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2663191713
Short name T705
Test name
Test status
Simulation time 527902815 ps
CPU time 1.19 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:31:49 PM PDT 24
Peak memory 201884 kb
Host smart-f9c6d0b8-da31-4fd7-8460-422e157420ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663191713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2663191713
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.855574013
Short name T290
Test name
Test status
Simulation time 500720380150 ps
CPU time 206.09 seconds
Started Aug 17 05:31:39 PM PDT 24
Finished Aug 17 05:35:05 PM PDT 24
Peak memory 202160 kb
Host smart-863aa04b-5bfd-4402-be0b-dea11af597c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855574013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.855574013
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4228539897
Short name T183
Test name
Test status
Simulation time 592668868968 ps
CPU time 319.56 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:36:58 PM PDT 24
Peak memory 202128 kb
Host smart-a41b4a9a-7a02-4c25-ab2a-d7654448d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228539897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4228539897
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3068102727
Short name T319
Test name
Test status
Simulation time 161970099119 ps
CPU time 96.74 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:33:15 PM PDT 24
Peak memory 202148 kb
Host smart-9d71fd1a-7f6e-46d7-abb7-3c3ee7f392f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068102727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3068102727
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.323378448
Short name T693
Test name
Test status
Simulation time 164713561678 ps
CPU time 394.54 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:38:13 PM PDT 24
Peak memory 202068 kb
Host smart-a91598b0-ec43-4277-a4dd-d25979ac2777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=323378448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.323378448
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.495377271
Short name T34
Test name
Test status
Simulation time 162267260742 ps
CPU time 354.13 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:37:33 PM PDT 24
Peak memory 202116 kb
Host smart-d226a01d-b57d-4de5-a240-dc0aa6bd7a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495377271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.495377271
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3350441320
Short name T772
Test name
Test status
Simulation time 327925394660 ps
CPU time 706.11 seconds
Started Aug 17 05:31:39 PM PDT 24
Finished Aug 17 05:43:25 PM PDT 24
Peak memory 202060 kb
Host smart-14b82b4d-ef3b-4afc-b883-92167ab4416a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350441320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3350441320
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.615765273
Short name T196
Test name
Test status
Simulation time 607124232235 ps
CPU time 348.35 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:37:27 PM PDT 24
Peak memory 202128 kb
Host smart-e774c0fc-c43f-410e-bd89-b797e4cf5d5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615765273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.615765273
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.754877583
Short name T610
Test name
Test status
Simulation time 203984772410 ps
CPU time 438.29 seconds
Started Aug 17 05:31:38 PM PDT 24
Finished Aug 17 05:38:56 PM PDT 24
Peak memory 202096 kb
Host smart-47de6053-ac48-4c24-999a-5a0812043634
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754877583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.754877583
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3262139235
Short name T707
Test name
Test status
Simulation time 78793402560 ps
CPU time 314.42 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:37:02 PM PDT 24
Peak memory 202396 kb
Host smart-4364ece0-6d88-4ed3-bdf7-688d495d822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262139235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3262139235
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1650254207
Short name T489
Test name
Test status
Simulation time 35985582762 ps
CPU time 75.68 seconds
Started Aug 17 05:31:48 PM PDT 24
Finished Aug 17 05:33:04 PM PDT 24
Peak memory 201936 kb
Host smart-8721139d-c556-48d5-add3-84b6de23d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650254207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1650254207
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1033792876
Short name T720
Test name
Test status
Simulation time 4192414303 ps
CPU time 10.68 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:31:58 PM PDT 24
Peak memory 201900 kb
Host smart-9e25e644-d9ad-4333-82f2-dee5b56bc374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033792876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1033792876
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.835091130
Short name T355
Test name
Test status
Simulation time 5564042545 ps
CPU time 4.44 seconds
Started Aug 17 05:31:40 PM PDT 24
Finished Aug 17 05:31:45 PM PDT 24
Peak memory 201924 kb
Host smart-c547ee22-7d47-4043-8661-5c5092fd8693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835091130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.835091130
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3031042822
Short name T318
Test name
Test status
Simulation time 369931812454 ps
CPU time 807.53 seconds
Started Aug 17 05:31:48 PM PDT 24
Finished Aug 17 05:45:16 PM PDT 24
Peak memory 202140 kb
Host smart-ed70b1b4-668c-4ee3-a84e-c56cf663c78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031042822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3031042822
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.613937798
Short name T19
Test name
Test status
Simulation time 8564924882 ps
CPU time 18.02 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:32:06 PM PDT 24
Peak memory 210484 kb
Host smart-d551877e-52b7-45d4-afed-ced258f71d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613937798 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.613937798
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1260148671
Short name T771
Test name
Test status
Simulation time 319053280 ps
CPU time 0.75 seconds
Started Aug 17 05:31:55 PM PDT 24
Finished Aug 17 05:31:56 PM PDT 24
Peak memory 201956 kb
Host smart-96a00f57-1f19-4fbf-b8ed-625771a795b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260148671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1260148671
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3322226235
Short name T700
Test name
Test status
Simulation time 179264252958 ps
CPU time 68.2 seconds
Started Aug 17 05:31:55 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 202084 kb
Host smart-2ba5eb58-ce24-42fd-ab36-e872c6fc13bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322226235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3322226235
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1915048652
Short name T309
Test name
Test status
Simulation time 282452373340 ps
CPU time 603.57 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:41:58 PM PDT 24
Peak memory 202052 kb
Host smart-acc37ea7-a7b7-4256-95b7-9bf2fbcf960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915048652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1915048652
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4177653280
Short name T592
Test name
Test status
Simulation time 165971269675 ps
CPU time 353.6 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:37:41 PM PDT 24
Peak memory 202128 kb
Host smart-dc4b8203-3c01-4218-bde2-117421632362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177653280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4177653280
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3003731772
Short name T96
Test name
Test status
Simulation time 489035574685 ps
CPU time 292.37 seconds
Started Aug 17 05:31:55 PM PDT 24
Finished Aug 17 05:36:48 PM PDT 24
Peak memory 202116 kb
Host smart-926c9045-ef03-4bd2-ba51-ed63ebd5856e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003731772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3003731772
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3773757879
Short name T225
Test name
Test status
Simulation time 493132035616 ps
CPU time 302.73 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:36:50 PM PDT 24
Peak memory 202048 kb
Host smart-54db5c16-3b50-4ef4-9d92-0d67df8ac995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773757879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3773757879
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3982126235
Short name T493
Test name
Test status
Simulation time 489212461015 ps
CPU time 489.59 seconds
Started Aug 17 05:31:47 PM PDT 24
Finished Aug 17 05:39:57 PM PDT 24
Peak memory 202072 kb
Host smart-f847ec7e-d3e0-4a35-ad07-d34ffe7c1fbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982126235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3982126235
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1842848449
Short name T320
Test name
Test status
Simulation time 362118319083 ps
CPU time 299.72 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:36:53 PM PDT 24
Peak memory 202048 kb
Host smart-2bc47661-dba2-4a05-a492-ffdb530e4ea9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842848449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1842848449
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.840213779
Short name T443
Test name
Test status
Simulation time 607306907233 ps
CPU time 1489.99 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:56:45 PM PDT 24
Peak memory 202124 kb
Host smart-f5fbd912-147c-4233-b5eb-9ef52fed0b99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840213779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.840213779
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4197804029
Short name T551
Test name
Test status
Simulation time 128465136971 ps
CPU time 436.99 seconds
Started Aug 17 05:31:55 PM PDT 24
Finished Aug 17 05:39:13 PM PDT 24
Peak memory 202408 kb
Host smart-c24ae1b8-a105-49f9-a98e-2ee0c8555906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197804029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4197804029
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1160117601
Short name T525
Test name
Test status
Simulation time 42122120405 ps
CPU time 91.57 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:33:26 PM PDT 24
Peak memory 201940 kb
Host smart-2a241aef-3dc0-47a7-a0ab-0837664a4e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160117601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1160117601
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3538237604
Short name T475
Test name
Test status
Simulation time 4450082925 ps
CPU time 2.95 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:31:57 PM PDT 24
Peak memory 201856 kb
Host smart-6b914225-8466-4936-8ec8-957126940ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538237604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3538237604
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2321912678
Short name T694
Test name
Test status
Simulation time 6038708768 ps
CPU time 7.42 seconds
Started Aug 17 05:31:49 PM PDT 24
Finished Aug 17 05:31:57 PM PDT 24
Peak memory 201948 kb
Host smart-b3801829-0163-43ca-a242-e86b72a50879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321912678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2321912678
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.890806847
Short name T524
Test name
Test status
Simulation time 2096978781 ps
CPU time 5.47 seconds
Started Aug 17 05:31:56 PM PDT 24
Finished Aug 17 05:32:02 PM PDT 24
Peak memory 201988 kb
Host smart-0a623d07-a62d-4774-8d8d-0d66540b8c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890806847 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.890806847
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.4220841876
Short name T738
Test name
Test status
Simulation time 420631692 ps
CPU time 1.53 seconds
Started Aug 17 05:32:02 PM PDT 24
Finished Aug 17 05:32:04 PM PDT 24
Peak memory 201992 kb
Host smart-47d0bbd9-2bd3-41e9-bc27-570bf355a9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220841876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.4220841876
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.681307459
Short name T314
Test name
Test status
Simulation time 231227477438 ps
CPU time 427.57 seconds
Started Aug 17 05:32:02 PM PDT 24
Finished Aug 17 05:39:10 PM PDT 24
Peak memory 202156 kb
Host smart-080e570e-b54a-4d1e-aac1-309793c2eeed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681307459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.681307459
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1802584814
Short name T243
Test name
Test status
Simulation time 370384263465 ps
CPU time 416.22 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:38:59 PM PDT 24
Peak memory 202140 kb
Host smart-17818db1-b66c-40e9-8373-ea3844877e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802584814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1802584814
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2546238653
Short name T335
Test name
Test status
Simulation time 326895203700 ps
CPU time 423.73 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:39:07 PM PDT 24
Peak memory 202152 kb
Host smart-72cf73ff-cf38-4289-ae2d-41330552cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546238653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2546238653
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2549719236
Short name T706
Test name
Test status
Simulation time 496506130511 ps
CPU time 306.51 seconds
Started Aug 17 05:32:04 PM PDT 24
Finished Aug 17 05:37:11 PM PDT 24
Peak memory 202156 kb
Host smart-9c7970ea-99d0-4834-a1da-6787fd6065c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549719236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2549719236
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1490624318
Short name T123
Test name
Test status
Simulation time 486285799275 ps
CPU time 63.49 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:32:58 PM PDT 24
Peak memory 202144 kb
Host smart-bb3c9812-4bb7-480c-b300-6c055bb39ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490624318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1490624318
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.821934430
Short name T434
Test name
Test status
Simulation time 159900351099 ps
CPU time 181.69 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:35:05 PM PDT 24
Peak memory 202112 kb
Host smart-6bdbda69-171e-47da-bcf4-e332dbcfb6fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=821934430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.821934430
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1462508478
Short name T293
Test name
Test status
Simulation time 576277076472 ps
CPU time 598.65 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:42:02 PM PDT 24
Peak memory 202016 kb
Host smart-2cfa01d3-0637-4cf1-8be6-9d352772b4a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462508478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1462508478
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1837830182
Short name T722
Test name
Test status
Simulation time 603147101719 ps
CPU time 253.69 seconds
Started Aug 17 05:32:02 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 202124 kb
Host smart-cc5129a1-de65-4af5-9ea3-7975a3027ea5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837830182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1837830182
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.621439947
Short name T67
Test name
Test status
Simulation time 110124398899 ps
CPU time 534.37 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:40:57 PM PDT 24
Peak memory 202380 kb
Host smart-6e247c30-e147-4e1b-a948-e8ffa8999085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621439947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.621439947
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1910787102
Short name T401
Test name
Test status
Simulation time 31842942661 ps
CPU time 38.21 seconds
Started Aug 17 05:32:04 PM PDT 24
Finished Aug 17 05:32:42 PM PDT 24
Peak memory 201896 kb
Host smart-cf436c93-c093-4150-b9d9-b92a2476714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910787102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1910787102
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.537705059
Short name T490
Test name
Test status
Simulation time 2917725947 ps
CPU time 7.72 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:32:11 PM PDT 24
Peak memory 201844 kb
Host smart-e823d614-cf15-4505-8a76-a92954facfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537705059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.537705059
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1554161242
Short name T384
Test name
Test status
Simulation time 5921753353 ps
CPU time 13.38 seconds
Started Aug 17 05:31:54 PM PDT 24
Finished Aug 17 05:32:08 PM PDT 24
Peak memory 201956 kb
Host smart-8f54f3b8-4390-459f-9537-53e2cbb4ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554161242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1554161242
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.426605231
Short name T33
Test name
Test status
Simulation time 202620780662 ps
CPU time 470.74 seconds
Started Aug 17 05:32:02 PM PDT 24
Finished Aug 17 05:39:53 PM PDT 24
Peak memory 202088 kb
Host smart-4727ad6b-2932-4a0e-b009-260049d9d0b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426605231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
426605231
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1703657634
Short name T678
Test name
Test status
Simulation time 4145797896 ps
CPU time 12.61 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:32:16 PM PDT 24
Peak memory 210752 kb
Host smart-8a4122ad-d80c-4a2e-a168-5feb64f5c481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703657634 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1703657634
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3459137254
Short name T403
Test name
Test status
Simulation time 476126911 ps
CPU time 0.91 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:28:10 PM PDT 24
Peak memory 201948 kb
Host smart-3bfa1e8c-b70e-4035-9eaa-025669f340e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459137254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3459137254
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.446862765
Short name T297
Test name
Test status
Simulation time 432149205740 ps
CPU time 116.43 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:30:01 PM PDT 24
Peak memory 202044 kb
Host smart-778577ba-e2fa-4682-ae5b-eb0ba200b779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446862765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.446862765
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2074502922
Short name T149
Test name
Test status
Simulation time 488737138451 ps
CPU time 1152.82 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:47:19 PM PDT 24
Peak memory 202076 kb
Host smart-a8182c3b-e461-40c1-b745-3c340ebce8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074502922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2074502922
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3143081319
Short name T416
Test name
Test status
Simulation time 161963978087 ps
CPU time 52.15 seconds
Started Aug 17 05:28:02 PM PDT 24
Finished Aug 17 05:28:54 PM PDT 24
Peak memory 202116 kb
Host smart-38f6eaec-f9cc-47a0-8675-ffeeab16517c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143081319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3143081319
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3613439404
Short name T280
Test name
Test status
Simulation time 336270303603 ps
CPU time 740.4 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:40:33 PM PDT 24
Peak memory 202116 kb
Host smart-6b41cb7d-3a20-4280-a739-b086e644205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613439404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3613439404
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2178499460
Short name T398
Test name
Test status
Simulation time 320784361145 ps
CPU time 684 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:39:31 PM PDT 24
Peak memory 202100 kb
Host smart-219225c5-1768-4357-8fd4-ae3cc43a358f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178499460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2178499460
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3777181993
Short name T585
Test name
Test status
Simulation time 536073207183 ps
CPU time 353.17 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 202104 kb
Host smart-0dd1dfbb-4ec2-4495-ba85-22869314e547
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777181993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3777181993
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2252533484
Short name T582
Test name
Test status
Simulation time 602786161616 ps
CPU time 1411.54 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:51:40 PM PDT 24
Peak memory 202044 kb
Host smart-2faf0ea1-6695-46f2-ad65-95d4d7a083ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252533484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2252533484
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3946139374
Short name T69
Test name
Test status
Simulation time 83718499498 ps
CPU time 320.74 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 202336 kb
Host smart-25786551-46a2-4cd4-b2a3-04edbb0afefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946139374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3946139374
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2044809021
Short name T734
Test name
Test status
Simulation time 32642220946 ps
CPU time 69.1 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:29:17 PM PDT 24
Peak memory 201848 kb
Host smart-fd387613-bb0d-4aaf-8f9c-f1a45cc72a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044809021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2044809021
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2399235979
Short name T709
Test name
Test status
Simulation time 5452363648 ps
CPU time 6.95 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:28:14 PM PDT 24
Peak memory 201944 kb
Host smart-c7b824f2-6f0c-4815-a9d1-bf51fdf766b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399235979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2399235979
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2469745224
Short name T54
Test name
Test status
Simulation time 6060559351 ps
CPU time 11.26 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:28:25 PM PDT 24
Peak memory 201976 kb
Host smart-1e207339-fc20-43db-889d-dfca726a8a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469745224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2469745224
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3229158067
Short name T792
Test name
Test status
Simulation time 1769882243 ps
CPU time 8.88 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:20 PM PDT 24
Peak memory 202000 kb
Host smart-48e906f5-b9bf-4649-bc2e-c4fba563b5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229158067 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3229158067
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.265689577
Short name T358
Test name
Test status
Simulation time 461436903 ps
CPU time 0.92 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 201960 kb
Host smart-c622733f-2266-4711-85d0-7ccb03249942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265689577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.265689577
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.884133938
Short name T341
Test name
Test status
Simulation time 384504561246 ps
CPU time 181.21 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:31:09 PM PDT 24
Peak memory 202148 kb
Host smart-666f41c7-e823-4262-b589-8a2b7c4f8b1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884133938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.884133938
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2077903929
Short name T153
Test name
Test status
Simulation time 179080721173 ps
CPU time 215.81 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:31:45 PM PDT 24
Peak memory 202024 kb
Host smart-7f157951-fe3f-454a-b628-97328a4354c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077903929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2077903929
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3719301684
Short name T471
Test name
Test status
Simulation time 324802512920 ps
CPU time 631.66 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:38:39 PM PDT 24
Peak memory 202156 kb
Host smart-8d943bca-04ef-4845-ba0b-39305f4a1c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719301684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3719301684
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3352328982
Short name T690
Test name
Test status
Simulation time 324296672906 ps
CPU time 190.83 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:31:14 PM PDT 24
Peak memory 202100 kb
Host smart-63600cc6-4063-4294-88bd-28f9b9ae5b77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352328982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3352328982
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1398906683
Short name T172
Test name
Test status
Simulation time 161820499058 ps
CPU time 143.02 seconds
Started Aug 17 05:28:15 PM PDT 24
Finished Aug 17 05:30:38 PM PDT 24
Peak memory 202112 kb
Host smart-f5d0ead4-a95a-40b4-aa36-41accfb0b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398906683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1398906683
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1075528040
Short name T186
Test name
Test status
Simulation time 320361408155 ps
CPU time 188.83 seconds
Started Aug 17 05:28:06 PM PDT 24
Finished Aug 17 05:31:15 PM PDT 24
Peak memory 202140 kb
Host smart-e10025e5-f906-4cac-80b2-7761c67e76b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075528040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1075528040
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2126995362
Short name T704
Test name
Test status
Simulation time 636434234685 ps
CPU time 1255.52 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:49:01 PM PDT 24
Peak memory 202004 kb
Host smart-08621d04-ae6e-4b9d-99cf-f435837ae654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126995362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2126995362
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4239910088
Short name T359
Test name
Test status
Simulation time 598687214884 ps
CPU time 596.11 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:38:07 PM PDT 24
Peak memory 202164 kb
Host smart-3c9f5b6f-5c00-4ec2-a025-737818bb1198
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239910088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4239910088
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2253743316
Short name T757
Test name
Test status
Simulation time 110844635664 ps
CPU time 577.5 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:37:46 PM PDT 24
Peak memory 202384 kb
Host smart-d244684f-64c7-4bd8-aff8-a0194d17dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253743316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2253743316
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4169939179
Short name T58
Test name
Test status
Simulation time 29802959120 ps
CPU time 63.26 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:29:12 PM PDT 24
Peak memory 201944 kb
Host smart-2b1ab2cb-036d-41c8-816a-4e76a6d6760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169939179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4169939179
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1034971592
Short name T385
Test name
Test status
Simulation time 2807394603 ps
CPU time 7.35 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:28:15 PM PDT 24
Peak memory 201892 kb
Host smart-d867d8db-48a5-42d0-ba76-4f41c8123337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034971592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1034971592
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3673536800
Short name T630
Test name
Test status
Simulation time 5776251476 ps
CPU time 4.23 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 201848 kb
Host smart-e98d0b63-b25c-47cd-b60d-e4929a42ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673536800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3673536800
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1384681843
Short name T653
Test name
Test status
Simulation time 123829133201 ps
CPU time 650.95 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:39:01 PM PDT 24
Peak memory 210588 kb
Host smart-82a91a56-c1c4-49c6-a1f1-79ee724a81da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384681843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1384681843
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3175978571
Short name T49
Test name
Test status
Simulation time 39124008379 ps
CPU time 10.37 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:28:21 PM PDT 24
Peak memory 210436 kb
Host smart-b5c8c42e-14b8-44b3-a0fd-1c846094e077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175978571 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3175978571
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1711972095
Short name T749
Test name
Test status
Simulation time 397782730 ps
CPU time 1.5 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:28:16 PM PDT 24
Peak memory 201952 kb
Host smart-d8e28ed8-0325-4b7e-a1e6-fc4e146bc1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711972095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1711972095
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1057021302
Short name T197
Test name
Test status
Simulation time 330832760393 ps
CPU time 189.89 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:31:22 PM PDT 24
Peak memory 202200 kb
Host smart-eb3dd551-74b4-4d04-85dc-03a59baa47c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057021302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1057021302
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3094069334
Short name T588
Test name
Test status
Simulation time 157609536597 ps
CPU time 326.94 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 202156 kb
Host smart-7d34a48b-50a5-4abb-b2a7-a4406e73c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094069334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3094069334
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3933476211
Short name T36
Test name
Test status
Simulation time 318475025291 ps
CPU time 67.4 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:29:21 PM PDT 24
Peak memory 202172 kb
Host smart-3358d419-58e7-4584-93c4-3b7a07402dbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933476211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3933476211
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1805903624
Short name T631
Test name
Test status
Simulation time 490052772947 ps
CPU time 279.31 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:32:50 PM PDT 24
Peak memory 202008 kb
Host smart-d916705d-7f3b-4205-9aac-d33550cd0061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805903624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1805903624
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3152344363
Short name T776
Test name
Test status
Simulation time 182302663308 ps
CPU time 109.08 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:29:56 PM PDT 24
Peak memory 202108 kb
Host smart-f4862557-672d-473f-a7c2-59911fca5f38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152344363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3152344363
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.173917614
Short name T518
Test name
Test status
Simulation time 401726855914 ps
CPU time 975.97 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:44:24 PM PDT 24
Peak memory 202132 kb
Host smart-5f57f248-3d08-4f92-bb61-65c6e8afd568
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173917614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.173917614
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3342349521
Short name T635
Test name
Test status
Simulation time 100025713174 ps
CPU time 516.92 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:36:50 PM PDT 24
Peak memory 202380 kb
Host smart-5470b917-7f25-4e4e-822f-f5035b370c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342349521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3342349521
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1882310993
Short name T457
Test name
Test status
Simulation time 23849870422 ps
CPU time 58.01 seconds
Started Aug 17 05:28:07 PM PDT 24
Finished Aug 17 05:29:05 PM PDT 24
Peak memory 201832 kb
Host smart-4694f049-c31e-4a24-b14b-b6a566d88959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882310993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1882310993
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.411908066
Short name T773
Test name
Test status
Simulation time 2988151494 ps
CPU time 1.81 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:28:14 PM PDT 24
Peak memory 201912 kb
Host smart-15dc2b93-87fc-4ad3-9878-6db42199653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411908066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.411908066
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.199991998
Short name T498
Test name
Test status
Simulation time 5768969986 ps
CPU time 7.1 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:28:21 PM PDT 24
Peak memory 201868 kb
Host smart-cbf2b968-ab6f-4967-87e9-accf2246d95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199991998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.199991998
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1946719477
Short name T790
Test name
Test status
Simulation time 13314972036 ps
CPU time 10.63 seconds
Started Aug 17 05:28:18 PM PDT 24
Finished Aug 17 05:28:28 PM PDT 24
Peak memory 210448 kb
Host smart-14e052fd-c77f-4c5e-9a7f-38f2a4e95b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946719477 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1946719477
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4225042184
Short name T458
Test name
Test status
Simulation time 337853797 ps
CPU time 1.35 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:18 PM PDT 24
Peak memory 201944 kb
Host smart-787aaa01-f32c-4f63-9094-5d9c54384bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225042184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4225042184
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.891238647
Short name T195
Test name
Test status
Simulation time 326843674775 ps
CPU time 110.15 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:29:58 PM PDT 24
Peak memory 202112 kb
Host smart-42c9a81a-b524-404f-b012-038dbf39dd4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891238647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.891238647
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.710070948
Short name T447
Test name
Test status
Simulation time 186785585708 ps
CPU time 445.06 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 202080 kb
Host smart-e7cead5e-c007-41f7-a5bf-a58fd8a34541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710070948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.710070948
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2890522984
Short name T642
Test name
Test status
Simulation time 164686129718 ps
CPU time 373.92 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:34:28 PM PDT 24
Peak memory 202160 kb
Host smart-951fe18e-f472-4e2c-8488-7a72806c817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890522984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2890522984
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1247163592
Short name T464
Test name
Test status
Simulation time 497040497618 ps
CPU time 587.93 seconds
Started Aug 17 05:28:17 PM PDT 24
Finished Aug 17 05:38:05 PM PDT 24
Peak memory 202292 kb
Host smart-c1faefb9-83cc-4c2c-9819-db42a05b2d2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247163592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1247163592
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.769053636
Short name T727
Test name
Test status
Simulation time 167595418679 ps
CPU time 77.99 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:29:32 PM PDT 24
Peak memory 202100 kb
Host smart-4d65a5d8-bbf6-40e4-8f49-bd7bf9b41a1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769053636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.769053636
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2155697035
Short name T512
Test name
Test status
Simulation time 200759937570 ps
CPU time 89.4 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:29:44 PM PDT 24
Peak memory 202104 kb
Host smart-7dd8c92f-5dba-4a02-b9a1-ea98c70bc5c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155697035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2155697035
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2044551582
Short name T579
Test name
Test status
Simulation time 122180076465 ps
CPU time 658.84 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:39:09 PM PDT 24
Peak memory 202372 kb
Host smart-3a9661b4-6511-4b04-b813-696d6adc21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044551582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2044551582
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.596998763
Short name T452
Test name
Test status
Simulation time 43505825867 ps
CPU time 6.4 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:28:31 PM PDT 24
Peak memory 201932 kb
Host smart-30bf716c-973f-467a-a7f4-0de03b496cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596998763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.596998763
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2035048183
Short name T37
Test name
Test status
Simulation time 3143061641 ps
CPU time 2.47 seconds
Started Aug 17 05:28:11 PM PDT 24
Finished Aug 17 05:28:13 PM PDT 24
Peak memory 201904 kb
Host smart-364ef0ca-3782-431c-ad44-4149e5e00780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035048183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2035048183
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1005374502
Short name T103
Test name
Test status
Simulation time 5563738039 ps
CPU time 3.81 seconds
Started Aug 17 05:28:25 PM PDT 24
Finished Aug 17 05:28:29 PM PDT 24
Peak memory 201952 kb
Host smart-56db3c50-288c-4f24-b052-ba8be06a686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005374502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1005374502
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2653055346
Short name T178
Test name
Test status
Simulation time 338108287294 ps
CPU time 345.45 seconds
Started Aug 17 05:28:09 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 202136 kb
Host smart-aea9621b-c353-4951-aaa0-b647eadf3c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653055346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2653055346
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.603367525
Short name T394
Test name
Test status
Simulation time 464610313 ps
CPU time 0.97 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:28:26 PM PDT 24
Peak memory 201992 kb
Host smart-4b0c5b80-910b-4a09-9ceb-e238c1feac16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603367525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.603367525
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3633062692
Short name T278
Test name
Test status
Simulation time 360117092368 ps
CPU time 432.67 seconds
Started Aug 17 05:28:24 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 202148 kb
Host smart-86cb75c8-4bc5-4208-9ee5-93cdce76390b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633062692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3633062692
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1545272255
Short name T557
Test name
Test status
Simulation time 191391970160 ps
CPU time 415.13 seconds
Started Aug 17 05:28:19 PM PDT 24
Finished Aug 17 05:35:14 PM PDT 24
Peak memory 202064 kb
Host smart-28d97c57-05dc-4da5-a3eb-a5f6a26c2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545272255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1545272255
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.660389981
Short name T269
Test name
Test status
Simulation time 168580844281 ps
CPU time 385.87 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:34:39 PM PDT 24
Peak memory 202064 kb
Host smart-a7b9a7de-6278-4a4b-8189-50c7c4c9368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660389981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.660389981
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.929347526
Short name T759
Test name
Test status
Simulation time 163591172180 ps
CPU time 79.83 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:29:36 PM PDT 24
Peak memory 202104 kb
Host smart-55be3864-fb43-4ddb-a38a-61718269b6bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=929347526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.929347526
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2718491639
Short name T670
Test name
Test status
Simulation time 489180197734 ps
CPU time 605.85 seconds
Started Aug 17 05:28:08 PM PDT 24
Finished Aug 17 05:38:14 PM PDT 24
Peak memory 202020 kb
Host smart-aac2b1bc-38d2-40d3-9229-4c5b4195de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718491639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2718491639
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2064433044
Short name T578
Test name
Test status
Simulation time 323587477315 ps
CPU time 173.85 seconds
Started Aug 17 05:28:13 PM PDT 24
Finished Aug 17 05:31:07 PM PDT 24
Peak memory 202068 kb
Host smart-cea5d123-85f9-41e3-b680-da921f212aaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064433044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2064433044
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1043985709
Short name T294
Test name
Test status
Simulation time 554006881392 ps
CPU time 133.42 seconds
Started Aug 17 05:28:10 PM PDT 24
Finished Aug 17 05:30:24 PM PDT 24
Peak memory 202144 kb
Host smart-72ae1d10-88ba-4ec4-be28-889941dbf019
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043985709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1043985709
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2475712810
Short name T594
Test name
Test status
Simulation time 399053081399 ps
CPU time 234.02 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:32:16 PM PDT 24
Peak memory 202120 kb
Host smart-9875c018-d2b4-4f0d-97b2-f7823b6e649f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475712810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2475712810
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4163149547
Short name T640
Test name
Test status
Simulation time 67761778610 ps
CPU time 249.9 seconds
Started Aug 17 05:28:22 PM PDT 24
Finished Aug 17 05:32:32 PM PDT 24
Peak memory 202364 kb
Host smart-42977386-293d-40d4-bc84-9053970b60f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163149547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4163149547
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2541768889
Short name T409
Test name
Test status
Simulation time 46412839071 ps
CPU time 29.54 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:28:42 PM PDT 24
Peak memory 201896 kb
Host smart-d6b85367-8ad5-4d4a-b47f-cabca5fd4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541768889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2541768889
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1349802577
Short name T415
Test name
Test status
Simulation time 4068253959 ps
CPU time 2.99 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:28:17 PM PDT 24
Peak memory 201948 kb
Host smart-a42dc8b7-c216-46ee-93fa-06155c110056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349802577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1349802577
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1878477483
Short name T484
Test name
Test status
Simulation time 5754578514 ps
CPU time 15.3 seconds
Started Aug 17 05:28:12 PM PDT 24
Finished Aug 17 05:28:27 PM PDT 24
Peak memory 201976 kb
Host smart-24ea5d7f-c62d-412d-a602-5942be049ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878477483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1878477483
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1267748867
Short name T323
Test name
Test status
Simulation time 261255195263 ps
CPU time 349.88 seconds
Started Aug 17 05:28:14 PM PDT 24
Finished Aug 17 05:34:04 PM PDT 24
Peak memory 202412 kb
Host smart-5a0da185-f508-4bed-a5c4-1752c6838b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267748867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1267748867
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2391358143
Short name T116
Test name
Test status
Simulation time 13434002931 ps
CPU time 18.51 seconds
Started Aug 17 05:28:16 PM PDT 24
Finished Aug 17 05:28:34 PM PDT 24
Peak memory 218160 kb
Host smart-7151ce54-9baf-48b9-bf94-bf79c930f87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391358143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2391358143
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%