Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5617	1			T2	1		T3	25		T7	12
testmodes[AdcCtrlTestmodeNormal]	4802	1			T2	2		T3	12		T7	2
testmodes[AdcCtrlTestmodeLowpower]	4839	1			T1	3		T5	1		T6	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2806	1			T3	17		T7	9		T9	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1536	1			T3	7		T7	2		T13	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1165	1			T7	1		T26	16		T40	41
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1511	1			T2	1		T3	8		T7	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1711	1			T2	1		T3	4		T12	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1226	1			T25	2		T26	24		T40	31
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1182	1			T26	16		T40	40		T39	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1210	1			T13	1		T25	2		T26	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2213	1			T1	2		T6	19		T25	5