Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19962

1

T1

30

T2

3

T3

74

auto[ADC_CTRL_FILTER_COND_OUT]

3128

1

T12

2

T13

3

T14

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16986

1

T2

3

T3

74

T5

10

auto[1]

6104

1

T1

30

T7

3

T8

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	366	1			T26	1		T40	16		T39	25
values[0]	15	1			T25	3		T195	1		T196	11
values[1]	625	1			T7	3		T27	7		T117	18
values[2]	2853	1			T1	30		T8	11		T15	3
values[3]	936	1			T30	1		T122	10		T38	7
values[4]	544	1			T3	39		T14	1		T128	10
values[5]	765	1			T14	1		T15	12		T122	12
values[6]	666	1			T12	2		T117	10		T54	17
values[7]	754	1			T11	7		T13	2		T14	1
values[8]	576	1			T13	1		T15	15		T147	1
values[9]	946	1			T2	2		T5	10		T12	1
minimum	14044	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T7	3		T25	3		T27	7
values[1]	2812	1			T1	30		T8	11		T15	3
values[2]	868	1			T122	10		T38	7		T115	23
values[3]	760	1			T3	39		T14	2		T15	12
values[4]	640	1			T122	12		T34	4		T158	23
values[5]	715	1			T11	7		T12	2		T39	12
values[6]	703	1			T13	3		T14	1		T15	15
values[7]	540	1			T5	10		T12	1		T148	1
values[8]	751	1			T2	2		T38	52		T117	3
values[9]	92	1			T130	10		T139	1		T197	11
minimum	14424	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	2		T55	14		T126	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	3		T27	1		T117	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T1	30		T8	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	1		T30	1		T37	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T122	1		T123	13		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	1		T115	12		T45	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	21		T14	2		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T128	1		T33	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	4		T56	4		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T122	1		T158	12		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	7		T12	1		T39	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T199	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	1		T16	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T14	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	10		T147	1		T56	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	1		T148	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	2		T38	31		T117	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T134	1		T54	3		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T197	9		T20	3		T201	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T130	10		T139	1		T201	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14282	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T55	12		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	6		T123	10		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T8	10		T28	9		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	2		T124	11		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	9		T123	12		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	6		T115	11		T45	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	18		T15	11		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T128	9		T136	12		T182	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T56	3		T121	11		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T122	11		T158	11		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	6		T54	2		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T199	15		T138	1		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	14		T56	4		T150	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T25	1		T115	4		T54	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T56	16		T203	4		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T128	11		T121	4		T132	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	21		T126	1		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	7		T55	1		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T197	2		T20	1		T201	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T201	13		T89	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T25	3		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T26	1		T40	16		T39	25
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T204	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T25	3		T195	1		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	2		T55	14		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T27	1		T117	18		T172	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T1	30		T8	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	1		T37	14		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T122	1		T123	13		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T30	1		T38	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	21		T14	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T128	1		T33	3		T45	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	1		T15	1		T56	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	1		T158	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	1		T117	10		T54	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	1		T199	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	7		T16	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	2		T14	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T147	1		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T134	1		T125	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T2	2		T5	10		T38	31
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T148	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13926	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T197	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T196	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T55	12		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T27	6		T172	7		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T8	10		T28	9		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	2		T115	11		T123	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T122	9		T123	12		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T38	6		T124	11		T182	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	18		T199	6		T205	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	9		T45	11		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	11		T56	3		T150	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	11		T158	11		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	2		T31	8		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T199	15		T202	10		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	6		T56	16		T136	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T25	1		T115	4		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	14		T56	4		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T125	8		T132	3		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T38	21		T126	1		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T128	11		T54	7		T55	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	2		T55	13		T126	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	2		T27	7		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	3		T8	11		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	3		T30	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T122	10		T123	13		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T38	7		T115	12		T45	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	20		T14	2		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T128	10		T33	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	4		T56	4		T121	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T122	12		T158	12		T198	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T12	1		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	1		T199	16		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	15		T16	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	3		T14	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T147	1		T56	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T148	1		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	2		T38	23		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T134	1		T54	8		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T197	3		T20	3		T201	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T130	1		T139	1		T201	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14424	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T55	13		T126	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T25	1		T117	17		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T1	27		T206	12		T207	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	13		T160	2		T208	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T123	12		T32	1		T205	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T115	11		T45	15		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	19		T150	7		T209	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T152	10		T133	12		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T56	3		T177	1		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T158	11		T211	10		T212	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	6		T39	5		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T202	11		T142	14		T213	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	8		T150	5		T203	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	1		T115	5		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T5	9		T56	16		T120	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T138	12		T142	5		T214	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	29		T117	2		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T54	2		T171	10		T120	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T197	8		T20	1		T201	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T130	9		T201	17		T215	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T26	1		T40	16		T39	25
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T204	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T25	2		T195	1		T196	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	2		T55	13		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T27	7		T117	1		T172	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T1	3		T8	11		T28	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	3		T37	1		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T122	10		T123	13		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T30	1		T38	7		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	20		T14	1		T199	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T128	10		T33	3		T45	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	1		T15	12		T56	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	12		T158	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T117	1		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T199	16		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T16	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	2		T14	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	15		T147	1		T56	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T134	1		T125	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	2		T5	1		T38	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	1		T148	1		T128	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14044	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T197	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T25	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	1		T55	13		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T117	17		T172	2		T160	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T1	27		T206	12		T207	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	13		T115	11		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T123	12		T32	1		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T138	14		T208	14		T210	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T3	19		T209	10		T216	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	15		T133	12		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	3		T150	7		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T158	11		T152	10		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T117	9		T54	14		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T202	11		T142	14		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	6		T39	5		T56	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	1		T115	5		T171	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T56	8		T150	5		T203	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	9		T138	12		T214	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	9		T38	29		T117	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	2		T130	9		T171	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19978

1

T1

30

T2

1

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3112

1

T2

2

T3

21

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17330

1

T2

3

T3

53

T5

10

auto[1]

5760

1

T1

30

T3

21

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T219	4		-	-		-	-
values[0]	50	1			T14	1		T219	15		T220	26
values[1]	536	1			T11	7		T14	1		T122	25
values[2]	800	1			T147	1		T135	1		T55	26
values[3]	710	1			T13	1		T15	3		T25	8
values[4]	609	1			T7	3		T15	15		T117	18
values[5]	2895	1			T1	30		T8	11		T12	1
values[6]	736	1			T30	1		T38	37		T117	3
values[7]	809	1			T5	10		T12	2		T13	2
values[8]	733	1			T14	1		T38	15		T115	10
values[9]	810	1			T2	2		T3	39		T15	12
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T11	7		T14	2		T122	25
values[1]	812	1			T123	25		T135	1		T55	26
values[2]	631	1			T13	1		T25	8		T122	10
values[3]	2784	1			T1	30		T7	3		T8	11
values[4]	659	1			T12	1		T30	1		T117	10
values[5]	789	1			T5	10		T13	2		T38	37
values[6]	847	1			T12	2		T27	7		T37	14
values[7]	582	1			T14	1		T38	15		T54	10
values[8]	683	1			T2	2		T3	39		T15	12
values[9]	113	1			T199	7		T221	14		T222	2
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T14	1		T122	2		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	7		T14	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T135	1		T55	14		T45	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T123	13		T158	12		T151	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T25	7		T148	1		T56	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T122	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1555	1			T1	30		T7	2		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T124	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T30	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T117	10		T197	9		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T38	20		T117	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	10		T39	6		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T12	2		T37	14		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	1		T115	6		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	11		T54	3		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	1		T223	4		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	10		T15	1		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	2		T3	11		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T224	14		T225	1		T226	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T199	1		T221	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T122	23		T128	11		T123	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T31	15		T227	3		T172	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	12		T45	11		T56	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T123	12		T158	11		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T25	1		T56	4		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T122	9		T128	9		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T7	1		T8	10		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	14		T124	11		T55	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T136	12		T205	11		T203	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T197	2		T31	8		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T38	17		T138	7		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	6		T115	11		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T38	6		T54	2		T150	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T27	6		T115	4		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	4		T54	7		T125	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T221	7		T228	2		T201	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	8		T15	11		T229	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	10		T54	1		T56	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T224	10		T225	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T199	6		T221	13		T222	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T219	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T220	12		T230	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	1		T219	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T122	2		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	7		T123	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T147	1		T135	1		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T158	12		T140	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T25	7		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T122	1		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T117	18		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	1		T128	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T1	30		T8	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T117	10		T55	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T38	20		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T115	12		T199	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	2		T13	2		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	10		T27	1		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T38	11		T54	18		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	1		T115	6		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	10		T15	1		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	2		T3	11		T16	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T219	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T220	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T219	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T122	23		T128	11		T123	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T123	12		T31	15		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T55	12		T170	11		T56	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T158	11		T132	7		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	2		T25	1		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T122	9		T32	1		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	1		T56	4		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	14		T128	9		T124	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T8	10		T28	9		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	1		T132	7		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	17		T133	10		T208	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T115	11		T199	15		T121	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	6		T126	9		T138	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	6		T39	6		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	4		T54	9		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T115	4		T152	1		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T15	11		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	10		T54	1		T56	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1