Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19969

1

T1

30

T2

1

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3121

1

T2

2

T3

21

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17329

1

T2

3

T3

53

T5

10

auto[1]

5761

1

T1

30

T3

21

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	146	1			T2	2		T15	12		T30	1
values[0]	15	1			T299	5		T176	10		-	-
values[1]	580	1			T11	7		T14	2		T122	25
values[2]	790	1			T147	1		T135	1		T55	26
values[3]	654	1			T13	1		T25	8		T122	10
values[4]	621	1			T7	3		T15	18		T117	18
values[5]	2937	1			T1	30		T8	11		T12	1
values[6]	733	1			T30	1		T38	37		T117	3
values[7]	787	1			T5	10		T12	2		T13	2
values[8]	754	1			T14	1		T115	10		T54	10
values[9]	675	1			T3	39		T16	1		T38	15
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	608	1			T11	7		T14	2		T122	12
values[1]	785	1			T123	25		T135	1		T55	26
values[2]	617	1			T13	1		T25	8		T122	10
values[3]	2814	1			T1	30		T7	3		T8	11
values[4]	673	1			T12	1		T30	1		T117	10
values[5]	720	1			T5	10		T13	2		T38	37
values[6]	884	1			T12	2		T27	7		T37	14
values[7]	603	1			T14	1		T38	15		T54	10
values[8]	705	1			T2	2		T3	39		T15	12
values[9]	75	1			T34	4		T199	7		T221	14
minimum	14606	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	1		T122	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	7		T14	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T135	1		T55	14		T56	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	13		T158	12		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	7		T148	1		T56	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T122	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T1	30		T7	2		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T124	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T30	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T117	10		T197	9		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	2		T38	20		T117	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	10		T39	6		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T12	2		T37	14		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	1		T115	6		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	11		T54	3		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T223	4		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	10		T15	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	2		T3	11		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T34	4		T224	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T199	1		T221	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14346	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T31	8		T258	1		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T122	11		T128	11		T123	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T227	3		T172	11		T219	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T55	12		T56	16		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	12		T158	11		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	1		T56	4		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T122	9		T128	9		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T7	1		T8	10		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	14		T124	11		T55	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T136	12		T205	11		T203	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T197	2		T31	8		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	17		T138	7		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	6		T115	11		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T38	6		T54	2		T150	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	6		T115	4		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	4		T54	7		T125	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T221	7		T228	2		T201	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	8		T15	11		T55	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	10		T54	1		T56	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T225	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T199	6		T221	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T25	3		T122	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T31	15		T289	2		T302	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T15	1		T34	4		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T2	2		T30	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T299	4		T176	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T122	2		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	7		T14	1		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T147	1		T135	1		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	9		T140	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	7		T148	1		T171	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T122	1		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	2		T15	1		T117	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	1		T128	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T1	30		T8	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T117	10		T55	1		T197	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	1		T38	20		T117	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T115	12		T151	9		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	2		T13	2		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	10		T27	1		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T54	3		T125	10		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T115	6		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	10		T38	11		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	11		T16	1		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T15	11		T268	12		T225	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T126	1		T199	6		T219	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T122	23		T128	11		T123	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T123	12		T31	15		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T55	12		T170	11		T56	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T132	7		T172	11		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	1		T171	2		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	9		T32	1		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	1		T15	2		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	14		T128	9		T124	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T8	10		T28	9		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	1		T197	2		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T38	17		T138	1		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T115	11		T199	15		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	6		T54	2		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	6		T39	6		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T54	7		T125	8		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T115	4		T199	2		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	8		T38	4		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	10		T54	1		T56	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	1		T122	12		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	1		T14	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T135	1		T55	13		T56	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T123	13		T158	12		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	6		T148	1		T56	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T122	10		T128	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T1	3		T7	2		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	15		T124	12		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T30	1		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T117	1		T197	3		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	2		T38	18		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T39	7		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	2		T37	1		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	7		T115	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T38	5		T54	8		T125	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T223	1		T221	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	9		T15	12		T55	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	2		T3	11		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T34	4		T224	1		T225	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T199	7		T221	14		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14458	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T31	16		T258	1		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T123	13		T45	15		T150	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	6		T172	11		T255	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T55	13		T56	16		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T123	12		T158	11		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	2		T56	8		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	1		T232	16		T209	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T1	27		T7	1		T117	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T160	12		T211	11		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T205	9		T203	5		T212	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	9		T197	8		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	19		T117	2		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	9		T39	5		T115	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T37	13		T54	14		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T115	5		T231	1		T258	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	10		T54	2		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T223	3		T201	17		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	9		T229	20		T233	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	10		T56	3		T129	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T234	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T235	9		T236	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T220	11		T173	6		T299	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T31	7		T289	2		T302	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T15	12		T34	4		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T2	2		T30	1		T126	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T299	4		T176	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	1		T122	25		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T14	1		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T147	1		T135	1		T55	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	1		T140	1		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	6		T148	1		T171	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T122	10		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	2		T15	3		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	15		T128	10		T124	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T1	3		T8	11		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T117	1		T55	2		T197	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	1		T38	18		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T115	12		T151	1		T199	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	2		T13	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T27	7		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T54	8		T125	9		T158	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T115	5		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	9		T38	5		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	11		T16	1		T54	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T233	8		T256	12		T296	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T215	13		T235	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T299	1		T176	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T123	13		T45	15		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	6		T123	12		T31	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	13		T56	16		T133	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	8		T233	13		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T25	2		T171	4		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	1		T158	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T117	17		T56	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T232	16		T211	11		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T1	27		T206	12		T207	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T117	9		T197	8		T172	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	19		T117	2		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T115	11		T151	8		T119	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	13		T54	14		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	9		T39	5		T217	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T54	2		T125	9		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T115	5		T223	3		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	9		T38	10		T229	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	10		T56	3		T129	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9