Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19779

1

T1

30

T2

1

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T2

2

T3

18

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17283

1

T2

3

T3

74

T6

20

auto[1]

5807

1

T1

30

T5

10

T8

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	29	1			T258	1		T209	11		T302	17
values[0]	50	1			T14	1		T55	2		T289	5
values[1]	498	1			T12	1		T14	1		T15	15
values[2]	616	1			T30	1		T117	3		T115	23
values[3]	655	1			T2	2		T3	18		T15	12
values[4]	648	1			T117	18		T128	12		T55	2
values[5]	662	1			T54	17		T135	1		T150	14
values[6]	736	1			T12	2		T15	3		T38	22
values[7]	624	1			T7	3		T30	1		T115	10
values[8]	2963	1			T1	30		T8	11		T13	3
values[9]	1211	1			T3	21		T5	10		T11	7
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T12	1		T14	2		T15	15
values[1]	588	1			T30	1		T115	23		T125	18
values[2]	676	1			T2	2		T3	18		T15	12
values[3]	690	1			T117	18		T54	17		T158	23
values[4]	569	1			T12	1		T135	1		T121	12
values[5]	780	1			T12	1		T15	3		T38	22
values[6]	2864	1			T1	30		T7	3		T8	11
values[7]	742	1			T148	1		T38	37		T170	12
values[8]	868	1			T3	21		T5	10		T11	7
values[9]	187	1			T122	25		T134	2		T199	3
minimum	14418	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	2		T55	1		T171	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T14	2		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T138	1		T172	1		T208	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T30	1		T115	12		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T55	1		T121	1		T205	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	2		T3	10		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T117	18		T259	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	15		T158	12		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T135	1		T121	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T36	1		T242	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	1		T15	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T38	11		T54	1		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T1	30		T8	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	2		T13	3		T115	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T170	1		T129	1		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T148	1		T38	20		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	11		T14	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	10		T11	7		T150	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T122	2		T134	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T134	1		T237	1		T233	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	1		T55	1		T171	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	14		T27	6		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T138	1		T172	1		T208	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T115	11		T125	8		T55	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T55	1		T121	2		T205	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	8		T15	11		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	15		T221	7		T228	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	2		T158	11		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T121	11		T198	4		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T242	11		T172	7		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	2		T38	6		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T38	4		T54	1		T203	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T8	10		T28	9		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	1		T115	4		T123	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T170	11		T129	12		T205	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	17		T166	1		T218	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	10		T25	1		T122	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	18		T199	6		T182	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T122	23		T199	2		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T211	15		T219	14		T267	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T209	11		T302	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T55	1		T278	11		T303	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T14	1		T289	3		T304	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T32	2		T171	5		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T14	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T246	1		T132	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	1		T117	3		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T152	11		T177	3		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	2		T3	10		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T117	18		T55	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	1		T158	12		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T135	1		T133	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T54	15		T150	6		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T15	1		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T38	11		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T30	1		T124	1		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	2		T115	6		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T1	30		T8	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	3		T148	1		T38	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T3	11		T14	1		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T5	10		T11	7		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T55	1		T278	3		T303	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T289	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T32	1		T171	2		T242	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T15	14		T27	6		T247	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T246	14		T132	7		T138	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T115	11		T55	12		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	10		T241	2		T228	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	8		T15	11		T125	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T55	1		T121	2		T205	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T128	11		T158	11		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T143	10		T214	10		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	2		T150	8		T172	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	2		T38	6		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T38	4		T54	1		T208	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	11		T171	10		T199	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T115	4		T123	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T8	10		T28	9		T145	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	17		T54	7		T126	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	10		T25	1		T122	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T150	18		T199	6		T182	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	2		T55	2		T171	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T14	2		T15	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T138	2		T172	2		T208	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	1		T115	12		T125	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T55	2		T121	3		T205	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	2		T3	9		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T117	1		T259	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T54	3		T158	12		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T135	1		T121	12		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T36	1		T242	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	1		T15	3		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	5		T54	2		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T1	3		T8	11		T28	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	2		T13	3		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T170	12		T129	13		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	1		T38	18		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	11		T14	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T11	1		T150	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T122	25		T134	1		T199	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T134	1		T237	1		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T276	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	1		T171	4		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	1		T37	13		T129	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T208	10		T216	7		T289	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T115	11		T125	9		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T205	9		T152	10		T177	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	9		T117	11		T56	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T117	17		T31	7		T218	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T54	14		T158	11		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T232	16		T214	7		T210	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T242	10		T172	2		T249	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T123	12		T158	14		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	10		T160	2		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T1	27		T206	12		T207	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	1		T115	5		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T120	10		T172	11		T201	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T38	19		T130	9		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	10		T25	1		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	9		T11	6		T150	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T210	9		T306	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T233	8		T211	15		T209	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T209	1		T302	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T55	2		T278	4		T303	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T14	1		T289	3		T304	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T32	2		T171	3		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	1		T14	1		T15	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T246	15		T132	8		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	1		T117	1		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T152	11		T177	2		T241	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	2		T3	9		T15	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T117	1		T55	2		T121	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	12		T158	12		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T135	1		T133	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T54	3		T150	9		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T15	3		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T38	5		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	1		T124	12		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	2		T115	5		T123	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	3		T8	11		T28	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T148	1		T38	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T3	11		T14	1		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T5	1		T11	1		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T209	10		T302	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T278	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T289	2		T304	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T32	1		T171	4		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	1		T37	13		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T208	10		T216	7		T289	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	2		T115	11		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T152	10		T177	1		T296	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	9		T117	9		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	17		T205	9		T31	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T158	11		T133	12		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	10		T214	7		T265	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T54	14		T150	5		T172	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	12		T158	14		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	10		T208	14		T250	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T151	15		T171	10		T255	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	1		T115	5		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	27		T206	12		T207	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	19		T54	2		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	10		T25	1		T39	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	9		T11	6		T150	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9