Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19928

1

T1

30

T2

1

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3162

1

T2

2

T3

39

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17512

1

T2

1

T3

56

T5

10

auto[1]

5578

1

T1

30

T2

2

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T7	3		T139	1		T242	22
values[0]	62	1			T121	12		T143	21		T23	2
values[1]	461	1			T3	21		T147	1		T134	1
values[2]	744	1			T25	5		T30	1		T37	14
values[3]	527	1			T5	10		T13	2		T14	1
values[4]	497	1			T122	13		T54	10		T124	12
values[5]	3038	1			T1	30		T3	18		T8	11
values[6]	878	1			T12	1		T15	15		T27	7
values[7]	579	1			T14	1		T25	3		T122	12
values[8]	599	1			T14	1		T15	12		T117	21
values[9]	1264	1			T2	2		T11	7		T12	1
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T3	21		T147	1		T134	1
values[1]	784	1			T25	5		T30	1		T37	14
values[2]	499	1			T5	10		T13	2		T14	1
values[3]	2786	1			T1	30		T8	11		T28	10
values[4]	813	1			T3	18		T12	1		T27	7
values[5]	841	1			T12	1		T15	15		T122	12
values[6]	495	1			T14	1		T25	3		T38	15
values[7]	749	1			T12	1		T14	1		T15	12
values[8]	928	1			T2	2		T7	3		T11	7
values[9]	175	1			T118	1		T139	2		T243	12
minimum	14402	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T134	1		T56	4		T126	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T147	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T37	14		T38	20		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	4		T30	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	10		T15	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	2		T14	1		T56	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	30		T8	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T122	1		T117	10		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T115	12		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	10		T27	1		T128	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	1		T170	1		T45	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T122	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	1		T115	6		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T25	3		T38	11		T117	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	1		T14	1		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	1		T117	3		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	2		T11	7		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	2		T39	6		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T118	1		T310	1		T173	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T139	2		T243	1		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	2		T153	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T56	3		T126	9		T121	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	10		T199	15		T203	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	17		T123	10		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	1		T122	9		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	2		T38	6		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T56	4		T229	20		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T8	10		T28	9		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T122	12		T124	11		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T115	11		T125	8		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	8		T27	6		T128	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	14		T170	11		T45	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T122	11		T221	7		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T115	4		T241	2		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T38	4		T199	2		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	15		T126	1		T199	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	11		T158	11		T121	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	1		T56	16		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	6		T54	1		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T311	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T243	11		T219	14		T252	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T19	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T7	2		T267	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T139	1		T242	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T121	1		T143	11		T312	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T23	2		T174	1		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T134	1		T56	4		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	11		T147	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T37	14		T38	20		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	4		T30	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	10		T15	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	2		T14	1		T119	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	3		T205	1		T231	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T122	1		T124	1		T56	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T1	30		T8	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	10		T117	10		T128	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	1		T170	1		T45	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T27	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T115	6		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T25	3		T122	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	1		T158	15		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	1		T117	21		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T11	7		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T2	2		T39	6		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T7	1		T267	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T121	11		T143	10		T312	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T295	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	3		T126	9		T121	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	10		T199	15		T203	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	17		T123	10		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	1		T122	9		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	2		T38	6		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T119	2		T197	2		T229	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T54	7		T205	4		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	12		T124	11		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T8	10		T28	9		T115	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	8		T128	20		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	14		T170	11		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T27	6		T38	4		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T115	4		T150	18		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	11		T136	12		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T158	15		T31	8		T241	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T15	11		T54	1		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T56	16		T126	1		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T39	6		T55	1		T136	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T134	1		T56	4		T126	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	11		T147	1		T199	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T37	1		T38	18		T123	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	4		T30	1		T122	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T15	3		T38	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	2		T14	1		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	3		T8	11		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	13		T117	1		T124	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T115	12		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	9		T27	7		T128	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	15		T170	12		T45	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T122	12		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T115	5		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	2		T38	5		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T14	1		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	12		T117	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T7	2		T11	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	2		T39	7		T54	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T118	1		T310	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T139	2		T243	12		T219	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	2		T153	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	3		T126	8		T152	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	10		T255	28		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T37	13		T38	19		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T25	1		T123	12		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	9		T203	5		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T56	8		T229	20		T258	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T1	27		T54	2		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T117	9		T133	12		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T115	11		T125	9		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	9		T54	14		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T45	15		T150	7		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T151	8		T223	3		T212	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T115	5		T242	4		T208	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T25	1		T38	10		T117	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T158	14		T151	8		T255	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T117	2		T158	11		T177	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	1		T11	6		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	5		T120	14		T242	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T173	6		T293	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T252	6		T154	10		T269	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T19	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T7	2		T267	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T139	1		T242	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T121	12		T143	11		T312	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T23	2		T174	1		T295	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T134	1		T56	4		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	11		T147	1		T199	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	1		T38	18		T123	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	4		T30	1		T122	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T15	3		T38	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	2		T14	1		T119	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T54	8		T205	5		T231	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	13		T124	12		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T1	3		T8	11		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	9		T117	1		T128	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	15		T170	12		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	1		T27	7		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	1		T115	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	2		T122	12		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T158	16		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	12		T117	2		T54	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T11	1		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	2		T39	7		T55	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T7	1		T267	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T242	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T143	10		T312	3		T234	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T56	3		T126	8		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T3	10		T19	1		T255	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	13		T38	19		T123	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	1		T123	12		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	9		T32	1		T203	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T119	5		T197	8		T229	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T54	2		T231	1		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	8		T233	12		T258	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	27		T115	11		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	9		T117	9		T54	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	15		T150	5		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	10		T151	8		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T115	5		T150	7		T151	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T25	1		T205	9		T60	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	14		T208	14		T313	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T117	19		T158	11		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T11	6		T56	16		T129	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T39	5		T120	14		T172	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9