Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19830

1

T1

30

T2

1

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3260

1

T2

2

T3

18

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17489

1

T2

3

T3

35

T6

20

auto[1]

5601

1

T1

30

T3

39

T5

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T158	30		T56	7		T151	16
values[0]	29	1			T132	8		T237	1		T212	13
values[1]	789	1			T15	15		T25	5		T128	22
values[2]	2748	1			T1	30		T8	11		T13	1
values[3]	599	1			T14	1		T122	12		T158	23
values[4]	725	1			T5	10		T117	10		T54	17
values[5]	652	1			T3	21		T14	1		T15	12
values[6]	789	1			T3	18		T7	3		T16	1
values[7]	502	1			T14	1		T115	23		T34	4
values[8]	673	1			T2	2		T25	3		T122	10
values[9]	919	1			T11	7		T12	3		T13	2
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	745	1			T13	1		T15	15		T128	22
values[1]	2859	1			T1	30		T8	11		T15	3
values[2]	520	1			T14	1		T158	23		T130	10
values[3]	814	1			T5	10		T15	12		T38	7
values[4]	633	1			T3	21		T7	3		T14	1
values[5]	659	1			T3	18		T16	1		T30	1
values[6]	534	1			T14	1		T38	15		T115	23
values[7]	741	1			T2	2		T25	3		T122	10
values[8]	824	1			T11	7		T12	2		T13	2
values[9]	190	1			T12	1		T170	12		T152	21
minimum	14571	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	1		T15	1		T128	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T134	1		T54	3		T56	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	30		T8	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	1		T27	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	12		T130	10		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	1		T136	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	10		T54	15		T150	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T38	1		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T7	2		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T122	1		T39	6		T117	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	1		T120	15		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	10		T16	1		T37	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T38	11		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	4		T199	1		T205	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	3		T38	20		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	2		T122	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	7		T12	2		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	2		T148	1		T115	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T12	1		T203	6		T211	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T170	1		T152	11		T218	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14321	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T25	4		T233	13		T258	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	14		T128	20		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	7		T56	4		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T8	10		T28	9		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	2		T27	6		T121	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T158	11		T166	16		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T136	12		T31	8		T172	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T54	2		T150	8		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	11		T38	6		T125	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	10		T7	1		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	12		T39	6		T129	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T138	6		T203	2		T160	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	8		T55	1		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	4		T115	11		T55	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T199	15		T205	11		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T38	17		T55	1		T172	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T122	9		T124	11		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T123	10		T158	15		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T115	4		T56	3		T126	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T203	4		T211	15		T314	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T170	11		T152	10		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T25	1		T269	12		T315	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T158	15		T151	16		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T56	4		T121	1		T133	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T132	1		T237	1		T212	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T235	2		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	1		T128	2		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T25	4		T134	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T1	30		T8	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T27	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T122	1		T158	12		T129	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T136	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	10		T54	15		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T117	10		T125	10		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	11		T14	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T122	1		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	2		T30	1		T120	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	10		T16	1		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T115	12		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	4		T199	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	3		T38	31		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	2		T122	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	7		T12	3		T123	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T13	2		T148	1		T115	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T158	15		T211	15		T212	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T56	3		T121	2		T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T132	7		T270	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	14		T128	20		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	1		T54	7		T56	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T8	10		T28	9		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	2		T27	6		T121	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T122	11		T158	11		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T136	12		T31	8		T172	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T54	2		T150	8		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T125	8		T143	10		T216	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	10		T54	1		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	11		T122	12		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	1		T138	6		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	8		T39	6		T55	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T115	11		T247	6		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T199	15		T136	5		T205	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T38	21		T55	13		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T122	9		T124	11		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	10		T241	2		T203	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T115	4		T170	11		T56	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	1		T15	15		T128	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T134	1		T54	8		T56	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T1	3		T8	11		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	3		T27	7		T121	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T158	12		T130	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T136	13		T31	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T54	3		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	12		T38	7		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	11		T7	2		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T122	13		T39	7		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	1		T120	1		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	9		T16	1		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	1		T38	5		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	4		T199	16		T205	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T25	2		T38	18		T55	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	2		T122	10		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T12	2		T123	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	2		T148	1		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T12	1		T203	5		T211	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T170	12		T152	11		T218	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14434	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T25	4		T233	1		T258	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T123	12		T160	2		T214	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T54	2		T56	8		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T1	27		T206	12		T207	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T250	1		T142	5		T273	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T158	11		T130	9		T166	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T214	7		T167	11		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	9		T54	14		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T117	11		T125	9		T255	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	10		T7	1		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	5		T117	17		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	14		T138	12		T203	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	9		T37	13		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	10		T115	11		T55	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T205	9		T242	4		T232	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T25	1		T38	19		T151	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T56	16		T202	11		T255	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	6		T123	13		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T115	5		T56	3		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T203	5		T211	15		T304	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T152	10		T218	11		T222	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T150	7		T212	12		T173	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T25	1		T233	12		T269	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T158	16		T151	1		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T56	4		T121	3		T133	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T132	8		T237	1		T212	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T235	1		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	15		T128	22		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T25	4		T134	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T1	3		T8	11		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	3		T27	7		T121	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	12		T158	12		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	1		T136	13		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T54	3		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T117	1		T125	9		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	11		T14	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	12		T122	13		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	2		T30	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	9		T16	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	1		T115	12		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	4		T199	16		T136	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T25	2		T38	23		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	2		T122	10		T124	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T12	3		T123	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	2		T148	1		T115	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T158	14		T151	15		T142	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T56	3		T133	12		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T212	12		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T123	12		T150	7		T160	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	1		T54	2		T56	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T1	27		T206	12		T207	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T142	5		T273	7		T274	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T158	11		T129	14		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T250	1		T214	7		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	9		T54	14		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T117	9		T125	9		T255	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	10		T32	1		T197	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T117	19		T242	10		T258	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	1		T120	14		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	9		T37	13		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T115	11		T249	9		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T205	9		T242	4		T232	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	1		T38	29		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T202	11		T276	9		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	6		T123	13		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T115	5		T56	16		T152	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9