Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19813

1

T1

30

T2

3

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3277

1

T3

18

T5

10

T11

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17310

1

T2

3

T3

53

T5

10

auto[1]

5780

1

T1

30

T3

21

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	152	1			T231	3		T277	1		T216	15
values[0]	97	1			T15	3		T122	13		T244	1
values[1]	639	1			T12	2		T123	25		T54	12
values[2]	511	1			T3	18		T13	2		T14	1
values[3]	898	1			T5	10		T11	7		T39	12
values[4]	653	1			T13	1		T15	27		T30	1
values[5]	523	1			T14	1		T25	3		T134	1
values[6]	599	1			T3	21		T7	3		T37	14
values[7]	784	1			T30	1		T56	20		T126	18
values[8]	592	1			T25	5		T148	1		T38	7
values[9]	3244	1			T1	30		T2	2		T8	11
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T12	1		T123	25		T54	27
values[1]	619	1			T3	18		T13	2		T14	1
values[2]	866	1			T5	10		T11	7		T15	12
values[3]	615	1			T13	1		T15	15		T25	3
values[4]	539	1			T14	1		T37	14		T134	1
values[5]	604	1			T3	21		T7	3		T122	10
values[6]	3036	1			T1	30		T8	11		T25	5
values[7]	641	1			T14	1		T148	1		T38	7
values[8]	803	1			T16	1		T122	12		T38	15
values[9]	125	1			T2	2		T12	1		T237	1
minimum	14630	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T131	1		T197	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	13		T54	18		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	2		T14	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	10		T151	9		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T117	3		T147	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	10		T11	7		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	1		T25	3		T38	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T171	16		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	1		T233	9		T160	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T37	14		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	11		T7	2		T117	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	1		T33	3		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T1	30		T8	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	4		T30	1		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	1		T32	2		T56	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T148	1		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	1		T122	1		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T38	11		T115	6		T125	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T2	2		T12	1		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T237	1		T198	1		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14343	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T12	1		T122	1		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T197	2		T152	10		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T123	12		T54	9		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T27	6		T150	8		T138	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	8		T132	7		T228	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T45	11		T229	20		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	11		T39	6		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	14		T38	17		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T171	12		T132	3		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T160	21		T20	1		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T199	15		T132	7		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	10		T7	1		T170	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	9		T56	4		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T8	10		T28	9		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T25	1		T56	3		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	6		T32	1		T56	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T123	10		T126	1		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T122	11		T115	11		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	4		T115	4		T125	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T317	9		T318	9		T319	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T198	11		T243	11		T210	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	2		T15	2		T25	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T122	12		T54	1		T121	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T316	1		T213	16		T319	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T231	2		T277	1		T216	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T15	1		T320	1		T321	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T122	1		T244	1		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T131	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T123	13		T54	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	2		T14	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	10		T54	15		T151	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T117	21		T147	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	10		T11	7		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	1		T38	20		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T15	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	3		T134	1		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	1		T199	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	11		T7	2		T117	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	14		T122	1		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T118	1		T136	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	1		T56	13		T126	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	1		T55	14		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	4		T148	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T1	30		T2	2		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	1		T38	11		T115	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T319	7		T322	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T231	1		T216	7		T275	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T15	2		T321	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T122	12		T245	6		T196	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	10		T247	6		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T123	12		T54	8		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T27	6		T197	2		T138	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T3	8		T54	2		T132	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T45	11		T150	8		T229	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	6		T124	11		T158	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	14		T38	17		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	11		T171	12		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	18		T160	21		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T199	15		T241	2		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	10		T7	1		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	9		T132	7		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	5		T246	14		T198	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T56	7		T126	9		T205	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	6		T55	12		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T25	1		T126	1		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T8	10		T28	9		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T38	4		T115	4		T123	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T131	1		T197	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T123	13		T54	11		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	2		T14	1		T27	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	9		T151	1		T132	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T117	1		T147	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	1		T11	1		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	15		T25	2		T38	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T171	14		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T134	1		T233	1		T160	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T37	1		T199	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T7	2		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T122	10		T33	3		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T1	3		T8	11		T28	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T25	4		T30	1		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	7		T32	2		T56	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T148	1		T123	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	1		T122	12		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	5		T115	5		T125	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T2	2		T12	1		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T237	1		T198	12		T243	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14481	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T12	1		T122	13		T54	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T197	8		T152	10		T203	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T123	12		T54	16		T129	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T117	17		T150	5		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	9		T151	8		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T117	2		T45	15		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	9		T11	6		T39	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	1		T38	19		T150	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T171	14		T31	7		T323	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T233	8		T160	17		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	13		T218	3		T214	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	10		T7	1		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T56	8		T232	16		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	27		T206	12		T207	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T25	1		T56	3		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	1		T56	16		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T123	13		T151	8		T223	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T115	11		T217	9		T273	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T38	10		T115	5		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T317	7		T318	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T210	9		T216	7		T324	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T208	13		T252	9		T290	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T304	13		T325	14		T234	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T316	1		T213	1		T319	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T231	2		T277	1		T216	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T15	3		T320	1		T321	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T122	13		T244	1		T245	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T131	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T123	13		T54	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	2		T14	1		T27	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	9		T54	3		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T117	2		T147	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	1		T11	1		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	15		T38	18		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T15	12		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T25	2		T134	1		T150	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	1		T199	16		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T7	2		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	1		T122	10		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T118	1		T136	6		T246	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	1		T56	9		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T38	7		T55	13		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	4		T148	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T1	3		T2	2		T8	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T14	1		T38	5		T115	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T213	15		T322	14		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T231	1		T216	7		T275	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T321	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T245	9		T266	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T152	10		T203	5		T208	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	12		T54	2		T129	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T197	8		T138	12		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	9		T54	14		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T117	19		T45	15		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	9		T11	6		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	19		T242	4		T201	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T171	14		T120	14		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T25	1		T150	7		T160	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T218	3		T284	8		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	10		T7	1		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	13		T232	16		T255	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T233	12		T218	14		T255	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	11		T126	8		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T55	13		T158	11		T172	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T25	1		T151	8		T233	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T1	27		T115	11		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T38	10		T115	5		T123	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9