Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19908

1

T1

30

T2

3

T3

74

auto[ADC_CTRL_FILTER_COND_OUT]

3182

1

T5

10

T12

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17751

1

T2

3

T3

56

T5

10

auto[1]

5339

1

T1

30

T3

18

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T125	18		T119	8		T229	41
values[0]	36	1			T122	13		T270	4		T257	17
values[1]	791	1			T122	12		T147	1		T158	23
values[2]	562	1			T3	21		T7	3		T12	2
values[3]	632	1			T3	18		T13	1		T117	3
values[4]	3020	1			T1	30		T5	10		T8	11
values[5]	579	1			T2	2		T27	7		T38	7
values[6]	635	1			T14	1		T25	8		T16	1
values[7]	613	1			T14	1		T15	15		T30	1
values[8]	713	1			T11	7		T14	1		T15	12
values[9]	913	1			T13	2		T148	1		T39	12
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T12	1		T15	3		T122	12
values[1]	478	1			T3	21		T7	3		T12	1
values[2]	748	1			T3	18		T54	2		T55	2
values[3]	3017	1			T1	30		T5	10		T8	11
values[4]	518	1			T2	2		T27	7		T16	1
values[5]	694	1			T14	2		T15	15		T25	8
values[6]	562	1			T14	1		T30	1		T38	15
values[7]	728	1			T11	7		T15	12		T30	1
values[8]	785	1			T13	2		T148	1		T128	10
values[9]	143	1			T258	40		T141	9		T160	25
minimum	14625	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T12	1		T128	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	1		T122	1		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	11		T7	2		T171	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T13	1		T117	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	10		T126	9		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T54	1		T55	1		T158	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T1	30		T8	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	10		T12	1		T117	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	2		T140	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	1		T16	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	1		T15	1		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T25	4		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	11		T115	12		T54	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T30	1		T115	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	7		T39	6		T117	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	1		T30	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	2		T148	1		T54	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T128	1		T134	1		T56	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T141	1		T244	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T258	22		T160	13		T327	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14347	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T122	1		T147	1		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T128	11		T158	11		T31	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	2		T122	11		T150	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	10		T7	1		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T241	10		T166	16		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T126	9		T199	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T54	1		T55	1		T158	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T8	10		T28	9		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T123	12		T55	13		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T136	12		T198	4		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	6		T38	6		T56	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	14		T122	9		T38	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T25	1		T170	11		T205	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	4		T115	11		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T115	4		T138	16		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	6		T123	10		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	11		T203	2		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T54	7		T124	11		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T128	9		T56	3		T229	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T141	8		T261	11		T262	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T258	18		T160	12		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T122	12		T242	11		T227	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T125	10		T119	6		T141	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T229	21		T160	13		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T270	3		T329	1		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T122	1		T257	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T158	12		T151	9		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	1		T147	1		T150	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	11		T7	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T15	1		T150	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	10		T126	9		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T117	3		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T1	30		T8	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	10		T12	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	2		T135	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	1		T38	1		T117	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T25	3		T122	1		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T15	1		T38	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	1		T115	6		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	7		T117	18		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T15	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	2		T148	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T128	1		T134	1		T56	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T125	8		T119	2		T141	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T229	20		T160	12		T330	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T122	12		T257	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T158	11		T199	2		T31	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T122	11		T150	18		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	10		T7	1		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	2		T150	8		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	8		T126	9		T136	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	1		T158	15		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T8	10		T28	9		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T54	1		T55	13		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	12		T198	4		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	6		T38	6		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T122	9		T56	4		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	1		T170	11		T56	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	14		T38	21		T115	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T115	4		T198	12		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T123	10		T32	1		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	11		T138	16		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T39	6		T54	7		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T128	9		T56	3		T202	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T128	12		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	3		T122	12		T150	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	11		T7	2		T171	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T13	1		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	9		T126	10		T199	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T54	2		T55	2		T158	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	3		T8	11		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T12	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	2		T140	1		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	7		T16	1		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	1		T15	15		T25	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	1		T25	4		T170	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	5		T115	12		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	1		T30	1		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T39	7		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	12		T30	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	2		T148	1		T54	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T128	10		T134	1		T56	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T141	9		T244	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T258	19		T160	13		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14484	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T122	13		T147	1		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T158	11		T151	23		T31	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T150	12		T129	14		T217	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T3	10		T7	1		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T117	2		T166	15		T232	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	9		T126	8		T242	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T158	14		T197	8		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	27		T37	13		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	9		T117	9		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T160	15		T208	14		T265	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T56	16		T133	12		T284	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	1		T38	19		T56	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T25	1		T120	14		T205	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	10		T115	11		T54	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T115	5		T120	10		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	6		T39	5		T117	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T203	9		T211	10		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T54	2		T125	9		T119	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T56	3		T229	20		T233	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T261	7		T262	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T258	21		T160	12		T327	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T203	5		T252	9		T290	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T242	10		T256	12		T255	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T125	9		T119	3		T141	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T229	21		T160	13		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T270	3		T329	1		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T122	13		T257	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T158	12		T151	1		T199	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	12		T147	1		T150	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	11		T7	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T15	3		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	9		T126	10		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T117	1		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	3		T8	11		T28	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T12	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	2		T135	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T27	7		T38	7		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T25	2		T122	10		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	1		T15	15		T38	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T30	1		T115	5		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T117	1		T123	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T15	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	2		T148	1		T39	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T128	10		T134	1		T56	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T125	9		T119	5		T262	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T229	20		T160	12		T330	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T257	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T158	11		T151	8		T31	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	7		T217	9		T242	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	10		T7	1		T151	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T150	5		T129	14		T223	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	9		T126	8		T242	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T117	2		T158	14		T197	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T1	27		T37	13		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	9		T55	13		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T208	14		T265	8		T323	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T117	9		T123	12		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	1		T56	8		T160	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T25	1		T56	16		T205	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	29		T115	11		T54	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T115	5		T120	24		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	6		T117	17		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	14		T203	9		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	5		T54	2		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T56	3		T233	20		T202	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9