Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T14	1		T122	25		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T14	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T135	1		T55	13		T45	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T123	13		T158	12		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T25	6		T148	1		T56	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T122	10		T128	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T1	3		T7	2		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	15		T124	12		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T30	1		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T117	1		T197	3		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	2		T38	18		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T39	7		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	2		T37	1		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	7		T115	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	5		T54	8		T125	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	1		T223	1		T221	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T15	12		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	2		T3	11		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T224	12		T225	14		T226	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T199	7		T221	14		T222	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T123	13		T150	5		T130	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	6		T31	7		T172	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T55	13		T45	15		T56	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	12		T158	11		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T25	2		T56	8		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T32	1		T232	16		T209	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T1	27		T7	1		T117	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T160	12		T211	11		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T205	9		T203	5		T212	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T117	9		T197	8		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	19		T117	2		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	9		T39	5		T115	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	13		T54	14		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T115	5		T202	11		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	10		T54	2		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T223	3		T201	17		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	9		T229	20		T233	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	10		T56	3		T129	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T224	12		T234	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T168	11		T235	9		T236	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T219	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T220	15		T230	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T14	1		T219	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T122	25		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	1		T123	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T147	1		T135	1		T55	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T158	12		T140	1		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	3		T25	6		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T122	10		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T117	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	15		T128	10		T124	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	3		T8	11		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T117	1		T55	2		T132	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	1		T38	18		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T115	12		T199	16		T121	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	2		T13	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T27	7		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T38	5		T54	11		T125	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T115	5		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	9		T15	12		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	2		T3	11		T16	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T220	11		T230	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T123	13		T45	15		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	6		T123	12		T31	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	13		T56	16		T133	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T158	11		T233	13		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T25	2		T171	4		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T32	1		T151	8		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T117	17		T56	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T160	12		T232	16		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T1	27		T206	12		T207	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T117	9		T172	2		T211	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	19		T117	2		T133	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T115	11		T197	8		T202	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	13		T126	8		T138	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	9		T39	5		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T38	10		T54	16		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T115	5		T223	3		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	9		T229	20		T233	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T56	3		T129	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9