Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19761

1

T1

30

T2

3

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3329

1

T3

18

T5

10

T11

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17545

1

T2

3

T3

53

T5

10

auto[1]

5545

1

T1

30

T3

21

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	58	1			T15	3		T122	13		T139	1
values[1]	671	1			T12	1		T123	25		T54	12
values[2]	515	1			T3	18		T12	1		T13	2
values[3]	831	1			T5	10		T11	7		T15	12
values[4]	704	1			T13	1		T15	15		T25	3
values[5]	533	1			T14	1		T134	1		T150	26
values[6]	618	1			T3	21		T7	3		T37	14
values[7]	779	1			T30	1		T56	20		T126	18
values[8]	558	1			T25	5		T148	1		T38	7
values[9]	3425	1			T1	30		T2	2		T8	11
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	784	1			T12	2		T15	3		T122	13
values[1]	617	1			T3	18		T13	2		T14	1
values[2]	856	1			T5	10		T11	7		T15	12
values[3]	628	1			T13	1		T15	15		T25	3
values[4]	541	1			T14	1		T37	14		T134	1
values[5]	650	1			T3	21		T7	3		T117	10
values[6]	3019	1			T1	30		T8	11		T25	5
values[7]	623	1			T14	1		T148	1		T38	7
values[8]	713	1			T16	1		T122	12		T115	33
values[9]	213	1			T2	2		T12	1		T38	15
minimum	14446	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T15	1		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	1		T122	1		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	2		T14	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	10		T150	6		T151	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T117	3		T147	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	10		T11	7		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T25	3		T38	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T128	1		T171	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	14		T134	1		T233	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	1		T199	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	11		T7	2		T117	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T56	13		T160	13		T232	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T1	30		T8	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T25	4		T30	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	1		T32	2		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T148	1		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T122	1		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T115	6		T125	10		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T2	2		T12	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T38	11		T237	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14301	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T179	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	2		T197	2		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T122	12		T123	12		T54	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	6		T138	6		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	8		T150	8		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T45	11		T129	12		T239	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	11		T39	6		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	14		T38	17		T150	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T128	9		T171	12		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T160	21		T20	1		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T199	15		T132	7		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	10		T7	1		T170	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T56	7		T160	12		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T8	10		T28	9		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	1		T122	9		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	6		T32	1		T55	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T123	10		T126	1		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T122	11		T115	11		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T115	4		T125	8		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T217	11		T31	8		T219	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T38	4		T198	11		T243	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T179	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T15	1		T139	1		T203	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T122	1		T244	1		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	1		T152	11		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T123	13		T54	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T13	2		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T54	15		T151	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T117	21		T147	1		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	10		T11	7		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T25	3		T38	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T30	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T134	1		T150	8		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	1		T199	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	11		T7	2		T37	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T122	1		T132	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T118	1		T136	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	1		T56	13		T126	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	1		T55	14		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T25	4		T148	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1736	1			T1	30		T2	2		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T14	1		T38	11		T115	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T15	2		T203	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T122	12		T245	6		T196	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	10		T247	6		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T123	12		T54	8		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T27	6		T197	2		T138	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	8		T54	2		T205	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T239	6		T211	11		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	11		T39	6		T124	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	14		T38	17		T45	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T128	9		T158	15		T171	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T150	18		T160	21		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T199	15		T241	2		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	10		T7	1		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T122	9		T132	7		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	5		T246	14		T205	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T56	7		T126	9		T172	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T38	6		T55	12		T249	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T25	1		T158	11		T126	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T8	10		T28	9		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T38	4		T115	4		T123	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T15	3		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T122	13		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T14	1		T27	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	9		T150	9		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T117	1		T147	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	1		T11	1		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	15		T25	2		T38	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T128	10		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	1		T134	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	1		T199	16		T132	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	11		T7	2		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T56	9		T160	13		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T1	3		T8	11		T28	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	4		T30	1		T122	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	7		T32	2		T55	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T148	1		T123	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	1		T122	12		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T115	5		T125	9		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T2	2		T12	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T38	5		T237	1		T198	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14422	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T179	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T197	8		T203	5		T208	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	12		T54	16		T129	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T117	17		T138	12		T19	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	9		T150	5		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T117	2		T45	15		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	9		T11	6		T39	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	1		T38	19		T150	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T171	14		T31	7		T201	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T37	13		T233	8		T160	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T218	3		T214	15		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	10		T7	1		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	11		T160	12		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T1	27		T206	12		T207	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	1		T158	11		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	1		T56	16		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T123	13		T151	8		T223	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T115	11		T133	12		T250	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T115	5		T125	9		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T217	9		T251	11		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T38	10		T210	9		T216	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T152	10		T252	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T15	3		T139	1		T203	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T122	13		T244	1		T245	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T131	1		T152	11		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T123	13		T54	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T13	2		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	9		T54	3		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T117	2		T147	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T5	1		T11	1		T15	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	15		T25	2		T38	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T30	1		T128	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	1		T150	19		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	1		T199	16		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	11		T7	2		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T122	10		T132	8		T203	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T118	1		T136	6		T246	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	1		T56	9		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	7		T55	13		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	4		T148	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T1	3		T2	2		T8	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T14	1		T38	5		T115	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T203	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T245	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T152	10		T208	13		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	12		T54	2		T129	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T197	8		T138	12		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	9		T54	14		T151	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T117	19		T120	10		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	9		T11	6		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T25	1		T38	19		T45	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T158	14		T171	14		T120	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T150	7		T160	17		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T218	3		T230	10		T254	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	10		T7	1		T37	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	12		T232	16		T255	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T233	12		T218	14		T255	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T56	11		T126	8		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T55	13		T249	9		T60	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	1		T158	11		T151	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T1	27		T115	11		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T38	10		T115	5		T123	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9