Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19894

1

T1

30

T2

3

T3

74

auto[ADC_CTRL_FILTER_COND_OUT]

3196

1

T5

10

T12

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17724

1

T2

3

T3

56

T5

10

auto[1]

5366

1

T1

30

T3

18

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T92	1		-	-		-	-
values[0]	44	1			T122	13		T256	13		T257	17
values[1]	735	1			T7	3		T122	12		T147	1
values[2]	616	1			T3	21		T12	2		T15	3
values[3]	638	1			T3	18		T13	1		T117	3
values[4]	2964	1			T1	30		T5	10		T8	11
values[5]	643	1			T2	2		T27	7		T37	14
values[6]	584	1			T14	1		T25	8		T16	1
values[7]	609	1			T14	1		T15	15		T38	52
values[8]	797	1			T11	7		T14	1		T15	12
values[9]	1061	1			T13	2		T148	1		T128	10
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T12	1		T122	25		T147	1
values[1]	510	1			T3	21		T7	3		T12	1
values[2]	801	1			T3	18		T54	2		T158	30
values[3]	2960	1			T1	30		T2	2		T5	10
values[4]	516	1			T27	7		T16	1		T38	7
values[5]	666	1			T14	2		T15	15		T25	8
values[6]	650	1			T14	1		T30	2		T38	52
values[7]	643	1			T11	7		T15	12		T39	12
values[8]	812	1			T13	2		T148	1		T128	10
values[9]	162	1			T33	3		T258	40		T141	9
minimum	14437	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T12	1		T128	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T122	2		T147	1		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	11		T7	2		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T13	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	10		T126	9		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T54	1		T158	15		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	30		T2	2		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	10		T12	1		T117	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T140	1		T136	1		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	1		T16	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T15	1		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	1		T25	4		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T38	31		T115	12		T54	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T30	2		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	7		T39	6		T117	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T115	6		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	2		T148	1		T54	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T128	1		T134	1		T56	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T33	3		T141	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T258	22		T160	13		T260	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14297	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T151	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	11		T158	11		T199	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T122	23		T150	26		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	10		T7	1		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	2		T55	1		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	8		T126	9		T199	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T54	1		T158	15		T126	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T8	10		T28	9		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	13		T171	10		T203	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T136	12		T198	4		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	6		T38	6		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	14		T122	9		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T25	1		T170	11		T198	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	21		T115	11		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T138	16		T20	1		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	6		T123	10		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	11		T115	4		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T54	7		T124	11		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T128	9		T56	3		T229	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T141	8		T261	11		T262	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T258	18		T160	12		T263	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	2		T25	3		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T92	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T122	1		T256	13		T257	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	2		T158	12		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	1		T147	1		T150	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	11		T12	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T15	1		T150	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	10		T126	9		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	1		T117	3		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T1	30		T8	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	10		T12	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	2		T37	14		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	1		T117	10		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T25	3		T122	1		T56	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	1		T15	1		T38	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T115	6		T118	1		T120	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	7		T39	6		T117	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T15	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	2		T148	1		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T128	1		T134	1		T56	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T122	12		T257	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T158	11		T199	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T122	11		T150	18		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	10		T128	11		T171	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	2		T150	8		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	8		T126	9		T136	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	1		T158	15		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T8	10		T28	9		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	1		T55	1		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	12		T198	4		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	6		T123	12		T55	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	9		T56	4		T246	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T25	1		T38	6		T170	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	14		T38	21		T115	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T115	4		T198	12		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	6		T123	10		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	11		T138	16		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T54	7		T124	11		T125	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T128	9		T56	3		T229	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	1		T128	12		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T122	25		T147	1		T150	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T7	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T13	1		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	9		T126	10		T199	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T54	2		T158	16		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T1	3		T2	2		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T12	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T140	1		T136	13		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	7		T16	1		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	1		T15	15		T25	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T25	4		T170	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T38	23		T115	12		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	1		T30	2		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T39	7		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	12		T115	5		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	2		T148	1		T54	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T128	10		T134	1		T56	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T33	3		T141	9		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T258	19		T160	13		T260	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14413	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T151	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T158	11		T31	7		T203	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	12		T217	9		T223	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	10		T7	1		T151	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T117	2		T129	14		T166	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	9		T126	8		T242	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T158	14		T197	8		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	27		T37	13		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	9		T117	9		T55	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T160	15		T208	14		T265	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T123	12		T56	16		T205	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	1		T56	8		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	1		T120	24		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	29		T115	11		T54	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T138	14		T20	1		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	6		T39	5		T117	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T115	5		T211	10		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T54	2		T125	9		T119	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T56	3		T229	20		T233	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T261	7		T262	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T258	21		T160	12		T263	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T266	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T151	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T92	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T122	13		T256	1		T257	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	2		T158	12		T199	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	12		T147	1		T150	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	11		T12	1		T128	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T15	3		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T126	10		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	1		T117	1		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T1	3		T8	11		T28	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T12	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T37	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T27	7		T117	1		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T25	2		T122	10		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	1		T15	15		T38	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T115	5		T118	1		T120	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	1		T39	7		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	1		T15	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T13	2		T148	1		T54	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T128	10		T134	1		T56	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T256	12		T257	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	1		T158	11		T31	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T150	7		T151	8		T242	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	10		T151	15		T171	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	5		T129	14		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	9		T126	8		T242	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T117	2		T158	14		T197	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T1	27		T206	12		T207	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	9		T233	13		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	13		T208	14		T265	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	9		T123	12		T55	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	1		T56	8		T160	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T25	1		T56	16		T205	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	29		T115	11		T54	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T115	5		T120	24		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	6		T39	5		T117	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T138	14		T203	9		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T54	2		T125	9		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T56	3		T229	20		T233	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9