Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19778

1

T1

30

T2

1

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3312

1

T2

2

T3

18

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17470

1

T2

3

T3

35

T6

20

auto[1]

5620

1

T1

30

T3

39

T5

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	88	1			T222	17		T267	17		T257	17
values[0]	52	1			T132	8		T212	13		T268	13
values[1]	784	1			T15	15		T25	5		T128	22
values[2]	2743	1			T1	30		T8	11		T13	1
values[3]	596	1			T14	1		T122	12		T129	25
values[4]	682	1			T5	10		T117	10		T54	17
values[5]	691	1			T3	21		T14	1		T15	12
values[6]	762	1			T7	3		T16	1		T30	1
values[7]	541	1			T2	2		T3	18		T14	1
values[8]	640	1			T25	3		T122	10		T38	52
values[9]	1113	1			T11	7		T12	3		T13	2
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	899	1			T13	1		T15	15		T25	5
values[1]	2864	1			T1	30		T8	11		T15	3
values[2]	541	1			T14	1		T158	23		T130	10
values[3]	855	1			T5	10		T15	12		T38	7
values[4]	566	1			T3	21		T7	3		T14	1
values[5]	661	1			T3	18		T30	1		T147	1
values[6]	516	1			T14	1		T16	1		T38	15
values[7]	706	1			T2	2		T12	2		T25	3
values[8]	752	1			T11	7		T13	2		T148	1
values[9]	307	1			T12	1		T170	12		T152	21
minimum	14423	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T15	1		T128	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T25	4		T134	1		T54	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T1	30		T8	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	1		T27	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T158	12		T130	10		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	1		T136	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	10		T38	1		T54	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	1		T117	13		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	11		T7	2		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	14		T122	1		T39	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T120	15		T138	13		T203	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	10		T30	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T38	11		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T16	1		T34	4		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	2		T25	3		T38	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	2		T122	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	7		T123	14		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	2		T148	1		T115	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T203	6		T211	16		T269	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	1		T170	1		T152	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14297	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	14		T128	20		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	1		T54	7		T56	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T8	10		T28	9		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	2		T27	6		T121	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T158	11		T166	16		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T136	12		T31	8		T172	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	6		T54	2		T150	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	11		T125	8		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	10		T7	1		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T122	12		T39	6		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T138	6		T203	2		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	8		T55	1		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	4		T115	11		T55	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T199	15		T205	15		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	17		T55	12		T172	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T122	9		T124	11		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T123	10		T158	15		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T115	4		T56	3		T126	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T203	4		T211	15		T269	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T170	11		T152	10		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	2		T25	3		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T222	8		T267	14		T257	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T132	1		T212	13		T270	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T268	1		T162	11		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	1		T128	2		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T25	4		T134	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T1	30		T8	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T27	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T122	1		T129	15		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	1		T136	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	10		T54	15		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T117	10		T125	10		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	11		T14	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T122	1		T117	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	2		T120	15		T138	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T16	1		T30	1		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T115	12		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	2		T3	10		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	3		T38	31		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T122	1		T124	1		T34	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T11	7		T12	2		T123	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	1		T13	2		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T222	9		T267	3		T257	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T132	7		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T268	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	14		T128	20		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	1		T54	7		T56	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T8	10		T28	9		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	2		T27	6		T121	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T122	11		T129	10		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T136	12		T31	8		T166	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	2		T158	11		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T125	8		T265	8		T272	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	10		T38	6		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	11		T122	12		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	1		T138	6		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	6		T55	1		T205	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T115	11		T199	2		T247	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	8		T199	15		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	21		T55	13		T198	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	9		T124	11		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T123	10		T158	15		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T115	4		T170	11		T56	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	1		T15	15		T128	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T25	4		T134	1		T54	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	3		T8	11		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	3		T27	7		T121	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T158	12		T130	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T136	13		T31	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T38	7		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T15	12		T117	2		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	11		T7	2		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	1		T122	13		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T120	1		T138	7		T203	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	9		T30	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T38	5		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T34	4		T199	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	2		T25	2		T38	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	2		T122	10		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T123	11		T158	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T148	1		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T203	5		T211	16		T269	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	1		T170	12		T152	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14410	1			T2	1		T3	35		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T123	12		T150	7		T160	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T25	1		T54	2		T56	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T1	27		T206	12		T207	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T250	1		T273	7		T274	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T158	11		T130	9		T166	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T214	7		T167	11		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	9		T54	14		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T117	11		T125	9		T258	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	10		T7	1		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	13		T39	5		T117	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T120	14		T138	12		T203	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	9		T120	10		T229	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T38	10		T115	11		T249	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T205	9		T232	16		T267	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	1		T38	19		T55	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T56	16		T202	11		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	6		T123	13		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T115	5		T56	3		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T203	5		T211	15		T269	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T152	10		T223	3		T218	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T212	12		T270	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T222	10		T267	4		T257	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T132	8		T212	1		T270	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T268	13		T162	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	15		T128	22		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	4		T134	1		T54	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	3		T8	11		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	3		T27	7		T121	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T122	12		T129	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	1		T136	13		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	1		T54	3		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T117	1		T125	9		T259	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	11		T14	1		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	12		T122	13		T117	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	2		T120	1		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T16	1		T30	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T115	12		T199	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	2		T3	9		T199	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T25	2		T38	23		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T122	10		T124	12		T34	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T11	1		T12	2		T123	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	1		T13	2		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T222	7		T267	13		T257	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T212	12		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T162	10		T235	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T123	12		T150	7		T31	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T25	1		T54	2		T56	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T1	27		T206	12		T207	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T142	5		T274	1		T275	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	14		T130	9		T172	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T250	1		T214	7		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	9		T54	14		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T117	9		T125	9		T255	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	10		T32	1		T197	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T117	19		T258	21		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T120	14		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	13		T39	5		T229	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T115	11		T249	9		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	9		T120	10		T205	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	1		T38	29		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T202	11		T276	9		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	6		T123	13		T158	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T115	5		T56	19		T152	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9