Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19913

1

T1

30

T2

3

T3

56

auto[ADC_CTRL_FILTER_COND_OUT]

3177

1

T3

18

T11

7

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17061

1

T2

3

T3

56

T5

10

auto[1]

6029

1

T1

30

T3

18

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	568	1			T2	2		T26	1		T40	16
values[0]	11	1			T196	11		-	-		-	-
values[1]	617	1			T7	3		T25	3		T27	7
values[2]	2847	1			T1	30		T8	11		T15	3
values[3]	898	1			T30	1		T122	10		T38	7
values[4]	618	1			T3	21		T14	1		T128	10
values[5]	773	1			T3	18		T14	1		T15	12
values[6]	656	1			T12	2		T117	10		T54	17
values[7]	698	1			T11	7		T13	2		T14	1
values[8]	627	1			T5	10		T13	1		T15	15
values[9]	733	1			T12	1		T148	1		T38	37
minimum	14044	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	586	1			T7	3		T25	3		T123	24
values[1]	2843	1			T1	30		T8	11		T15	3
values[2]	866	1			T30	1		T38	7		T115	23
values[3]	693	1			T3	39		T14	2		T15	12
values[4]	731	1			T122	12		T54	17		T34	4
values[5]	697	1			T11	7		T12	2		T39	12
values[6]	685	1			T13	3		T14	1		T15	15
values[7]	542	1			T5	10		T12	1		T148	1
values[8]	745	1			T2	2		T38	37		T117	3
values[9]	96	1			T38	15		T54	10		T130	10
minimum	14606	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	2		T25	3		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T123	14		T55	14		T158	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T1	30		T8	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	14		T134	1		T151	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T32	2		T205	11		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	1		T38	1		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	11		T14	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	10		T14	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T34	4		T56	4		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T122	1		T54	15		T158	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T39	6		T117	10		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	7		T12	2		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T14	1		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	2		T115	6		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	10		T12	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T148	1		T134	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	2		T38	20		T117	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T128	1		T126	1		T171	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T38	11		T197	9		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T54	3		T130	10		T201	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14328	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T27	1		T117	18		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T166	17		T252	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T123	10		T55	12		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T8	10		T15	2		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T132	7		T160	9		T253	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T32	1		T205	15		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T38	6		T115	11		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	10		T15	11		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	8		T128	9		T121	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	3		T150	18		T121	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T122	11		T54	2		T158	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	6		T54	1		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T199	15		T138	1		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	14		T25	1		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T115	4		T56	4		T198	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T56	16		T121	4		T203	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	3		T138	6		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	17		T55	1		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T128	11		T126	1		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T38	4		T197	2		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T54	7		T201	13		T21	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T27	6		T222	9		T286	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T2	2		T26	1		T40	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T54	3		T199	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T196	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T25	3		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T27	1		T117	18		T55	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T1	30		T8	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	14		T123	14		T158	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T122	1		T32	2		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T38	1		T115	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	11		T170	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	1		T128	1		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	1		T15	1		T56	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	10		T122	1		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T117	10		T34	4		T151	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	2		T54	15		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	7		T13	2		T115	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	10		T13	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T134	1		T56	9		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T38	20		T117	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T148	1		T128	1		T126	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13926	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T38	4		T129	10		T197	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T54	7		T199	2		T222	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T196	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	1		T126	9		T166	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T27	6		T55	12		T31	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T8	10		T15	2		T28	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T123	10		T158	15		T132	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	9		T32	1		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	6		T115	11		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	10		T170	11		T199	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T128	9		T45	11		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	11		T56	3		T150	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	8		T122	11		T158	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T136	5		T229	20		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	2		T199	15		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	1		T39	6		T54	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T115	4		T138	1		T172	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	14		T125	8		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	4		T132	3		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T38	17		T55	1		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T128	11		T126	1		T171	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T25	2		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T123	11		T55	13		T158	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T1	3		T8	11		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	1		T134	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	2		T205	17		T152	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	1		T38	7		T115	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	11		T14	1		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	9		T14	1		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T34	4		T56	4		T150	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T122	12		T54	3		T158	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	7		T117	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T12	2		T199	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	1		T14	1		T15	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	2		T115	5		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T12	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T148	1		T134	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T38	18		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T128	12		T126	2		T171	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T38	5		T197	3		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T54	8		T130	1		T201	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14459	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T27	7		T117	1		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	1		T25	1		T166	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T123	13		T55	13		T158	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T1	27		T206	12		T207	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	13		T151	8		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T32	1		T205	9		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	11		T123	12		T45	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	10		T209	10		T274	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	9		T152	10		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	3		T150	7		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	14		T158	11		T212	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	5		T117	9		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	6		T202	11		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T25	1		T125	9		T150	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T115	5		T56	8		T203	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	9		T56	16		T120	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T138	12		T233	12		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	19		T117	2		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T171	10		T120	14		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T38	10		T197	8		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T54	2		T130	9		T201	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T126	8		T287	2		T288	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T117	17		T142	13		T222	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T2	2		T26	1		T40	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T54	8		T199	3		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T196	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	2		T25	2		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	7		T117	1		T55	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	3		T8	11		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	1		T123	11		T158	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T122	10		T32	2		T124	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T30	1		T38	7		T115	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	11		T170	12		T199	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T128	10		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	1		T15	12		T56	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	9		T122	12		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T117	1		T34	4		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	2		T54	3		T199	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	1		T25	4		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T13	2		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T13	1		T15	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	1		T56	5		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T38	18		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T148	1		T128	12		T126	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14044	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T38	10		T129	14		T197	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T54	2		T201	17		T215	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T25	1		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T117	17		T55	13		T31	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T1	27		T206	12		T207	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	13		T123	13		T158	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T32	1		T205	9		T242	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T115	11		T123	12		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	10		T217	9		T255	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	15		T133	12		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	3		T150	7		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	9		T158	11		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T117	9		T151	15		T229	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T54	14		T202	11		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	1		T39	5		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	6		T115	5		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	9		T125	9		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T56	8		T138	12		T203	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	19		T117	2		T119	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T130	9		T171	10		T120	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9