Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17484

1

T2

3

T3

56

T5

10

auto[ADC_CTRL_FILTER_COND_OUT]

5606

1

T1

30

T3

18

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17185

1

T2

1

T3

56

T6

20

auto[1]

5905

1

T1

30

T2

2

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	177	1			T122	10		T38	7		T115	10
values[0]	3	1			T283	3		-	-		-	-
values[1]	646	1			T13	2		T14	1		T25	5
values[2]	683	1			T12	1		T25	3		T147	1
values[3]	508	1			T11	7		T14	1		T32	3
values[4]	721	1			T3	21		T16	1		T30	1
values[5]	700	1			T117	3		T128	12		T125	18
values[6]	684	1			T3	18		T13	1		T30	1
values[7]	541	1			T15	3		T27	7		T38	15
values[8]	590	1			T7	3		T39	12		T158	30
values[9]	3439	1			T1	30		T2	2		T5	10
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	657	1			T25	5		T54	17		T150	14
values[1]	2937	1			T1	30		T8	11		T11	7
values[2]	450	1			T14	1		T30	1		T32	3
values[3]	749	1			T3	21		T16	1		T115	23
values[4]	662	1			T30	1		T37	14		T148	1
values[5]	668	1			T3	18		T13	1		T15	3
values[6]	589	1			T27	7		T117	10		T123	25
values[7]	725	1			T5	10		T7	3		T15	12
values[8]	965	1			T12	2		T14	1		T15	15
values[9]	120	1			T2	2		T134	1		T54	10
minimum	14568	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T25	4		T233	13		T172	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T54	15		T150	6		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	3		T147	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1584	1			T1	30		T8	1		T11	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	1		T32	2		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T34	4		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	11		T16	1		T125	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T115	12		T134	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T37	14		T148	1		T117	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	1		T38	20		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	11		T117	18		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	10		T13	1		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T27	1		T129	15		T151	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T117	10		T123	13		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	10		T15	1		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	2		T39	6		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	1		T15	1		T115	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T14	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T2	2		T134	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T54	3		T238	1		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14311	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T14	1		T219	1		T289	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T25	1		T172	7		T249	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T54	2		T150	8		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T128	9		T123	10		T45	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	988	1			T8	10		T28	9		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T32	1		T199	15		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T199	2		T121	2		T231	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	10		T125	8		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T115	11		T265	8		T220	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	4		T136	5		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T38	17		T128	11		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	4		T182	11		T229	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	8		T15	2		T122	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T27	6		T129	10		T199	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T123	12		T56	3		T126	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	11		T55	1		T158	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T39	6		T55	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	14		T115	4		T55	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T122	9		T38	6		T132	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T278	12		T280	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T54	7		T238	11		T243	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T219	3		T289	14		T89	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T115	6		T134	1		T121	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T122	1		T38	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T283	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T25	4		T233	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T54	15		T150	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	3		T147	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T54	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	1		T32	2		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	7		T130	10		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	11		T16	1		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	1		T115	12		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T117	3		T125	10		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T128	1		T151	16		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	14		T148	1		T117	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	10		T13	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T27	1		T38	11		T129	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	1		T117	10		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T158	15		T151	9		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	2		T39	6		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T2	2		T5	10		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1725	1			T1	30		T8	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T115	4		T121	11		T19	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T122	9		T38	6		T247	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T25	1		T249	10		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T54	2		T150	8		T126	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T128	9		T123	10		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T54	1		T150	18		T258	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T32	1		T136	12		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T171	10		T199	2		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	10		T158	11		T199	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	11		T172	1		T265	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T125	8		T170	11		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T128	11		T217	11		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T182	11		T229	20		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	8		T122	23		T38	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T27	6		T38	4		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	2		T123	12		T56	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T158	15		T199	6		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	1		T39	6		T198	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T15	25		T55	13		T56	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1130	1			T8	10		T28	9		T145	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T25	4		T233	1		T172	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	3		T150	9		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	2		T147	1		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1331	1			T1	3		T8	11		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	1		T32	2		T199	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T30	1		T34	4		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	11		T16	1		T125	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T115	12		T134	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T37	1		T148	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	1		T38	18		T128	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	5		T117	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	9		T13	1		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T27	7		T129	11		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T117	1		T123	13		T56	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T15	12		T55	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	2		T39	7		T55	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T12	1		T15	15		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	1		T14	1		T122	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T2	2		T134	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T54	8		T238	12		T243	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14440	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T14	1		T219	4		T289	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	1		T233	12		T172	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T54	14		T150	5		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	1		T123	13		T45	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1241	1			T1	27		T11	6		T206	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T32	1		T138	14		T202	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T130	9		T231	1		T203	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	10		T125	9		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T115	11		T151	15		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	13		T117	2		T56	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	19		T217	9		T233	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	10		T117	17		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	9		T154	11		T290	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T129	14		T151	8		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	9		T123	12		T56	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	9		T158	14		T242	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T39	5		T171	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T115	5		T55	13		T56	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T160	15		T212	13		T285	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T167	11		T230	7		T278	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T54	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T287	2		T291	13		T234	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T289	16		T89	12		T179	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T115	5		T134	1		T121	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T122	10		T38	7		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T283	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T25	4		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T54	3		T150	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T25	2		T147	1		T128	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T54	2		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	1		T32	2		T136	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T130	1		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	11		T16	1		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	1		T115	12		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T117	1		T125	9		T170	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T128	12		T151	1		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	1		T148	1		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	9		T13	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T27	7		T38	5		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	3		T117	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T158	16		T151	1		T199	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	2		T39	7		T198	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T2	2		T5	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1499	1			T1	3		T8	11		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T115	5		T19	1		T224	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T25	1		T233	12		T142	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T54	14		T150	5		T126	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	1		T123	13		T45	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	7		T258	21		T208	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T32	1		T172	11		T256	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	6		T130	9		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	10		T158	11		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T115	11		T142	14		T265	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T117	2		T125	9		T56	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T151	15		T217	9		T233	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	13		T117	17		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	9		T38	19		T255	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T38	10		T129	14		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	9		T123	12		T56	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T158	14		T151	8		T223	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T39	5		T218	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	9		T55	13		T56	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1356	1			T1	27		T54	2		T206	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9