Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23090

1

T1

30

T2

3

T3

74

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19902

1

T1

30

T2

3

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3188

1

T3

39

T7

3

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17374

1

T2

3

T3

56

T5

10

auto[1]

5716

1

T1

30

T3

18

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

30

T2

3

T3

56

auto[1]

3848

1

T3

18

T7

3

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	173	1			T11	7		T139	1		T31	23
values[0]	40	1			T143	21		T23	2		T174	1
values[1]	409	1			T3	21		T147	1		T134	1
values[2]	798	1			T25	5		T30	1		T37	14
values[3]	595	1			T5	10		T13	2		T14	1
values[4]	417	1			T122	13		T54	10		T124	12
values[5]	2985	1			T1	30		T3	18		T8	11
values[6]	925	1			T12	1		T15	15		T27	7
values[7]	607	1			T14	1		T25	3		T122	12
values[8]	606	1			T12	1		T14	1		T15	12
values[9]	1137	1			T2	2		T7	3		T13	1
minimum	14398	1			T2	1		T3	35		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	489	1			T3	21		T147	1		T56	7
values[1]	811	1			T25	5		T30	1		T37	14
values[2]	509	1			T5	10		T13	2		T14	1
values[3]	2802	1			T1	30		T8	11		T28	10
values[4]	793	1			T3	18		T12	1		T27	7
values[5]	834	1			T12	1		T15	15		T122	12
values[6]	548	1			T14	1		T25	3		T117	21
values[7]	725	1			T12	1		T14	1		T15	12
values[8]	927	1			T2	2		T7	3		T11	7
values[9]	168	1			T139	1		T219	15		T277	1
minimum	14484	1			T2	1		T3	35		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

3984

1

T1

27

T3

19

T5

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T147	1		T56	4		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	11		T199	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T37	14		T38	20		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	4		T30	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	10		T15	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	2		T14	1		T56	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T1	30		T8	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T122	1		T117	10		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T27	1		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	10		T115	12		T128	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T170	1		T45	16		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T15	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T115	6		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	3		T117	21		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T14	1		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	1		T135	1		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T2	2		T11	7		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	2		T39	6		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T292	1		T293	9		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T139	1		T219	1		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14323	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T153	2		T273	1		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	3		T121	11		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T3	10		T199	15		T203	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	17		T123	10		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	1		T122	9		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	2		T38	6		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T56	4		T119	2		T229	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T8	10		T28	9		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	12		T124	11		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	6		T125	8		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	8		T115	11		T128	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T170	11		T45	11		T150	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	14		T122	11		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T115	4		T241	2		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T199	2		T136	12		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T158	15		T126	1		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	11		T158	11		T199	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T56	16		T129	10		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T39	6		T54	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T219	14		T269	7		T294	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	2		T25	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T295	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T11	7		T139	1		T31	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T242	11		T160	13		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T143	11		T234	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T23	2		T174	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T147	1		T134	1		T56	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	11		T199	1		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T37	14		T38	20		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	4		T30	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	10		T15	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	2		T14	1		T56	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T54	3		T36	1		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T122	1		T124	1		T233	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T1	30		T8	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	10		T117	10		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	1		T170	1		T45	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	1		T15	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T115	6		T150	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T25	3		T122	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T14	1		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	1		T117	21		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T2	2		T13	1		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	2		T39	6		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14280	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T31	15		T267	3		T230	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T242	11		T160	12		T219	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T143	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T56	3		T126	9		T121	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T3	10		T199	15		T203	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T38	17		T123	10		T246	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	1		T122	9		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	2		T38	6		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T56	4		T119	2		T229	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T54	7		T205	4		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T122	12		T124	11		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T8	10		T28	9		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	8		T115	11		T128	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	6		T170	11		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	14		T38	4		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T115	4		T150	18		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T122	11		T136	12		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T158	15		T31	8		T241	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	11		T158	11		T199	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T56	16		T126	1		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T7	1		T39	6		T54	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T25	3		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	1		T56	4		T121	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	11		T199	16		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T37	1		T38	18		T123	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	4		T30	1		T122	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T15	3		T38	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	2		T14	1		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T1	3		T8	11		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	13		T117	1		T124	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T27	7		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	9		T115	12		T128	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T170	12		T45	12		T150	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T15	15		T122	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T115	5		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	2		T117	2		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T14	1		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	12		T135	1		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T2	2		T11	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	2		T39	7		T54	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T292	1		T293	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T139	1		T219	15		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14433	1			T2	1		T3	35		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T153	2		T273	1		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T56	3		T202	11		T211	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	10		T19	1		T255	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T37	13		T38	19		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	1		T123	12		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	9		T197	8		T203	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T56	8		T119	5		T229	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T1	27		T54	2		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T117	9		T133	12		T296	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T125	9		T150	5		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	9		T115	11		T54	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	15		T150	7		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	10		T151	8		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T115	5		T242	4		T208	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T25	1		T117	19		T205	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T158	14		T151	8		T255	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T158	11		T177	1		T256	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	6		T56	16		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	1		T39	5		T120	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T293	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T154	10		T269	7		T297	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T126	8		T143	10		T287	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T11	1		T139	1		T31	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T242	12		T160	13		T219	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T143	11		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T23	2		T174	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T147	1		T134	1		T56	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	11		T199	16		T203	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	1		T38	18		T123	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	4		T30	1		T122	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T15	3		T38	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	2		T14	1		T56	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T54	8		T36	1		T205	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T122	13		T124	12		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T1	3		T8	11		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	9		T117	1		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T27	7		T170	12		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	1		T15	15		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	1		T115	5		T150	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T25	2		T122	12		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T14	1		T158	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	12		T117	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	2		T13	1		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	2		T39	7		T54	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T2	1		T3	35		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T11	6		T31	7		T285	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T242	10		T160	12		T289	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T143	10		T234	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T56	3		T126	8		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T3	10		T19	1		T255	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T37	13		T38	19		T123	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	1		T123	12		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	9		T32	1		T197	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T56	8		T119	5		T229	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T54	2		T231	1		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T233	12		T216	7		T298	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T1	27		T206	12		T207	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	9		T117	9		T115	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	15		T150	5		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	10		T151	8		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T115	5		T150	7		T233	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T25	1		T205	9		T289	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T158	14		T151	8		T208	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T117	19		T158	11		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T56	16		T129	14		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T39	5		T120	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19106

1

T1

3

T2

3

T3

55

auto[1]

auto[0]

3984

1

T1

27

T3

19

T5

9