Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.97


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T308 /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1368160616 Aug 18 05:42:57 PM PDT 24 Aug 18 05:55:44 PM PDT 24 325537805478 ps
T797 /workspace/coverage/default/45.adc_ctrl_smoke.3749733076 Aug 18 05:44:19 PM PDT 24 Aug 18 05:44:33 PM PDT 24 5805055265 ps
T798 /workspace/coverage/default/31.adc_ctrl_filters_polled.1748319304 Aug 18 05:43:25 PM PDT 24 Aug 18 05:44:55 PM PDT 24 161141148229 ps
T799 /workspace/coverage/default/2.adc_ctrl_poweron_counter.2603064178 Aug 18 05:42:38 PM PDT 24 Aug 18 05:42:47 PM PDT 24 3011142004 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2673366258 Aug 18 05:41:49 PM PDT 24 Aug 18 05:41:51 PM PDT 24 384266757 ps
T800 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3285294084 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:00 PM PDT 24 305043404 ps
T801 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.342991607 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:48 PM PDT 24 536192752 ps
T50 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3242893392 Aug 18 05:41:57 PM PDT 24 Aug 18 05:42:07 PM PDT 24 4283425823 ps
T53 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.976950254 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:59 PM PDT 24 1901556460 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3194063019 Aug 18 05:42:09 PM PDT 24 Aug 18 05:42:17 PM PDT 24 9170469781 ps
T802 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4215078136 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 436933324 ps
T93 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.750929414 Aug 18 05:42:14 PM PDT 24 Aug 18 05:42:15 PM PDT 24 378224327 ps
T803 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1939993950 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:56 PM PDT 24 539572590 ps
T78 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1057064046 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:00 PM PDT 24 407034290 ps
T804 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.326604907 Aug 18 05:42:06 PM PDT 24 Aug 18 05:42:06 PM PDT 24 509952402 ps
T51 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2336502913 Aug 18 05:42:11 PM PDT 24 Aug 18 05:42:53 PM PDT 24 20383430771 ps
T805 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2938470772 Aug 18 05:42:24 PM PDT 24 Aug 18 05:42:25 PM PDT 24 540270966 ps
T71 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3649937724 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:01 PM PDT 24 555798525 ps
T58 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3539158574 Aug 18 05:41:42 PM PDT 24 Aug 18 05:41:48 PM PDT 24 4272469600 ps
T113 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1893253715 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:55 PM PDT 24 409376168 ps
T806 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1676278016 Aug 18 05:42:16 PM PDT 24 Aug 18 05:42:17 PM PDT 24 371893264 ps
T64 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3388255803 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:55 PM PDT 24 550637326 ps
T52 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.509192996 Aug 18 05:42:04 PM PDT 24 Aug 18 05:42:06 PM PDT 24 3621894862 ps
T110 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1970554610 Aug 18 05:42:07 PM PDT 24 Aug 18 05:42:14 PM PDT 24 4431943237 ps
T98 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3750965365 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 578875552 ps
T99 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4162306796 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:48 PM PDT 24 545924267 ps
T807 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3937627849 Aug 18 05:42:19 PM PDT 24 Aug 18 05:42:20 PM PDT 24 520096682 ps
T808 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3581718968 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:58 PM PDT 24 301928019 ps
T79 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2635321137 Aug 18 05:42:22 PM PDT 24 Aug 18 05:42:24 PM PDT 24 366107017 ps
T59 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2654911041 Aug 18 05:41:40 PM PDT 24 Aug 18 05:41:45 PM PDT 24 4636985123 ps
T94 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.258059536 Aug 18 05:41:42 PM PDT 24 Aug 18 05:41:44 PM PDT 24 435815579 ps
T67 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1387018047 Aug 18 05:41:51 PM PDT 24 Aug 18 05:41:53 PM PDT 24 314526274 ps
T809 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2281936747 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:49 PM PDT 24 496064174 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.60620668 Aug 18 05:41:49 PM PDT 24 Aug 18 05:41:51 PM PDT 24 708045016 ps
T100 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3934247098 Aug 18 05:41:51 PM PDT 24 Aug 18 05:41:52 PM PDT 24 1455400116 ps
T68 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.858605985 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:56 PM PDT 24 531113652 ps
T810 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.581536645 Aug 18 05:41:49 PM PDT 24 Aug 18 05:41:50 PM PDT 24 310857962 ps
T331 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.581491548 Aug 18 05:42:06 PM PDT 24 Aug 18 05:42:11 PM PDT 24 4323405340 ps
T811 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1546583170 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:00 PM PDT 24 545812264 ps
T101 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1257986693 Aug 18 05:42:07 PM PDT 24 Aug 18 05:42:09 PM PDT 24 415622436 ps
T812 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2769122648 Aug 18 05:42:02 PM PDT 24 Aug 18 05:42:04 PM PDT 24 460992487 ps
T813 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2977420748 Aug 18 05:42:09 PM PDT 24 Aug 18 05:42:10 PM PDT 24 538373664 ps
T814 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2597430380 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 311774827 ps
T102 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4182220026 Aug 18 05:41:50 PM PDT 24 Aug 18 05:41:52 PM PDT 24 522288455 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2258455968 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:53 PM PDT 24 2707827264 ps
T103 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.69283553 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:59 PM PDT 24 534741319 ps
T815 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3005516444 Aug 18 05:42:11 PM PDT 24 Aug 18 05:42:13 PM PDT 24 505332058 ps
T816 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2172215525 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:58 PM PDT 24 425048117 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1134426670 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 351936165 ps
T104 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3635641894 Aug 18 05:42:04 PM PDT 24 Aug 18 05:42:07 PM PDT 24 846210256 ps
T817 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.896024188 Aug 18 05:42:15 PM PDT 24 Aug 18 05:42:18 PM PDT 24 518477279 ps
T105 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4222855290 Aug 18 05:41:50 PM PDT 24 Aug 18 05:42:18 PM PDT 24 40164976375 ps
T818 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1089006882 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:49 PM PDT 24 548413721 ps
T80 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1912540533 Aug 18 05:41:43 PM PDT 24 Aug 18 05:41:50 PM PDT 24 4487292028 ps
T819 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2567676378 Aug 18 05:42:12 PM PDT 24 Aug 18 05:42:14 PM PDT 24 414159221 ps
T820 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3244270938 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:56 PM PDT 24 324412373 ps
T76 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1002967613 Aug 18 05:42:19 PM PDT 24 Aug 18 05:42:20 PM PDT 24 509080466 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4234116395 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:57 PM PDT 24 2301659008 ps
T65 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2199691643 Aug 18 05:42:03 PM PDT 24 Aug 18 05:42:05 PM PDT 24 496459718 ps
T66 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1336435147 Aug 18 05:41:56 PM PDT 24 Aug 18 05:42:01 PM PDT 24 9052669577 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.12270857 Aug 18 05:42:12 PM PDT 24 Aug 18 05:42:16 PM PDT 24 3961078664 ps
T81 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1761175020 Aug 18 05:41:51 PM PDT 24 Aug 18 05:42:09 PM PDT 24 8114582980 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1710468723 Aug 18 05:41:58 PM PDT 24 Aug 18 05:42:00 PM PDT 24 393240798 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1858283332 Aug 18 05:41:58 PM PDT 24 Aug 18 05:41:59 PM PDT 24 530040003 ps
T825 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.686178175 Aug 18 05:41:55 PM PDT 24 Aug 18 05:42:01 PM PDT 24 367731800 ps
T826 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.657627480 Aug 18 05:42:12 PM PDT 24 Aug 18 05:42:14 PM PDT 24 432664629 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.821280407 Aug 18 05:42:21 PM PDT 24 Aug 18 05:42:30 PM PDT 24 1062338169 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1229306206 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:56 PM PDT 24 2843290464 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.207047775 Aug 18 05:41:58 PM PDT 24 Aug 18 05:41:59 PM PDT 24 439626142 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.115828403 Aug 18 05:41:58 PM PDT 24 Aug 18 05:42:00 PM PDT 24 560767011 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2958182050 Aug 18 05:42:09 PM PDT 24 Aug 18 05:42:11 PM PDT 24 340259609 ps
T831 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.970799736 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:58 PM PDT 24 2202920045 ps
T73 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3951087050 Aug 18 05:41:42 PM PDT 24 Aug 18 05:41:44 PM PDT 24 412094815 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.793640547 Aug 18 05:41:58 PM PDT 24 Aug 18 05:42:15 PM PDT 24 4462953405 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3171255437 Aug 18 05:41:51 PM PDT 24 Aug 18 05:41:56 PM PDT 24 2737653387 ps
T834 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2316096318 Aug 18 05:42:11 PM PDT 24 Aug 18 05:42:23 PM PDT 24 4353624549 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.254515800 Aug 18 05:41:43 PM PDT 24 Aug 18 05:41:55 PM PDT 24 4232599044 ps
T836 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3287448798 Aug 18 05:42:15 PM PDT 24 Aug 18 05:42:15 PM PDT 24 566980434 ps
T837 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3980392081 Aug 18 05:42:11 PM PDT 24 Aug 18 05:42:12 PM PDT 24 441223631 ps
T838 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4242971857 Aug 18 05:42:15 PM PDT 24 Aug 18 05:42:16 PM PDT 24 405224445 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1873386576 Aug 18 05:41:49 PM PDT 24 Aug 18 05:42:15 PM PDT 24 26921439613 ps
T332 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3579035754 Aug 18 05:41:58 PM PDT 24 Aug 18 05:42:04 PM PDT 24 4332407245 ps
T107 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1267708745 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:01 PM PDT 24 467095310 ps
T75 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3909191091 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:55 PM PDT 24 688540337 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2617359397 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:56 PM PDT 24 504021011 ps
T841 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2565943555 Aug 18 05:42:03 PM PDT 24 Aug 18 05:42:04 PM PDT 24 565269752 ps
T842 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4017614678 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:59 PM PDT 24 520110470 ps
T333 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.808495373 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:54 PM PDT 24 8298816321 ps
T108 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.980870316 Aug 18 05:42:10 PM PDT 24 Aug 18 05:42:12 PM PDT 24 938277781 ps
T843 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4216318034 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:56 PM PDT 24 536771767 ps
T844 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3954873771 Aug 18 05:42:17 PM PDT 24 Aug 18 05:42:19 PM PDT 24 512682860 ps
T845 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.643475944 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:57 PM PDT 24 483033661 ps
T846 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2622893317 Aug 18 05:42:21 PM PDT 24 Aug 18 05:42:37 PM PDT 24 4321202174 ps
T847 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4102934078 Aug 18 05:42:04 PM PDT 24 Aug 18 05:42:06 PM PDT 24 540655351 ps
T848 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.363222974 Aug 18 05:42:01 PM PDT 24 Aug 18 05:42:02 PM PDT 24 385089011 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2248486272 Aug 18 05:41:52 PM PDT 24 Aug 18 05:42:05 PM PDT 24 4563916777 ps
T850 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.222684839 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:58 PM PDT 24 446903357 ps
T851 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.241041035 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:49 PM PDT 24 1383896691 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2201844213 Aug 18 05:41:42 PM PDT 24 Aug 18 05:42:03 PM PDT 24 8207223643 ps
T853 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.725185821 Aug 18 05:41:46 PM PDT 24 Aug 18 05:41:52 PM PDT 24 4856451402 ps
T854 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.117094933 Aug 18 05:41:52 PM PDT 24 Aug 18 05:41:53 PM PDT 24 476783189 ps
T77 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1446761833 Aug 18 05:42:27 PM PDT 24 Aug 18 05:42:29 PM PDT 24 2400895455 ps
T72 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2800770459 Aug 18 05:41:50 PM PDT 24 Aug 18 05:41:53 PM PDT 24 438848727 ps
T855 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.83455944 Aug 18 05:42:12 PM PDT 24 Aug 18 05:42:13 PM PDT 24 482672956 ps
T856 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2788170689 Aug 18 05:42:21 PM PDT 24 Aug 18 05:42:22 PM PDT 24 534082849 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3832084329 Aug 18 05:42:10 PM PDT 24 Aug 18 05:42:11 PM PDT 24 721728377 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1636254957 Aug 18 05:42:14 PM PDT 24 Aug 18 05:42:18 PM PDT 24 4726141851 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3094725403 Aug 18 05:41:56 PM PDT 24 Aug 18 05:41:57 PM PDT 24 532213213 ps
T860 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2774841579 Aug 18 05:41:54 PM PDT 24 Aug 18 05:42:09 PM PDT 24 8156047964 ps
T861 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1089670521 Aug 18 05:42:12 PM PDT 24 Aug 18 05:42:14 PM PDT 24 584390030 ps
T862 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.614107541 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:59 PM PDT 24 651085448 ps
T863 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4004598234 Aug 18 05:42:13 PM PDT 24 Aug 18 05:42:14 PM PDT 24 428546464 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2510452851 Aug 18 05:42:32 PM PDT 24 Aug 18 05:42:34 PM PDT 24 593988540 ps
T865 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3694220939 Aug 18 05:42:01 PM PDT 24 Aug 18 05:42:03 PM PDT 24 368564177 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2115955506 Aug 18 05:42:14 PM PDT 24 Aug 18 05:42:15 PM PDT 24 307139633 ps
T867 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4018189027 Aug 18 05:41:58 PM PDT 24 Aug 18 05:41:59 PM PDT 24 433163478 ps
T868 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3293738228 Aug 18 05:42:16 PM PDT 24 Aug 18 05:42:18 PM PDT 24 465053641 ps
T869 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.962384696 Aug 18 05:41:58 PM PDT 24 Aug 18 05:41:59 PM PDT 24 425099884 ps
T109 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1105974557 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:01 PM PDT 24 468764515 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3445936937 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:58 PM PDT 24 509095254 ps
T871 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2743648603 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:58 PM PDT 24 474642750 ps
T872 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2731595078 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:57 PM PDT 24 413988018 ps
T873 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3393618567 Aug 18 05:42:00 PM PDT 24 Aug 18 05:42:01 PM PDT 24 388443557 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2936482074 Aug 18 05:42:13 PM PDT 24 Aug 18 05:44:17 PM PDT 24 52904161886 ps
T875 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2014559973 Aug 18 05:41:45 PM PDT 24 Aug 18 05:41:50 PM PDT 24 4245316364 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2980418125 Aug 18 05:42:00 PM PDT 24 Aug 18 05:42:03 PM PDT 24 1872023779 ps
T877 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4256737341 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:50 PM PDT 24 815110710 ps
T878 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3208513720 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:58 PM PDT 24 362752506 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.404484036 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:51 PM PDT 24 2256252544 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3818939474 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:49 PM PDT 24 614132952 ps
T881 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1374195649 Aug 18 05:42:07 PM PDT 24 Aug 18 05:42:08 PM PDT 24 609727538 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.559955870 Aug 18 05:42:00 PM PDT 24 Aug 18 05:42:05 PM PDT 24 4673817236 ps
T883 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.13296957 Aug 18 05:42:15 PM PDT 24 Aug 18 05:42:17 PM PDT 24 621758414 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3639686245 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 565656941 ps
T885 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3316833855 Aug 18 05:41:52 PM PDT 24 Aug 18 05:41:56 PM PDT 24 572931419 ps
T886 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2221134366 Aug 18 05:42:28 PM PDT 24 Aug 18 05:42:29 PM PDT 24 559723119 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3635765650 Aug 18 05:41:43 PM PDT 24 Aug 18 05:41:45 PM PDT 24 1390457014 ps
T888 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.86893004 Aug 18 05:42:17 PM PDT 24 Aug 18 05:42:19 PM PDT 24 517791952 ps
T889 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4169131562 Aug 18 05:41:49 PM PDT 24 Aug 18 05:41:50 PM PDT 24 443051812 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1614619779 Aug 18 05:42:19 PM PDT 24 Aug 18 05:42:24 PM PDT 24 5418845286 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.197896448 Aug 18 05:41:53 PM PDT 24 Aug 18 05:41:55 PM PDT 24 461838090 ps
T892 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4150669246 Aug 18 05:41:43 PM PDT 24 Aug 18 05:41:55 PM PDT 24 4520857168 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4276815403 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:50 PM PDT 24 548678552 ps
T894 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2730247689 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:56 PM PDT 24 392362789 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3918168290 Aug 18 05:42:00 PM PDT 24 Aug 18 05:42:08 PM PDT 24 2488129052 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4174725635 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:00 PM PDT 24 538154112 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.194389764 Aug 18 05:41:48 PM PDT 24 Aug 18 05:41:54 PM PDT 24 1258703040 ps
T898 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1768345377 Aug 18 05:42:26 PM PDT 24 Aug 18 05:42:29 PM PDT 24 5270986943 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2378142218 Aug 18 05:41:57 PM PDT 24 Aug 18 05:41:59 PM PDT 24 633736531 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3770517117 Aug 18 05:41:59 PM PDT 24 Aug 18 05:42:00 PM PDT 24 442441472 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3023095479 Aug 18 05:42:05 PM PDT 24 Aug 18 05:42:08 PM PDT 24 459642053 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1162557358 Aug 18 05:41:50 PM PDT 24 Aug 18 05:41:57 PM PDT 24 539963605 ps
T903 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3964188187 Aug 18 05:42:08 PM PDT 24 Aug 18 05:42:13 PM PDT 24 9507932319 ps
T904 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.967478748 Aug 18 05:42:01 PM PDT 24 Aug 18 05:42:02 PM PDT 24 617222261 ps
T905 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.838364243 Aug 18 05:42:10 PM PDT 24 Aug 18 05:42:11 PM PDT 24 396911547 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3644621683 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:55 PM PDT 24 542592525 ps
T907 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3020372171 Aug 18 05:41:54 PM PDT 24 Aug 18 05:41:56 PM PDT 24 531685290 ps
T908 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3341173781 Aug 18 05:42:30 PM PDT 24 Aug 18 05:42:31 PM PDT 24 516626990 ps
T909 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1029806994 Aug 18 05:41:44 PM PDT 24 Aug 18 05:41:47 PM PDT 24 4518009042 ps
T910 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1987393782 Aug 18 05:41:46 PM PDT 24 Aug 18 05:42:06 PM PDT 24 4915774024 ps
T911 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4003856066 Aug 18 05:41:48 PM PDT 24 Aug 18 05:42:09 PM PDT 24 8159391464 ps
T912 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1890332151 Aug 18 05:42:23 PM PDT 24 Aug 18 05:42:23 PM PDT 24 351408033 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2377336915 Aug 18 05:42:02 PM PDT 24 Aug 18 05:42:22 PM PDT 24 14388327301 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1263677983 Aug 18 05:41:39 PM PDT 24 Aug 18 05:41:41 PM PDT 24 377777993 ps
T915 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2254925953 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:56 PM PDT 24 431901052 ps
T916 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4159279732 Aug 18 05:42:06 PM PDT 24 Aug 18 05:42:08 PM PDT 24 467441284 ps
T917 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3575120488 Aug 18 05:42:05 PM PDT 24 Aug 18 05:42:06 PM PDT 24 384332564 ps
T918 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2824032252 Aug 18 05:41:47 PM PDT 24 Aug 18 05:41:51 PM PDT 24 1111432194 ps
T919 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.635970838 Aug 18 05:41:55 PM PDT 24 Aug 18 05:41:56 PM PDT 24 352633454 ps

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.871706297
Short name T7
Test name
Test status
Simulation time 163273826754 ps
CPU time 13 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:43:37 PM PDT 24
Peak memory 210284 kb
Host smart-e179bf8a-6c9b-4433-a312-e607389fb236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871706297 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.871706297
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.884222550
Short name T15
Test name
Test status
Simulation time 489700510342 ps
CPU time 147.96 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:45:53 PM PDT 24
Peak memory 202112 kb
Host smart-6c5e8f6c-17a9-48b7-b146-cb5af1779658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884222550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.884222550
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4025768376
Short name T39
Test name
Test status
Simulation time 332314098331 ps
CPU time 708.34 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:55:14 PM PDT 24
Peak memory 210608 kb
Host smart-bd562c7f-de9d-4de9-ac54-520ba6d2a5aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025768376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4025768376
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.65867041
Short name T56
Test name
Test status
Simulation time 533072785778 ps
CPU time 1164.99 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 202108 kb
Host smart-2cbbf8d6-bdf1-44ef-915e-d9a490b18b1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65867041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gatin
g.65867041
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1647036592
Short name T38
Test name
Test status
Simulation time 507650243275 ps
CPU time 583.81 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:53:29 PM PDT 24
Peak memory 202120 kb
Host smart-6378e492-e26d-4f76-8881-f95b6e7d2d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647036592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1647036592
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3234216787
Short name T13
Test name
Test status
Simulation time 14237783291 ps
CPU time 13.64 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:44:02 PM PDT 24
Peak memory 210380 kb
Host smart-d2bd5c37-1204-4afa-9fd1-4d8138f7dd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234216787 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3234216787
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2649610338
Short name T205
Test name
Test status
Simulation time 524894370177 ps
CPU time 940.34 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:59:17 PM PDT 24
Peak memory 210492 kb
Host smart-4941ca91-b30f-427c-b8af-0f349e9758af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649610338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2649610338
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.791885805
Short name T289
Test name
Test status
Simulation time 407041087786 ps
CPU time 1069.04 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 202392 kb
Host smart-c17be8c0-190d-4e02-9f79-3d099f5b85a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791885805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
791885805
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3460491589
Short name T158
Test name
Test status
Simulation time 338234977462 ps
CPU time 179.61 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:46:02 PM PDT 24
Peak memory 202040 kb
Host smart-3e92398c-6de9-4b83-b574-b49651ae9161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460491589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3460491589
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1327568302
Short name T12
Test name
Test status
Simulation time 491309538764 ps
CPU time 259.36 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:48:39 PM PDT 24
Peak memory 202128 kb
Host smart-594b731a-930e-44a2-b7f7-0bae06041f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327568302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1327568302
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3565050381
Short name T150
Test name
Test status
Simulation time 366048663063 ps
CPU time 171.51 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:46:15 PM PDT 24
Peak memory 202000 kb
Host smart-f606b9d6-ee35-432f-b215-b936e485f90e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565050381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3565050381
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3194063019
Short name T57
Test name
Test status
Simulation time 9170469781 ps
CPU time 7.37 seconds
Started Aug 18 05:42:09 PM PDT 24
Finished Aug 18 05:42:17 PM PDT 24
Peak memory 201140 kb
Host smart-db29b65a-9347-4931-a7eb-456d8e661104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194063019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3194063019
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2460575132
Short name T172
Test name
Test status
Simulation time 482615127209 ps
CPU time 140.73 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 05:46:20 PM PDT 24
Peak memory 202108 kb
Host smart-3b4a39ba-f580-48bc-9f1c-333527451695
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460575132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2460575132
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3929061234
Short name T171
Test name
Test status
Simulation time 381339059619 ps
CPU time 197.65 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 05:47:16 PM PDT 24
Peak memory 202088 kb
Host smart-9ed22f7f-1d0c-4444-96e2-b030dcec9fc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929061234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3929061234
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2180911781
Short name T115
Test name
Test status
Simulation time 377993096166 ps
CPU time 412.73 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 202076 kb
Host smart-85382bd5-62d2-4c7d-9f9c-2061d9a8d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180911781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2180911781
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1940115772
Short name T219
Test name
Test status
Simulation time 492849035070 ps
CPU time 1178.69 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 06:04:00 PM PDT 24
Peak memory 202096 kb
Host smart-75e537e4-1889-4e59-9f37-317d265a293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940115772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1940115772
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3750965365
Short name T98
Test name
Test status
Simulation time 578875552 ps
CPU time 1.52 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200852 kb
Host smart-694269b4-733b-43d2-a551-50ac87948700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750965365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3750965365
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.142545899
Short name T364
Test name
Test status
Simulation time 399496136 ps
CPU time 1.16 seconds
Started Aug 18 05:42:59 PM PDT 24
Finished Aug 18 05:43:00 PM PDT 24
Peak memory 201856 kb
Host smart-5721aa5c-40cf-47c5-8926-246574ee6443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142545899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.142545899
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1708712406
Short name T122
Test name
Test status
Simulation time 491463801852 ps
CPU time 333.78 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:48:58 PM PDT 24
Peak memory 202108 kb
Host smart-29ea5066-a082-49d1-b84a-0a0a208ccd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708712406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1708712406
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.618107213
Short name T211
Test name
Test status
Simulation time 514426630224 ps
CPU time 1172.21 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 202092 kb
Host smart-de4db8b3-39ad-4414-b871-6960f88682fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618107213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.618107213
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1405431674
Short name T3
Test name
Test status
Simulation time 336479021283 ps
CPU time 145.64 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:45:41 PM PDT 24
Peak memory 202120 kb
Host smart-8effd18b-49d8-404b-8df9-de0b654b21c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405431674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1405431674
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3388255803
Short name T64
Test name
Test status
Simulation time 550637326 ps
CPU time 1.72 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 201128 kb
Host smart-0d429b6b-46ba-4680-9a4f-a1c7155ffb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388255803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3388255803
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.818568000
Short name T214
Test name
Test status
Simulation time 370355337379 ps
CPU time 807.35 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:57:11 PM PDT 24
Peak memory 202020 kb
Host smart-4670a1b0-1c41-4958-b810-1a7ad40681c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818568000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.818568000
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1228055344
Short name T222
Test name
Test status
Simulation time 490402161763 ps
CPU time 350.44 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:49:08 PM PDT 24
Peak memory 202128 kb
Host smart-a1537dbe-c3e7-4432-a477-e8ecd3a2feb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228055344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1228055344
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2057077132
Short name T1
Test name
Test status
Simulation time 615309885858 ps
CPU time 350.11 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:49:25 PM PDT 24
Peak memory 201996 kb
Host smart-8a5982cd-3716-411c-bae5-c81c5c63d255
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057077132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2057077132
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4106247425
Short name T160
Test name
Test status
Simulation time 524424065410 ps
CPU time 146.6 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:45:53 PM PDT 24
Peak memory 202176 kb
Host smart-e1cdbe93-4639-439d-b49f-d5dcd0eb5a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106247425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4106247425
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1664619055
Short name T216
Test name
Test status
Simulation time 970045315099 ps
CPU time 687.54 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:54:42 PM PDT 24
Peak memory 212976 kb
Host smart-027eb24f-7065-4c49-9373-d8ed07d9a16e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664619055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1664619055
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.399845866
Short name T234
Test name
Test status
Simulation time 573466160174 ps
CPU time 1272 seconds
Started Aug 18 05:44:24 PM PDT 24
Finished Aug 18 06:05:36 PM PDT 24
Peak memory 202100 kb
Host smart-07acef6a-5b1c-4e90-8209-97569d1d9fce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399845866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.399845866
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3055368494
Short name T61
Test name
Test status
Simulation time 4248386203 ps
CPU time 5.26 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:42:41 PM PDT 24
Peak memory 217352 kb
Host smart-477e3da6-05c2-403e-8dd7-cbcc6c76432e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055368494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3055368494
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2006856766
Short name T25
Test name
Test status
Simulation time 58338914691 ps
CPU time 13.39 seconds
Started Aug 18 05:43:00 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 210496 kb
Host smart-5af32031-820d-440f-968e-b0b5f7cd7690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006856766 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2006856766
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.397032818
Short name T141
Test name
Test status
Simulation time 491046516218 ps
CPU time 573.4 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 202144 kb
Host smart-336039c9-e708-420d-bb25-cfd850f2da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397032818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.397032818
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2644844850
Short name T278
Test name
Test status
Simulation time 522992046374 ps
CPU time 1203.49 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 06:03:21 PM PDT 24
Peak memory 202100 kb
Host smart-c5d93cde-ee8b-48ee-8b28-0c1d3b4a077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644844850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2644844850
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.619181952
Short name T14
Test name
Test status
Simulation time 492772191604 ps
CPU time 1088.91 seconds
Started Aug 18 05:44:01 PM PDT 24
Finished Aug 18 06:02:10 PM PDT 24
Peak memory 202164 kb
Host smart-e9b3020d-22f5-476f-bc94-2ec366c991e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619181952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.619181952
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4066181246
Short name T270
Test name
Test status
Simulation time 9106035603 ps
CPU time 6.12 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:35 PM PDT 24
Peak memory 202088 kb
Host smart-fca77241-3bbc-4266-a7c2-236e9e2e987d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066181246 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4066181246
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3682056247
Short name T201
Test name
Test status
Simulation time 523628345163 ps
CPU time 1248.29 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 06:04:35 PM PDT 24
Peak memory 202128 kb
Host smart-fd9fad06-8c11-4f53-9b47-ec0d043da20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682056247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3682056247
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1265439624
Short name T138
Test name
Test status
Simulation time 513092524937 ps
CPU time 925.97 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:58:59 PM PDT 24
Peak memory 202096 kb
Host smart-506d487e-0d0e-445f-8bcc-c311838b6e9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265439624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1265439624
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1550795460
Short name T235
Test name
Test status
Simulation time 463540571223 ps
CPU time 199.83 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:47:42 PM PDT 24
Peak memory 202136 kb
Host smart-1f50ef0f-d395-4c26-93d0-b95fb0b58ba8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550795460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1550795460
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3734812651
Short name T230
Test name
Test status
Simulation time 323945968436 ps
CPU time 690.31 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:54:39 PM PDT 24
Peak memory 202136 kb
Host smart-4028be01-d12b-4433-8b36-a562c8d5d15c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734812651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3734812651
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1638485484
Short name T136
Test name
Test status
Simulation time 322126637037 ps
CPU time 684.81 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:55:15 PM PDT 24
Peak memory 202096 kb
Host smart-9a298438-e34a-4a00-b9ae-2b6b88e8f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638485484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1638485484
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.988124872
Short name T176
Test name
Test status
Simulation time 528213065753 ps
CPU time 328.39 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:48:47 PM PDT 24
Peak memory 202124 kb
Host smart-1a53f6b0-de30-4e49-9420-f7337bdfce2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988124872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.988124872
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1479715904
Short name T283
Test name
Test status
Simulation time 56528108249 ps
CPU time 12.06 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:44:34 PM PDT 24
Peak memory 210540 kb
Host smart-f6663689-47dc-41fc-93ce-930d633c4e42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479715904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1479715904
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.715486616
Short name T321
Test name
Test status
Simulation time 167410207682 ps
CPU time 390.45 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:50:01 PM PDT 24
Peak memory 202112 kb
Host smart-98391fd9-4113-4891-a67e-cdc332abb02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715486616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
715486616
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1105057960
Short name T40
Test name
Test status
Simulation time 201654418082 ps
CPU time 800.65 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 202316 kb
Host smart-bee9586a-af97-4926-8734-5dd4ee6a0d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105057960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1105057960
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3916711829
Short name T245
Test name
Test status
Simulation time 343369491891 ps
CPU time 711.29 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:55:06 PM PDT 24
Peak memory 202112 kb
Host smart-40422963-a5aa-413e-9e9f-15badb24905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916711829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3916711829
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.658570278
Short name T293
Test name
Test status
Simulation time 621484343521 ps
CPU time 140.01 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:44:58 PM PDT 24
Peak memory 201932 kb
Host smart-5bb6bb1e-ab27-4996-b4ef-c3cdee90d657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658570278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.658570278
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2930523874
Short name T174
Test name
Test status
Simulation time 327828045433 ps
CPU time 50.9 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:44:10 PM PDT 24
Peak memory 202108 kb
Host smart-b5af4a79-e47b-4ac4-8d0d-3cbcdcf9df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930523874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2930523874
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4131915132
Short name T179
Test name
Test status
Simulation time 924828606035 ps
CPU time 2296.43 seconds
Started Aug 18 05:44:00 PM PDT 24
Finished Aug 18 06:22:16 PM PDT 24
Peak memory 202396 kb
Host smart-177be5cf-4e29-4297-94d3-c68a406c0f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131915132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4131915132
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1421279600
Short name T302
Test name
Test status
Simulation time 514347376920 ps
CPU time 604.62 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:53:13 PM PDT 24
Peak memory 202096 kb
Host smart-8949fe9c-4c1e-4eda-92e9-b29984f64875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421279600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1421279600
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4215328793
Short name T117
Test name
Test status
Simulation time 572880571682 ps
CPU time 1248.05 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 06:04:13 PM PDT 24
Peak memory 202076 kb
Host smart-6fff043b-96c9-4a27-9432-c6cc59fce7e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215328793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4215328793
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.214985758
Short name T307
Test name
Test status
Simulation time 506782301016 ps
CPU time 536.96 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 202072 kb
Host smart-cb9188de-ff01-41cd-aeb8-b8244eb09d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214985758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
214985758
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1513155079
Short name T54
Test name
Test status
Simulation time 530700179089 ps
CPU time 777.5 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 202004 kb
Host smart-5fcede14-9638-4dcd-9f4a-50bca530321a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513155079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1513155079
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4252052460
Short name T196
Test name
Test status
Simulation time 488266826565 ps
CPU time 379.3 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 202088 kb
Host smart-1c1e23b9-0f23-410b-b514-4ec28a5f12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252052460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4252052460
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3832084329
Short name T857
Test name
Test status
Simulation time 721728377 ps
CPU time 1.58 seconds
Started Aug 18 05:42:10 PM PDT 24
Finished Aug 18 05:42:11 PM PDT 24
Peak memory 201168 kb
Host smart-1def5a73-1e88-4de1-ba3b-fec3a3c36eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832084329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3832084329
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2751364690
Short name T319
Test name
Test status
Simulation time 509912028269 ps
CPU time 589.36 seconds
Started Aug 18 05:42:33 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 202096 kb
Host smart-808d97b2-a636-4d9b-b823-77957356c760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751364690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2751364690
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3581726672
Short name T276
Test name
Test status
Simulation time 204786483123 ps
CPU time 245.9 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:47:20 PM PDT 24
Peak memory 202160 kb
Host smart-e9236477-e7bc-4cb0-8b92-15edb302f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581726672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3581726672
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2096969044
Short name T151
Test name
Test status
Simulation time 548983166226 ps
CPU time 253.92 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:48:02 PM PDT 24
Peak memory 202096 kb
Host smart-744ee910-35e8-4148-9736-68b75cafb147
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096969044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2096969044
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2344325633
Short name T258
Test name
Test status
Simulation time 577914120157 ps
CPU time 1621.06 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 210568 kb
Host smart-02f6d08c-d2ca-46b9-8642-3586f2b1388d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344325633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2344325633
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.993709292
Short name T19
Test name
Test status
Simulation time 7385807931 ps
CPU time 10.67 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:44:31 PM PDT 24
Peak memory 210524 kb
Host smart-4ccd1cac-7975-4a9c-bf2a-817070ac5d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993709292 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.993709292
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3579863908
Short name T242
Test name
Test status
Simulation time 333693104555 ps
CPU time 176.79 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:45:57 PM PDT 24
Peak memory 202116 kb
Host smart-0d7ef352-52a6-4fbe-b721-6fba532b31ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579863908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3579863908
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1787383785
Short name T152
Test name
Test status
Simulation time 332463306325 ps
CPU time 365.06 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 202172 kb
Host smart-5526f462-2a8f-485e-8891-0fa8a17de307
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787383785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1787383785
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.224217078
Short name T262
Test name
Test status
Simulation time 11692828574 ps
CPU time 9.07 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:43:49 PM PDT 24
Peak memory 210660 kb
Host smart-7f2f8322-64d7-480d-9771-aaabccdce64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224217078 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.224217078
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3891934893
Short name T92
Test name
Test status
Simulation time 501060282147 ps
CPU time 294.17 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:49:14 PM PDT 24
Peak memory 202048 kb
Host smart-dfbe3d01-a6d3-4d38-a6c2-3ce7885de112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891934893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3891934893
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1912540533
Short name T80
Test name
Test status
Simulation time 4487292028 ps
CPU time 6.92 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 201164 kb
Host smart-82479794-60fa-4d69-aefc-395114229236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912540533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1912540533
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.296292366
Short name T225
Test name
Test status
Simulation time 324593025831 ps
CPU time 529.01 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:51:27 PM PDT 24
Peak memory 202160 kb
Host smart-a4dfdf2e-297c-4a19-8e24-a39d2de3eeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296292366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.296292366
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1514984287
Short name T128
Test name
Test status
Simulation time 332212907961 ps
CPU time 190.32 seconds
Started Aug 18 05:42:27 PM PDT 24
Finished Aug 18 05:45:38 PM PDT 24
Peak memory 202176 kb
Host smart-35c1753e-01cd-478e-81cc-53ae8a4f4018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514984287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1514984287
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2850543508
Short name T204
Test name
Test status
Simulation time 493846325163 ps
CPU time 1064.05 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 202108 kb
Host smart-04ad4ab4-95a4-4ec8-bb73-dea3bd09ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850543508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2850543508
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3093547963
Short name T143
Test name
Test status
Simulation time 169986382458 ps
CPU time 110.09 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:45:14 PM PDT 24
Peak memory 202164 kb
Host smart-9e4e7562-00eb-40fc-9f96-0cb7acc02d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093547963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3093547963
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.110542675
Short name T762
Test name
Test status
Simulation time 96290054645 ps
CPU time 403.97 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 202304 kb
Host smart-a33cd515-c6df-4714-8e6a-bdfb29d569ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110542675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.110542675
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3658609936
Short name T257
Test name
Test status
Simulation time 379587028026 ps
CPU time 836.53 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:57:11 PM PDT 24
Peak memory 202096 kb
Host smart-13aa9bca-15e8-4349-8206-45e65227848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658609936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3658609936
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1234907377
Short name T277
Test name
Test status
Simulation time 168087929296 ps
CPU time 96.06 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:44:46 PM PDT 24
Peak memory 202000 kb
Host smart-5a3afec8-ab1e-445a-9f28-ff66e0912f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234907377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1234907377
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.539564996
Short name T288
Test name
Test status
Simulation time 544965895709 ps
CPU time 1296.94 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 202072 kb
Host smart-7838f156-24f4-4e4e-a227-e71172e49317
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539564996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.539564996
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1793846455
Short name T197
Test name
Test status
Simulation time 161211813384 ps
CPU time 97.25 seconds
Started Aug 18 05:43:27 PM PDT 24
Finished Aug 18 05:45:04 PM PDT 24
Peak memory 202116 kb
Host smart-f893fe1a-f342-49a3-add4-420a0924c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793846455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1793846455
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1998700563
Short name T129
Test name
Test status
Simulation time 425996325347 ps
CPU time 540.44 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 202372 kb
Host smart-e4326ea6-b59d-4ba1-a810-997c7c95f63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998700563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1998700563
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1284775487
Short name T318
Test name
Test status
Simulation time 164822180085 ps
CPU time 57.87 seconds
Started Aug 18 05:43:38 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 202064 kb
Host smart-b823c3dc-1a1a-40f5-a788-ec9467d94c31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284775487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1284775487
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2741315532
Short name T295
Test name
Test status
Simulation time 491542443008 ps
CPU time 296.41 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 202096 kb
Host smart-3b3fa720-e410-4f69-a90b-58bee6ba79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741315532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2741315532
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1786947540
Short name T190
Test name
Test status
Simulation time 103476461214 ps
CPU time 392.27 seconds
Started Aug 18 05:44:28 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 202352 kb
Host smart-04517bd0-0514-452e-b3d8-57f0dac238f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786947540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1786947540
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2449994528
Short name T264
Test name
Test status
Simulation time 4551368788 ps
CPU time 6.59 seconds
Started Aug 18 05:44:45 PM PDT 24
Finished Aug 18 05:44:52 PM PDT 24
Peak memory 202268 kb
Host smart-fcdf31e5-0b85-42e9-8524-0a5a15ff7089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449994528 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2449994528
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3156278812
Short name T16
Test name
Test status
Simulation time 3777669930 ps
CPU time 5.52 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:42:41 PM PDT 24
Peak memory 210420 kb
Host smart-a2da3e42-c670-4626-bb69-33e29e1e3195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156278812 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3156278812
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3654876916
Short name T306
Test name
Test status
Simulation time 161284544300 ps
CPU time 195.33 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:46:03 PM PDT 24
Peak memory 202168 kb
Host smart-dcf2ea4c-bf61-4cc6-b027-86ceb1e3e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654876916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3654876916
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.462428591
Short name T311
Test name
Test status
Simulation time 491383253250 ps
CPU time 146.77 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:45:15 PM PDT 24
Peak memory 202156 kb
Host smart-4d7ce1b0-6651-4e38-9fb7-854ef7534b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462428591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.462428591
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2174133681
Short name T296
Test name
Test status
Simulation time 173120319350 ps
CPU time 96.34 seconds
Started Aug 18 05:42:40 PM PDT 24
Finished Aug 18 05:44:16 PM PDT 24
Peak memory 202040 kb
Host smart-180beb40-591c-48ef-b2ed-4b176e5cf12a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174133681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2174133681
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1494012547
Short name T220
Test name
Test status
Simulation time 518791400972 ps
CPU time 1091.3 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 06:01:15 PM PDT 24
Peak memory 202140 kb
Host smart-a760e59a-e50f-46d1-a355-c206b10ad6f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494012547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1494012547
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3104974938
Short name T182
Test name
Test status
Simulation time 270036804972 ps
CPU time 951.57 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:58:44 PM PDT 24
Peak memory 212356 kb
Host smart-0b262b65-8422-4995-8d63-22c77bfe75ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104974938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3104974938
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2153435573
Short name T199
Test name
Test status
Simulation time 492978764771 ps
CPU time 203.95 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:46:21 PM PDT 24
Peak memory 202104 kb
Host smart-579cf2fe-4e54-4d4b-a96d-77d461af4daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153435573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2153435573
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3060880251
Short name T213
Test name
Test status
Simulation time 413541595045 ps
CPU time 214.42 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 202112 kb
Host smart-234e7e8d-3f14-4e85-8965-34cce9514335
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060880251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3060880251
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1184184389
Short name T193
Test name
Test status
Simulation time 76083691982 ps
CPU time 257.04 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:47:09 PM PDT 24
Peak memory 218200 kb
Host smart-e222404e-4993-4bd9-9f3a-5c56775cd4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184184389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1184184389
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4156196365
Short name T266
Test name
Test status
Simulation time 323969098139 ps
CPU time 692.93 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:54:52 PM PDT 24
Peak memory 202296 kb
Host smart-fe95bd0a-3053-4636-8170-d1f5c4208471
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156196365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4156196365
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2348630527
Short name T340
Test name
Test status
Simulation time 64596096057 ps
CPU time 377.04 seconds
Started Aug 18 05:42:32 PM PDT 24
Finished Aug 18 05:48:49 PM PDT 24
Peak memory 202332 kb
Host smart-7319b550-ab2a-4118-b0fe-ce380dd870ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348630527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2348630527
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3178688276
Short name T249
Test name
Test status
Simulation time 185736975859 ps
CPU time 218.85 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 202108 kb
Host smart-2f9890c6-9d58-4bb3-b9b4-f87234ee57e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178688276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3178688276
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2099553506
Short name T299
Test name
Test status
Simulation time 6966852768 ps
CPU time 13.92 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 210660 kb
Host smart-15aa2219-82da-432f-9086-f1e86cc661d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099553506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2099553506
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4131854415
Short name T268
Test name
Test status
Simulation time 323623720574 ps
CPU time 755.75 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:56:10 PM PDT 24
Peak memory 202104 kb
Host smart-7d1d3ce9-de3a-4032-9543-a72a82d13ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131854415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4131854415
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2152059271
Short name T338
Test name
Test status
Simulation time 94963347650 ps
CPU time 530.82 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 202536 kb
Host smart-ec5613f9-71c6-4dc2-9c72-8cef0d417267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152059271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2152059271
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.449125752
Short name T203
Test name
Test status
Simulation time 550919243714 ps
CPU time 1290.01 seconds
Started Aug 18 05:44:26 PM PDT 24
Finished Aug 18 06:05:56 PM PDT 24
Peak memory 202012 kb
Host smart-f9617d75-e665-4f37-bde9-9914e0b5e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449125752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.449125752
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.95393564
Short name T189
Test name
Test status
Simulation time 141444694739 ps
CPU time 703.77 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:56:17 PM PDT 24
Peak memory 202416 kb
Host smart-f8958e99-b991-4b97-8020-5ad4434a760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95393564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.95393564
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3635641894
Short name T104
Test name
Test status
Simulation time 846210256 ps
CPU time 2.35 seconds
Started Aug 18 05:42:04 PM PDT 24
Finished Aug 18 05:42:07 PM PDT 24
Peak memory 201096 kb
Host smart-778dbf00-fd3d-4400-a9ec-7dc0a9f31ef2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635641894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3635641894
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4222855290
Short name T105
Test name
Test status
Simulation time 40164976375 ps
CPU time 28.16 seconds
Started Aug 18 05:41:50 PM PDT 24
Finished Aug 18 05:42:18 PM PDT 24
Peak memory 201140 kb
Host smart-572c5be3-6e39-47d1-acfe-dd0c424d50cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222855290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4222855290
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3635765650
Short name T887
Test name
Test status
Simulation time 1390457014 ps
CPU time 1.12 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 200920 kb
Host smart-6ead554b-73fd-4e03-b817-da5f7eb0cfb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635765650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3635765650
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.258059536
Short name T94
Test name
Test status
Simulation time 435815579 ps
CPU time 1.96 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 200976 kb
Host smart-c077a9de-70f9-49e8-96f1-45facd210a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258059536 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.258059536
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1710468723
Short name T823
Test name
Test status
Simulation time 393240798 ps
CPU time 1.04 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200900 kb
Host smart-9c973d73-a02b-4e7f-b75c-18ee03005f84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710468723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1710468723
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1263677983
Short name T914
Test name
Test status
Simulation time 377777993 ps
CPU time 1.55 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 200848 kb
Host smart-187b0f8c-44e8-4496-8583-02350222b491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263677983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1263677983
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2258455968
Short name T111
Test name
Test status
Simulation time 2707827264 ps
CPU time 4.76 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 200868 kb
Host smart-9aeb6817-e6ce-4878-8c91-1c85b666e3dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258455968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2258455968
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1387018047
Short name T67
Test name
Test status
Simulation time 314526274 ps
CPU time 1.98 seconds
Started Aug 18 05:41:51 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 201144 kb
Host smart-9b89217c-a662-4517-9069-8d2a201b60cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387018047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1387018047
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4256737341
Short name T877
Test name
Test status
Simulation time 815110710 ps
CPU time 3.24 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 201048 kb
Host smart-d7ed0237-6896-40fb-800d-cb94c9141650
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256737341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4256737341
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2377336915
Short name T913
Test name
Test status
Simulation time 14388327301 ps
CPU time 19.08 seconds
Started Aug 18 05:42:02 PM PDT 24
Finished Aug 18 05:42:22 PM PDT 24
Peak memory 201172 kb
Host smart-92207654-c32e-4942-8169-d0e219e4ea2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377336915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2377336915
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.980870316
Short name T108
Test name
Test status
Simulation time 938277781 ps
CPU time 1.24 seconds
Started Aug 18 05:42:10 PM PDT 24
Finished Aug 18 05:42:12 PM PDT 24
Peak memory 200900 kb
Host smart-b7b22519-65a4-43f9-8e9e-103276357792
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980870316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.980870316
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2378142218
Short name T899
Test name
Test status
Simulation time 633736531 ps
CPU time 1.12 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200988 kb
Host smart-d335184b-aa33-4bb9-bf1b-8d8e068209ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378142218 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2378142218
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1134426670
Short name T112
Test name
Test status
Simulation time 351936165 ps
CPU time 1.06 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200924 kb
Host smart-aae55725-33a7-4ad6-98c4-56b3b9b51045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134426670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1134426670
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2597430380
Short name T814
Test name
Test status
Simulation time 311774827 ps
CPU time 1.27 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200848 kb
Host smart-4bddfaac-9797-4730-a72e-1d618b71a4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597430380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2597430380
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2014559973
Short name T875
Test name
Test status
Simulation time 4245316364 ps
CPU time 5.26 seconds
Started Aug 18 05:41:45 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 201164 kb
Host smart-ec935b6f-a778-4575-b879-62f313dc4c3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014559973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2014559973
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2201844213
Short name T852
Test name
Test status
Simulation time 8207223643 ps
CPU time 20.32 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:42:03 PM PDT 24
Peak memory 201176 kb
Host smart-82382143-c6b4-4e7b-97a6-86d2fdc961b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201844213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2201844213
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.115828403
Short name T829
Test name
Test status
Simulation time 560767011 ps
CPU time 1.29 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200988 kb
Host smart-008d3d29-dfe8-4079-b736-81ee445ea2d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115828403 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.115828403
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2565943555
Short name T841
Test name
Test status
Simulation time 565269752 ps
CPU time 0.88 seconds
Started Aug 18 05:42:03 PM PDT 24
Finished Aug 18 05:42:04 PM PDT 24
Peak memory 200852 kb
Host smart-b8275872-d022-43ee-ab9f-34da086ef2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565943555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2565943555
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.976950254
Short name T53
Test name
Test status
Simulation time 1901556460 ps
CPU time 5.11 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200896 kb
Host smart-b5f3d3bb-ec65-48a1-a331-d6f9eef2c29f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976950254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.976950254
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3909191091
Short name T75
Test name
Test status
Simulation time 688540337 ps
CPU time 1.3 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 201100 kb
Host smart-f194f4c1-c6c3-4da6-9ff6-a912279d7867
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909191091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3909191091
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1636254957
Short name T858
Test name
Test status
Simulation time 4726141851 ps
CPU time 4.09 seconds
Started Aug 18 05:42:14 PM PDT 24
Finished Aug 18 05:42:18 PM PDT 24
Peak memory 201176 kb
Host smart-7b5665b9-a23a-4070-85e1-98b6c9f67efa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636254957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1636254957
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3293738228
Short name T868
Test name
Test status
Simulation time 465053641 ps
CPU time 1.55 seconds
Started Aug 18 05:42:16 PM PDT 24
Finished Aug 18 05:42:18 PM PDT 24
Peak memory 210652 kb
Host smart-893366c2-a454-46aa-9b60-828b986480fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293738228 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3293738228
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1089006882
Short name T818
Test name
Test status
Simulation time 548413721 ps
CPU time 2.04 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 200848 kb
Host smart-158ef7d4-e219-4c10-accc-f14e650b5bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089006882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1089006882
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.635970838
Short name T919
Test name
Test status
Simulation time 352633454 ps
CPU time 0.85 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200844 kb
Host smart-4fe22ddb-6c82-4d2a-bc1d-bbc2069203f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635970838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.635970838
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1229306206
Short name T827
Test name
Test status
Simulation time 2843290464 ps
CPU time 1.36 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200980 kb
Host smart-f6cb199d-97f6-49cb-901a-997d1dcee72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229306206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1229306206
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3208513720
Short name T878
Test name
Test status
Simulation time 362752506 ps
CPU time 2.14 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 201080 kb
Host smart-30e216b2-4a21-4592-9409-9e7d516fcd74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208513720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3208513720
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3579035754
Short name T332
Test name
Test status
Simulation time 4332407245 ps
CPU time 6.38 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:42:04 PM PDT 24
Peak memory 201168 kb
Host smart-e7b66b10-be0c-4e19-9120-f75d19fd64a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579035754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3579035754
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1057064046
Short name T78
Test name
Test status
Simulation time 407034290 ps
CPU time 1.01 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200964 kb
Host smart-d4064146-b1d1-4168-8328-b6e55c95127a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057064046 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1057064046
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1267708745
Short name T107
Test name
Test status
Simulation time 467095310 ps
CPU time 1.87 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 200952 kb
Host smart-d2d9b41e-454e-4278-9e5f-73d041b6ce5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267708745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1267708745
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.207047775
Short name T828
Test name
Test status
Simulation time 439626142 ps
CPU time 0.81 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200740 kb
Host smart-d63efc6d-b4b8-4968-b68e-91aa7fcb475b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207047775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.207047775
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3918168290
Short name T895
Test name
Test status
Simulation time 2488129052 ps
CPU time 8.63 seconds
Started Aug 18 05:42:00 PM PDT 24
Finished Aug 18 05:42:08 PM PDT 24
Peak memory 200932 kb
Host smart-fb97acf8-de6d-470c-a897-773988f9acc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918168290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3918168290
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3020372171
Short name T907
Test name
Test status
Simulation time 531685290 ps
CPU time 2.62 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 201136 kb
Host smart-9e0c9d32-edd8-4afc-837f-897169499f20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020372171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3020372171
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1029806994
Short name T909
Test name
Test status
Simulation time 4518009042 ps
CPU time 3.73 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:47 PM PDT 24
Peak memory 201040 kb
Host smart-a95a8aaf-9daf-4c6a-b11b-171e0c4b6d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029806994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1029806994
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3951087050
Short name T73
Test name
Test status
Simulation time 412094815 ps
CPU time 1.34 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 209388 kb
Host smart-53281212-602d-4986-be6b-360be99272cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951087050 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3951087050
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3770517117
Short name T900
Test name
Test status
Simulation time 442441472 ps
CPU time 1.01 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200908 kb
Host smart-7929cef6-789f-4bef-848f-fd941b933ab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770517117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3770517117
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2172215525
Short name T816
Test name
Test status
Simulation time 425048117 ps
CPU time 1.07 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 199752 kb
Host smart-2f896f05-60a1-4247-bfa8-6bed96ef40fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172215525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2172215525
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2980418125
Short name T876
Test name
Test status
Simulation time 1872023779 ps
CPU time 2.87 seconds
Started Aug 18 05:42:00 PM PDT 24
Finished Aug 18 05:42:03 PM PDT 24
Peak memory 200792 kb
Host smart-4cc8244a-ec4c-4007-861a-84ddcd915bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980418125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2980418125
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.858605985
Short name T68
Test name
Test status
Simulation time 531113652 ps
CPU time 2.17 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200876 kb
Host smart-368c8632-c509-449d-acc1-d0c1fa1258f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858605985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.858605985
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4003856066
Short name T911
Test name
Test status
Simulation time 8159391464 ps
CPU time 20.66 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 201148 kb
Host smart-ebb223aa-a6e4-4010-a4d9-90f144806201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003856066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4003856066
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3393618567
Short name T873
Test name
Test status
Simulation time 388443557 ps
CPU time 1.67 seconds
Started Aug 18 05:42:00 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 201192 kb
Host smart-5dfcf3d6-0a1f-4e49-b2ab-54b5321d7deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393618567 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3393618567
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.86893004
Short name T888
Test name
Test status
Simulation time 517791952 ps
CPU time 1.88 seconds
Started Aug 18 05:42:17 PM PDT 24
Finished Aug 18 05:42:19 PM PDT 24
Peak memory 200896 kb
Host smart-f8203ff2-ac19-4d2e-a61b-6097ab73b4c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86893004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.86893004
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2281936747
Short name T809
Test name
Test status
Simulation time 496064174 ps
CPU time 1.77 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 200772 kb
Host smart-508bb846-7e40-42b7-a239-1a2ac7bb8559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281936747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2281936747
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.725185821
Short name T853
Test name
Test status
Simulation time 4856451402 ps
CPU time 5.61 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:41:52 PM PDT 24
Peak memory 201148 kb
Host smart-b2fbb733-7146-4c57-ae45-057c0380cd9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725185821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.725185821
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1446761833
Short name T77
Test name
Test status
Simulation time 2400895455 ps
CPU time 2.69 seconds
Started Aug 18 05:42:27 PM PDT 24
Finished Aug 18 05:42:29 PM PDT 24
Peak memory 217240 kb
Host smart-7ee9c881-23e2-410a-bef9-7aceadc6f954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446761833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1446761833
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2635321137
Short name T79
Test name
Test status
Simulation time 366107017 ps
CPU time 1.72 seconds
Started Aug 18 05:42:22 PM PDT 24
Finished Aug 18 05:42:24 PM PDT 24
Peak memory 201000 kb
Host smart-7d3d206d-dec9-4170-b204-08858ef71c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635321137 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2635321137
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1374195649
Short name T881
Test name
Test status
Simulation time 609727538 ps
CPU time 1.17 seconds
Started Aug 18 05:42:07 PM PDT 24
Finished Aug 18 05:42:08 PM PDT 24
Peak memory 200920 kb
Host smart-5e715c2d-9d98-4365-9ebe-2f1fe6745f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374195649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1374195649
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3937627849
Short name T807
Test name
Test status
Simulation time 520096682 ps
CPU time 0.92 seconds
Started Aug 18 05:42:19 PM PDT 24
Finished Aug 18 05:42:20 PM PDT 24
Peak memory 200784 kb
Host smart-81a28b91-704e-4848-8700-45f4c47ed5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937627849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3937627849
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1970554610
Short name T110
Test name
Test status
Simulation time 4431943237 ps
CPU time 6.83 seconds
Started Aug 18 05:42:07 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 201112 kb
Host smart-7950b097-002a-46fe-9189-728bdc93ea5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970554610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1970554610
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1089670521
Short name T861
Test name
Test status
Simulation time 584390030 ps
CPU time 1.83 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 201172 kb
Host smart-6d638554-0811-4b67-a1f5-3bb2457d896c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089670521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1089670521
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2316096318
Short name T834
Test name
Test status
Simulation time 4353624549 ps
CPU time 12.15 seconds
Started Aug 18 05:42:11 PM PDT 24
Finished Aug 18 05:42:23 PM PDT 24
Peak memory 201108 kb
Host smart-2acb154c-c9fb-4bda-b8a7-155f89a473d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316096318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2316096318
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2769122648
Short name T812
Test name
Test status
Simulation time 460992487 ps
CPU time 1.3 seconds
Started Aug 18 05:42:02 PM PDT 24
Finished Aug 18 05:42:04 PM PDT 24
Peak memory 200992 kb
Host smart-ad981f9b-c84f-48ef-bb58-039850515d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769122648 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2769122648
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1257986693
Short name T101
Test name
Test status
Simulation time 415622436 ps
CPU time 1.67 seconds
Started Aug 18 05:42:07 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 200912 kb
Host smart-e7d3a756-a039-4812-bd56-40842340f943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257986693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1257986693
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4169131562
Short name T889
Test name
Test status
Simulation time 443051812 ps
CPU time 1.22 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200760 kb
Host smart-0c18d98b-ad57-4aa7-ab92-13fb47f1d8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169131562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4169131562
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.970799736
Short name T831
Test name
Test status
Simulation time 2202920045 ps
CPU time 3.17 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 200928 kb
Host smart-8729c658-d779-40d7-a2fa-5fac5a52bba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970799736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.970799736
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2199691643
Short name T65
Test name
Test status
Simulation time 496459718 ps
CPU time 2.36 seconds
Started Aug 18 05:42:03 PM PDT 24
Finished Aug 18 05:42:05 PM PDT 24
Peak memory 217356 kb
Host smart-4984b0e5-7f90-4540-8b72-93fe91cfc531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199691643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2199691643
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1768345377
Short name T898
Test name
Test status
Simulation time 5270986943 ps
CPU time 2.85 seconds
Started Aug 18 05:42:26 PM PDT 24
Finished Aug 18 05:42:29 PM PDT 24
Peak memory 201144 kb
Host smart-01d9c31c-fc80-4626-bd58-1bdbe502e6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768345377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1768345377
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.967478748
Short name T904
Test name
Test status
Simulation time 617222261 ps
CPU time 1.05 seconds
Started Aug 18 05:42:01 PM PDT 24
Finished Aug 18 05:42:02 PM PDT 24
Peak memory 200924 kb
Host smart-5a367e5e-9a35-4f5a-aac5-2b5410201c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967478748 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.967478748
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4174725635
Short name T896
Test name
Test status
Simulation time 538154112 ps
CPU time 1 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200900 kb
Host smart-cb00907e-9dbb-4b68-b6b2-a1ccc4a266ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174725635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4174725635
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3005516444
Short name T815
Test name
Test status
Simulation time 505332058 ps
CPU time 1.72 seconds
Started Aug 18 05:42:11 PM PDT 24
Finished Aug 18 05:42:13 PM PDT 24
Peak memory 200796 kb
Host smart-67b40f25-6e91-49bd-8385-96b0766cc750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005516444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3005516444
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1614619779
Short name T890
Test name
Test status
Simulation time 5418845286 ps
CPU time 5.4 seconds
Started Aug 18 05:42:19 PM PDT 24
Finished Aug 18 05:42:24 PM PDT 24
Peak memory 201064 kb
Host smart-3e97747d-4cde-4441-b8cc-65e987a2af7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614619779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1614619779
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2731595078
Short name T872
Test name
Test status
Simulation time 413988018 ps
CPU time 3.34 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:57 PM PDT 24
Peak memory 201152 kb
Host smart-7a183bab-55b4-4627-9eaa-133f2c638330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731595078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2731595078
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.808495373
Short name T333
Test name
Test status
Simulation time 8298816321 ps
CPU time 7.06 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 201136 kb
Host smart-d299606b-8486-4bdb-961b-489016e7ab13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808495373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.808495373
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3644621683
Short name T906
Test name
Test status
Simulation time 542592525 ps
CPU time 1.34 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 200984 kb
Host smart-aec3dfb5-75b4-47bf-abf6-515730528a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644621683 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3644621683
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1858283332
Short name T824
Test name
Test status
Simulation time 530040003 ps
CPU time 1.03 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200924 kb
Host smart-8e53f792-2dd0-4c58-8a9a-87974e0a3b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858283332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1858283332
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2115955506
Short name T866
Test name
Test status
Simulation time 307139633 ps
CPU time 0.98 seconds
Started Aug 18 05:42:14 PM PDT 24
Finished Aug 18 05:42:15 PM PDT 24
Peak memory 200848 kb
Host smart-0874bc6d-6160-49ea-b9f4-bdcfefe82481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115955506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2115955506
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.559955870
Short name T882
Test name
Test status
Simulation time 4673817236 ps
CPU time 4.9 seconds
Started Aug 18 05:42:00 PM PDT 24
Finished Aug 18 05:42:05 PM PDT 24
Peak memory 201124 kb
Host smart-2f264ce8-b78a-4781-95d2-7ac84553c610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559955870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.559955870
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2774841579
Short name T860
Test name
Test status
Simulation time 8156047964 ps
CPU time 14.96 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 201160 kb
Host smart-b8deea2b-4812-4f21-8202-456a20783a77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774841579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2774841579
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.657627480
Short name T826
Test name
Test status
Simulation time 432664629 ps
CPU time 1.89 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 200932 kb
Host smart-36c40d1a-0acb-4d4b-a076-2deb2671f476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657627480 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.657627480
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2743648603
Short name T871
Test name
Test status
Simulation time 474642750 ps
CPU time 0.83 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 200908 kb
Host smart-e54e28eb-c057-4cb8-9c65-0fac01d1825d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743648603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2743648603
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2958182050
Short name T830
Test name
Test status
Simulation time 340259609 ps
CPU time 1.43 seconds
Started Aug 18 05:42:09 PM PDT 24
Finished Aug 18 05:42:11 PM PDT 24
Peak memory 200844 kb
Host smart-1b42e5f2-9a29-488f-b7b4-faf6669ba523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958182050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2958182050
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3242893392
Short name T50
Test name
Test status
Simulation time 4283425823 ps
CPU time 9.77 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:42:07 PM PDT 24
Peak memory 201104 kb
Host smart-c0f623b2-095c-4570-a616-f7e95c7af3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242893392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3242893392
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2510452851
Short name T864
Test name
Test status
Simulation time 593988540 ps
CPU time 1.89 seconds
Started Aug 18 05:42:32 PM PDT 24
Finished Aug 18 05:42:34 PM PDT 24
Peak memory 209372 kb
Host smart-20d07089-e4c0-4a86-91d0-8d20352660f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510452851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2510452851
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1336435147
Short name T66
Test name
Test status
Simulation time 9052669577 ps
CPU time 4.33 seconds
Started Aug 18 05:41:56 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 201160 kb
Host smart-7bdfd980-1729-437e-b37c-b5382d86303d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336435147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1336435147
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.821280407
Short name T106
Test name
Test status
Simulation time 1062338169 ps
CPU time 3.39 seconds
Started Aug 18 05:42:21 PM PDT 24
Finished Aug 18 05:42:30 PM PDT 24
Peak memory 201048 kb
Host smart-df0dcbb4-aae1-4ef1-96e3-cb464a288d95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821280407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.821280407
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2936482074
Short name T874
Test name
Test status
Simulation time 52904161886 ps
CPU time 123.57 seconds
Started Aug 18 05:42:13 PM PDT 24
Finished Aug 18 05:44:17 PM PDT 24
Peak memory 201132 kb
Host smart-322466bc-5114-496d-9a9e-59f8d6a35f69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936482074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2936482074
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.241041035
Short name T851
Test name
Test status
Simulation time 1383896691 ps
CPU time 1.59 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 200924 kb
Host smart-16abb9c6-c34a-48b9-9953-348e0e44d047
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241041035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.241041035
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.896024188
Short name T817
Test name
Test status
Simulation time 518477279 ps
CPU time 2.06 seconds
Started Aug 18 05:42:15 PM PDT 24
Finished Aug 18 05:42:18 PM PDT 24
Peak memory 200988 kb
Host smart-51a36674-6aad-4230-b0a9-50abfbf2a53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896024188 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.896024188
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4102934078
Short name T847
Test name
Test status
Simulation time 540655351 ps
CPU time 1.95 seconds
Started Aug 18 05:42:04 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 200900 kb
Host smart-9cb5d811-0b27-449e-8ae9-0993494f939b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102934078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4102934078
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.581536645
Short name T810
Test name
Test status
Simulation time 310857962 ps
CPU time 0.78 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200832 kb
Host smart-1bc85436-97e5-4183-92e6-c80469d59abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581536645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.581536645
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1987393782
Short name T910
Test name
Test status
Simulation time 4915774024 ps
CPU time 19.38 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 201112 kb
Host smart-3de9440f-085d-4c10-99d4-1e63431508f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987393782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1987393782
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2800770459
Short name T72
Test name
Test status
Simulation time 438848727 ps
CPU time 2.23 seconds
Started Aug 18 05:41:50 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 201124 kb
Host smart-0c5716a9-a73c-4bfb-a9b6-381be1fc0dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800770459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2800770459
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2248486272
Short name T849
Test name
Test status
Simulation time 4563916777 ps
CPU time 12.86 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:42:05 PM PDT 24
Peak memory 201176 kb
Host smart-542d0fb1-2983-4703-90ed-e0fa1915f927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248486272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2248486272
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.83455944
Short name T855
Test name
Test status
Simulation time 482672956 ps
CPU time 0.68 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:13 PM PDT 24
Peak memory 200864 kb
Host smart-97683829-07ae-4bbd-80e2-2555acde0d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83455944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.83455944
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4216318034
Short name T843
Test name
Test status
Simulation time 536771767 ps
CPU time 1.15 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200712 kb
Host smart-7bd2facc-7c3d-42d4-bac3-ea23941c72ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216318034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4216318034
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.838364243
Short name T905
Test name
Test status
Simulation time 396911547 ps
CPU time 0.84 seconds
Started Aug 18 05:42:10 PM PDT 24
Finished Aug 18 05:42:11 PM PDT 24
Peak memory 200756 kb
Host smart-ec2922bf-b173-4269-928a-4d6caee473e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838364243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.838364243
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.222684839
Short name T850
Test name
Test status
Simulation time 446903357 ps
CPU time 0.85 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 200788 kb
Host smart-a1e28e80-98ed-4fa4-97f4-bd944859c2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222684839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.222684839
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2730247689
Short name T894
Test name
Test status
Simulation time 392362789 ps
CPU time 1.42 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 201076 kb
Host smart-90e8a39f-eb42-452e-90cd-b7d8655d0305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730247689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2730247689
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1546583170
Short name T811
Test name
Test status
Simulation time 545812264 ps
CPU time 0.91 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200840 kb
Host smart-5018053d-b57f-468d-aee9-6775a2d5786e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546583170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1546583170
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4018189027
Short name T867
Test name
Test status
Simulation time 433163478 ps
CPU time 0.87 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200788 kb
Host smart-a7c6dd81-cb88-4e0b-896d-0dcfd07b4c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018189027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4018189027
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3244270938
Short name T820
Test name
Test status
Simulation time 324412373 ps
CPU time 1 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200828 kb
Host smart-b02d7eaf-70f8-4590-9a59-19964e60b2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244270938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3244270938
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2254925953
Short name T915
Test name
Test status
Simulation time 431901052 ps
CPU time 1.12 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200712 kb
Host smart-929c3f62-11d9-449e-8cfb-bfbcc81f611d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254925953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2254925953
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3285294084
Short name T800
Test name
Test status
Simulation time 305043404 ps
CPU time 1.24 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 200804 kb
Host smart-127e2c14-b4df-4693-88a7-10ef27e00792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285294084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3285294084
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.60620668
Short name T114
Test name
Test status
Simulation time 708045016 ps
CPU time 1.87 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 201008 kb
Host smart-8476ce81-2fba-4459-9f41-64713f41fa5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60620668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasi
ng.60620668
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1873386576
Short name T839
Test name
Test status
Simulation time 26921439613 ps
CPU time 25.56 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:42:15 PM PDT 24
Peak memory 201104 kb
Host smart-cc6c70a5-8d8f-4d1c-9c5e-560fbaa5aaeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873386576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1873386576
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.194389764
Short name T897
Test name
Test status
Simulation time 1258703040 ps
CPU time 1.17 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 200900 kb
Host smart-09f20510-35f0-483a-b223-c752529f1232
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194389764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.194389764
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2673366258
Short name T74
Test name
Test status
Simulation time 384266757 ps
CPU time 1.66 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 200992 kb
Host smart-3122a02d-4fa6-4608-9add-f029965f4886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673366258 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2673366258
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4182220026
Short name T102
Test name
Test status
Simulation time 522288455 ps
CPU time 1.13 seconds
Started Aug 18 05:41:50 PM PDT 24
Finished Aug 18 05:41:52 PM PDT 24
Peak memory 200928 kb
Host smart-20180453-96e5-4e89-8569-aa4ec172b903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182220026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4182220026
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.643475944
Short name T845
Test name
Test status
Simulation time 483033661 ps
CPU time 1.63 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:41:57 PM PDT 24
Peak memory 200824 kb
Host smart-cc77b5ac-0db2-429f-b0da-c518a406aa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643475944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.643475944
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2622893317
Short name T846
Test name
Test status
Simulation time 4321202174 ps
CPU time 16.35 seconds
Started Aug 18 05:42:21 PM PDT 24
Finished Aug 18 05:42:37 PM PDT 24
Peak memory 201136 kb
Host smart-8b851451-41c4-4595-b63a-a06d640ea7c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622893317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2622893317
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3818939474
Short name T880
Test name
Test status
Simulation time 614132952 ps
CPU time 2.1 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 201144 kb
Host smart-ff22b9db-2d50-4d86-86f5-b504d3fd7099
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818939474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3818939474
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4150669246
Short name T892
Test name
Test status
Simulation time 4520857168 ps
CPU time 12.05 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 201160 kb
Host smart-29dece20-8428-40ce-beab-74e29355bedd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150669246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4150669246
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.117094933
Short name T854
Test name
Test status
Simulation time 476783189 ps
CPU time 1.01 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 200808 kb
Host smart-77018362-b38f-49db-83ef-00bc9a94088f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117094933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.117094933
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4017614678
Short name T842
Test name
Test status
Simulation time 520110470 ps
CPU time 1.87 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200828 kb
Host smart-7f79b4da-2baf-4f96-8951-dda1d236868f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017614678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4017614678
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2977420748
Short name T813
Test name
Test status
Simulation time 538373664 ps
CPU time 0.98 seconds
Started Aug 18 05:42:09 PM PDT 24
Finished Aug 18 05:42:10 PM PDT 24
Peak memory 201080 kb
Host smart-b21e93c7-143f-4a5d-a461-6325a5351f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977420748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2977420748
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3954873771
Short name T844
Test name
Test status
Simulation time 512682860 ps
CPU time 1.92 seconds
Started Aug 18 05:42:17 PM PDT 24
Finished Aug 18 05:42:19 PM PDT 24
Peak memory 200844 kb
Host smart-de6d3856-db1a-47ec-ac07-3b89601f196b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954873771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3954873771
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2788170689
Short name T856
Test name
Test status
Simulation time 534082849 ps
CPU time 0.93 seconds
Started Aug 18 05:42:21 PM PDT 24
Finished Aug 18 05:42:22 PM PDT 24
Peak memory 200804 kb
Host smart-015ea3df-272c-45d7-80df-a6755435a70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788170689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2788170689
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3341173781
Short name T908
Test name
Test status
Simulation time 516626990 ps
CPU time 0.87 seconds
Started Aug 18 05:42:30 PM PDT 24
Finished Aug 18 05:42:31 PM PDT 24
Peak memory 200788 kb
Host smart-6d749199-0cad-4cdc-a096-c10124746641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341173781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3341173781
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1890332151
Short name T912
Test name
Test status
Simulation time 351408033 ps
CPU time 0.85 seconds
Started Aug 18 05:42:23 PM PDT 24
Finished Aug 18 05:42:23 PM PDT 24
Peak memory 200760 kb
Host smart-0a6355d6-37de-470a-827d-936a7f2f550d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890332151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1890332151
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4215078136
Short name T802
Test name
Test status
Simulation time 436933324 ps
CPU time 1.16 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200852 kb
Host smart-3b4fad45-64e5-4bd6-b09d-6c367be61c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215078136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4215078136
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.342991607
Short name T801
Test name
Test status
Simulation time 536192752 ps
CPU time 0.84 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 200792 kb
Host smart-565a4cd5-50aa-4659-a7b8-48ed8748f7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342991607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.342991607
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2567676378
Short name T819
Test name
Test status
Simulation time 414159221 ps
CPU time 1.53 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 200820 kb
Host smart-b49ed740-8b9a-494e-ae23-35ea61614aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567676378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2567676378
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.69283553
Short name T103
Test name
Test status
Simulation time 534741319 ps
CPU time 2.72 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 201112 kb
Host smart-53fbdb59-08d2-4a4e-82f3-146cca5f14ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69283553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasi
ng.69283553
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2336502913
Short name T51
Test name
Test status
Simulation time 20383430771 ps
CPU time 42.39 seconds
Started Aug 18 05:42:11 PM PDT 24
Finished Aug 18 05:42:53 PM PDT 24
Peak memory 201108 kb
Host smart-c75fbd16-734f-4a74-a819-f066417cef07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336502913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2336502913
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3934247098
Short name T100
Test name
Test status
Simulation time 1455400116 ps
CPU time 1.07 seconds
Started Aug 18 05:41:51 PM PDT 24
Finished Aug 18 05:41:52 PM PDT 24
Peak memory 200884 kb
Host smart-895af4c6-8bdb-4994-ac4a-0dbfc6fe931f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934247098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3934247098
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3445936937
Short name T870
Test name
Test status
Simulation time 509095254 ps
CPU time 1.55 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 200940 kb
Host smart-3c1a7d44-edf9-4d30-96d3-191ea43bc5da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445936937 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3445936937
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3639686245
Short name T884
Test name
Test status
Simulation time 565656941 ps
CPU time 1.93 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 200884 kb
Host smart-bec691d4-71d7-4d4f-b2cb-e03781c64d70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639686245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3639686245
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3094725403
Short name T859
Test name
Test status
Simulation time 532213213 ps
CPU time 0.8 seconds
Started Aug 18 05:41:56 PM PDT 24
Finished Aug 18 05:41:57 PM PDT 24
Peak memory 200852 kb
Host smart-d29d4e2b-a897-4806-acb8-c2c0f3ddb207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094725403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3094725403
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.12270857
Short name T822
Test name
Test status
Simulation time 3961078664 ps
CPU time 3.21 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:16 PM PDT 24
Peak memory 201128 kb
Host smart-677f5bc2-d449-4016-9005-de1909b3bd5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctr
l_same_csr_outstanding.12270857
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4276815403
Short name T893
Test name
Test status
Simulation time 548678552 ps
CPU time 1.92 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 201168 kb
Host smart-3bceb0ed-cbf4-4286-94fc-088e64ffc664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276815403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.4276815403
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2654911041
Short name T59
Test name
Test status
Simulation time 4636985123 ps
CPU time 4.25 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 201176 kb
Host smart-ff8f0f2f-d196-43ef-8ade-ac33a78d7bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654911041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2654911041
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3980392081
Short name T837
Test name
Test status
Simulation time 441223631 ps
CPU time 1.16 seconds
Started Aug 18 05:42:11 PM PDT 24
Finished Aug 18 05:42:12 PM PDT 24
Peak memory 200852 kb
Host smart-eceeb370-1855-4579-b701-ba33d2537467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980392081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3980392081
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.686178175
Short name T825
Test name
Test status
Simulation time 367731800 ps
CPU time 0.8 seconds
Started Aug 18 05:41:55 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 200844 kb
Host smart-3d38b3c9-9922-4856-a29e-b2c68208782c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686178175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.686178175
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3287448798
Short name T836
Test name
Test status
Simulation time 566980434 ps
CPU time 0.76 seconds
Started Aug 18 05:42:15 PM PDT 24
Finished Aug 18 05:42:15 PM PDT 24
Peak memory 200800 kb
Host smart-e69b795f-aebe-4cbe-b51f-b3d143c058ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287448798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3287448798
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4242971857
Short name T838
Test name
Test status
Simulation time 405224445 ps
CPU time 1.06 seconds
Started Aug 18 05:42:15 PM PDT 24
Finished Aug 18 05:42:16 PM PDT 24
Peak memory 200852 kb
Host smart-91b9146e-d148-4047-8c81-535300cd7cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242971857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4242971857
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3575120488
Short name T917
Test name
Test status
Simulation time 384332564 ps
CPU time 0.83 seconds
Started Aug 18 05:42:05 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 200836 kb
Host smart-b1d4c6f3-b34e-4e68-833e-d9af4c1ef7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575120488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3575120488
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.962384696
Short name T869
Test name
Test status
Simulation time 425099884 ps
CPU time 0.83 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 200832 kb
Host smart-09c37bbc-c593-46de-a9f9-5b963a493118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962384696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.962384696
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.326604907
Short name T804
Test name
Test status
Simulation time 509952402 ps
CPU time 0.68 seconds
Started Aug 18 05:42:06 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 200776 kb
Host smart-0aca9bb8-9f93-4c07-8e07-df66d1b171b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326604907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.326604907
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2221134366
Short name T886
Test name
Test status
Simulation time 559723119 ps
CPU time 0.98 seconds
Started Aug 18 05:42:28 PM PDT 24
Finished Aug 18 05:42:29 PM PDT 24
Peak memory 200844 kb
Host smart-6a34c804-c019-4d4a-b973-4fefa14a9a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221134366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2221134366
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3581718968
Short name T808
Test name
Test status
Simulation time 301928019 ps
CPU time 0.89 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 200804 kb
Host smart-94324886-5e45-411c-808a-274ac41e38e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581718968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3581718968
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2938470772
Short name T805
Test name
Test status
Simulation time 540270966 ps
CPU time 1 seconds
Started Aug 18 05:42:24 PM PDT 24
Finished Aug 18 05:42:25 PM PDT 24
Peak memory 200820 kb
Host smart-69d0d0fc-e680-4efa-9a1d-5b95714fc3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938470772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2938470772
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.13296957
Short name T883
Test name
Test status
Simulation time 621758414 ps
CPU time 1.69 seconds
Started Aug 18 05:42:15 PM PDT 24
Finished Aug 18 05:42:17 PM PDT 24
Peak memory 201004 kb
Host smart-8fa7ab25-c7c0-41cd-9302-e5f89fcb72c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13296957 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.13296957
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1893253715
Short name T113
Test name
Test status
Simulation time 409376168 ps
CPU time 1.65 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 200896 kb
Host smart-02ed7678-175c-45ae-8014-5866e7ba91e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893253715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1893253715
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.363222974
Short name T848
Test name
Test status
Simulation time 385089011 ps
CPU time 0.69 seconds
Started Aug 18 05:42:01 PM PDT 24
Finished Aug 18 05:42:02 PM PDT 24
Peak memory 200784 kb
Host smart-2d370fbf-c5ac-4064-bc65-addff99a9a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363222974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.363222974
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.509192996
Short name T52
Test name
Test status
Simulation time 3621894862 ps
CPU time 2.33 seconds
Started Aug 18 05:42:04 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 201152 kb
Host smart-75f116f4-11ef-499c-b11b-ecc4e9c66b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509192996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.509192996
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3694220939
Short name T865
Test name
Test status
Simulation time 368564177 ps
CPU time 2.23 seconds
Started Aug 18 05:42:01 PM PDT 24
Finished Aug 18 05:42:03 PM PDT 24
Peak memory 201164 kb
Host smart-c7918c27-fc9f-41f0-bfd0-60c25d5c9886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694220939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3694220939
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3539158574
Short name T58
Test name
Test status
Simulation time 4272469600 ps
CPU time 6.25 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 201140 kb
Host smart-0e54655a-44ed-4bfb-82c3-a4e92ce6b512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539158574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3539158574
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1002967613
Short name T76
Test name
Test status
Simulation time 509080466 ps
CPU time 1.19 seconds
Started Aug 18 05:42:19 PM PDT 24
Finished Aug 18 05:42:20 PM PDT 24
Peak memory 200924 kb
Host smart-3604a0b6-6730-4b53-beab-a08218b2e4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002967613 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1002967613
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1105974557
Short name T109
Test name
Test status
Simulation time 468764515 ps
CPU time 1.78 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 201132 kb
Host smart-7d0b3dc5-16b0-48c3-ae64-4c7806119db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105974557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1105974557
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1676278016
Short name T806
Test name
Test status
Simulation time 371893264 ps
CPU time 0.81 seconds
Started Aug 18 05:42:16 PM PDT 24
Finished Aug 18 05:42:17 PM PDT 24
Peak memory 200780 kb
Host smart-ed570776-19d1-4c75-a62e-dba8bcc57311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676278016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1676278016
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.404484036
Short name T879
Test name
Test status
Simulation time 2256252544 ps
CPU time 3.13 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 200896 kb
Host smart-9a44ae48-9168-4ae6-9c0d-c1b0be9228af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404484036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.404484036
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2824032252
Short name T918
Test name
Test status
Simulation time 1111432194 ps
CPU time 3.5 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 201056 kb
Host smart-bcab371d-84b8-41bf-81f5-29e1dc279c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824032252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2824032252
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3964188187
Short name T903
Test name
Test status
Simulation time 9507932319 ps
CPU time 4.51 seconds
Started Aug 18 05:42:08 PM PDT 24
Finished Aug 18 05:42:13 PM PDT 24
Peak memory 201176 kb
Host smart-100471fc-5733-493f-b41d-56a4429a32f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964188187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3964188187
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.750929414
Short name T93
Test name
Test status
Simulation time 378224327 ps
CPU time 0.98 seconds
Started Aug 18 05:42:14 PM PDT 24
Finished Aug 18 05:42:15 PM PDT 24
Peak memory 200924 kb
Host smart-c4e58704-22a4-4a9c-b7ab-dc8c72d7153c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750929414 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.750929414
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4162306796
Short name T99
Test name
Test status
Simulation time 545924267 ps
CPU time 1.41 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 200908 kb
Host smart-4bda4010-e9b2-467b-a665-b747de3d8dea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162306796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4162306796
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1939993950
Short name T803
Test name
Test status
Simulation time 539572590 ps
CPU time 0.99 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200824 kb
Host smart-f848ea29-381c-4896-b3b3-21a7c87b080e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939993950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1939993950
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4234116395
Short name T821
Test name
Test status
Simulation time 2301659008 ps
CPU time 3.27 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:57 PM PDT 24
Peak memory 200984 kb
Host smart-370a4a07-23fa-4fac-b082-059b53250cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234116395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4234116395
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3023095479
Short name T901
Test name
Test status
Simulation time 459642053 ps
CPU time 2.42 seconds
Started Aug 18 05:42:05 PM PDT 24
Finished Aug 18 05:42:08 PM PDT 24
Peak memory 201180 kb
Host smart-fd7e0e30-fbce-41ac-a66d-1fb206814d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023095479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3023095479
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.254515800
Short name T835
Test name
Test status
Simulation time 4232599044 ps
CPU time 11.53 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 201148 kb
Host smart-f11cabbb-da90-4595-bd1a-100170c6c4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254515800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.254515800
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1162557358
Short name T902
Test name
Test status
Simulation time 539963605 ps
CPU time 1.1 seconds
Started Aug 18 05:41:50 PM PDT 24
Finished Aug 18 05:41:57 PM PDT 24
Peak memory 200996 kb
Host smart-ca6d8ec9-43ed-47b4-8627-d77f8889cfeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162557358 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1162557358
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.197896448
Short name T891
Test name
Test status
Simulation time 461838090 ps
CPU time 1.7 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 200832 kb
Host smart-6a036f4e-96f3-47a0-a116-61a45b183921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197896448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.197896448
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4159279732
Short name T916
Test name
Test status
Simulation time 467441284 ps
CPU time 1.69 seconds
Started Aug 18 05:42:06 PM PDT 24
Finished Aug 18 05:42:08 PM PDT 24
Peak memory 200824 kb
Host smart-bb334ed6-d5fc-4dd5-bf85-6fec247da76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159279732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4159279732
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3171255437
Short name T833
Test name
Test status
Simulation time 2737653387 ps
CPU time 3.79 seconds
Started Aug 18 05:41:51 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200924 kb
Host smart-f8c676de-634b-4eff-ad91-e32514214f4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171255437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3171255437
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3316833855
Short name T885
Test name
Test status
Simulation time 572931419 ps
CPU time 2.92 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 217316 kb
Host smart-5f6ab18a-e8b1-4459-a4c1-9be6c39ef883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316833855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3316833855
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.581491548
Short name T331
Test name
Test status
Simulation time 4323405340 ps
CPU time 4.65 seconds
Started Aug 18 05:42:06 PM PDT 24
Finished Aug 18 05:42:11 PM PDT 24
Peak memory 201080 kb
Host smart-c95b1367-0d59-4d37-be7a-a14b8759821f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581491548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.581491548
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3649937724
Short name T71
Test name
Test status
Simulation time 555798525 ps
CPU time 2.52 seconds
Started Aug 18 05:41:59 PM PDT 24
Finished Aug 18 05:42:01 PM PDT 24
Peak memory 200992 kb
Host smart-6ba2d180-8e48-4c27-9526-3f0bd1c027e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649937724 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3649937724
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4004598234
Short name T863
Test name
Test status
Simulation time 428546464 ps
CPU time 0.96 seconds
Started Aug 18 05:42:13 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 200832 kb
Host smart-2b518a73-691f-4783-aacb-25a52fac29f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004598234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4004598234
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2617359397
Short name T840
Test name
Test status
Simulation time 504021011 ps
CPU time 1.82 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:56 PM PDT 24
Peak memory 200860 kb
Host smart-57c007c0-03e7-46d7-9903-952a9cc13d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617359397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2617359397
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.793640547
Short name T832
Test name
Test status
Simulation time 4462953405 ps
CPU time 16.77 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:42:15 PM PDT 24
Peak memory 201124 kb
Host smart-84c95c66-6a93-4f33-bbc1-14fec457f0d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793640547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.793640547
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.614107541
Short name T862
Test name
Test status
Simulation time 651085448 ps
CPU time 1.64 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 201108 kb
Host smart-4c3ee97c-d1b3-470a-862e-c256e80819cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614107541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.614107541
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1761175020
Short name T81
Test name
Test status
Simulation time 8114582980 ps
CPU time 17.86 seconds
Started Aug 18 05:41:51 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 201112 kb
Host smart-2129ca05-97fa-4a9c-8623-5d8e18d9eb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761175020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1761175020
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2094157786
Short name T702
Test name
Test status
Simulation time 167353368813 ps
CPU time 8.88 seconds
Started Aug 18 05:42:30 PM PDT 24
Finished Aug 18 05:42:39 PM PDT 24
Peak memory 202120 kb
Host smart-ea0b436e-fc14-48d1-912b-b448571dbce5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094157786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2094157786
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.862780658
Short name T238
Test name
Test status
Simulation time 164128728826 ps
CPU time 302.18 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 202072 kb
Host smart-861d3155-60cf-4fc0-97f8-fcedafe4de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862780658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.862780658
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1441090726
Short name T636
Test name
Test status
Simulation time 162936769290 ps
CPU time 101.82 seconds
Started Aug 18 05:42:31 PM PDT 24
Finished Aug 18 05:44:13 PM PDT 24
Peak memory 202136 kb
Host smart-41689d05-a6c7-4fe7-9876-7bca38d5bb31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441090726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1441090726
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3720532009
Short name T140
Test name
Test status
Simulation time 325390612421 ps
CPU time 721.75 seconds
Started Aug 18 05:42:33 PM PDT 24
Finished Aug 18 05:54:35 PM PDT 24
Peak memory 202068 kb
Host smart-3a667ead-3780-4a5c-bc73-2af69148cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720532009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3720532009
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2630579148
Short name T372
Test name
Test status
Simulation time 162458716348 ps
CPU time 66.27 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:44:01 PM PDT 24
Peak memory 202048 kb
Host smart-5a1e03dc-d67f-4249-8c81-d6c184ed804f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630579148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2630579148
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3448965497
Short name T167
Test name
Test status
Simulation time 545461000404 ps
CPU time 342.69 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:48:35 PM PDT 24
Peak memory 202048 kb
Host smart-cb6deac1-9029-44ff-932b-4b1073621ef7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448965497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3448965497
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.270625977
Short name T424
Test name
Test status
Simulation time 390923606742 ps
CPU time 954.51 seconds
Started Aug 18 05:42:40 PM PDT 24
Finished Aug 18 05:58:35 PM PDT 24
Peak memory 202056 kb
Host smart-c8f67e48-d58c-49e0-866f-8524dffd25e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270625977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.270625977
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3186756446
Short name T690
Test name
Test status
Simulation time 140560725600 ps
CPU time 455.24 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 202340 kb
Host smart-9a6524e1-c88a-4691-90ff-c10395d9e4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186756446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3186756446
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.29943268
Short name T436
Test name
Test status
Simulation time 22323748523 ps
CPU time 28.16 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:43:07 PM PDT 24
Peak memory 201924 kb
Host smart-a8a36f58-e1d6-43a4-860c-e60d13a08f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29943268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.29943268
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1790432549
Short name T537
Test name
Test status
Simulation time 3956767606 ps
CPU time 9.37 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:42:59 PM PDT 24
Peak memory 201932 kb
Host smart-e8542b9f-b236-4178-bae2-a81289f20790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790432549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1790432549
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.520261600
Short name T774
Test name
Test status
Simulation time 6189104682 ps
CPU time 5.46 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:42:54 PM PDT 24
Peak memory 201920 kb
Host smart-a597e784-8d37-429b-a32c-888699e7a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520261600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.520261600
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.765643583
Short name T675
Test name
Test status
Simulation time 2282106840 ps
CPU time 6.04 seconds
Started Aug 18 05:42:30 PM PDT 24
Finished Aug 18 05:42:36 PM PDT 24
Peak memory 202288 kb
Host smart-7454ec04-1db9-49e6-8098-8d8976134f50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765643583 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.765643583
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1913933458
Short name T82
Test name
Test status
Simulation time 390684731 ps
CPU time 0.83 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:42:38 PM PDT 24
Peak memory 201944 kb
Host smart-33826895-c4d0-4437-81f0-75745689156a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913933458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1913933458
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1750746420
Short name T736
Test name
Test status
Simulation time 159833806286 ps
CPU time 312.53 seconds
Started Aug 18 05:42:29 PM PDT 24
Finished Aug 18 05:47:41 PM PDT 24
Peak memory 202140 kb
Host smart-55114eeb-39e0-4d7d-9f8a-aa199cb17afb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750746420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1750746420
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1381435553
Short name T610
Test name
Test status
Simulation time 330918430316 ps
CPU time 713.03 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:54:36 PM PDT 24
Peak memory 202132 kb
Host smart-824b3039-0dbd-4f7e-8114-190da22dc14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381435553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1381435553
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2892386308
Short name T483
Test name
Test status
Simulation time 477281621220 ps
CPU time 1053.89 seconds
Started Aug 18 05:42:59 PM PDT 24
Finished Aug 18 06:00:33 PM PDT 24
Peak memory 202152 kb
Host smart-7ead0dff-1fba-4b6f-825d-f1ebd0afd870
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892386308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2892386308
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3909835455
Short name T135
Test name
Test status
Simulation time 167029922695 ps
CPU time 98.98 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:44:35 PM PDT 24
Peak memory 202152 kb
Host smart-e91aeda2-6189-424e-8503-763ce0e7f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909835455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3909835455
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3063630366
Short name T645
Test name
Test status
Simulation time 502899604934 ps
CPU time 71.68 seconds
Started Aug 18 05:42:26 PM PDT 24
Finished Aug 18 05:43:37 PM PDT 24
Peak memory 202064 kb
Host smart-166f5518-a67d-4f43-8a2f-9f49a9111b3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063630366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3063630366
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2815247573
Short name T533
Test name
Test status
Simulation time 368627897598 ps
CPU time 883.73 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:57:57 PM PDT 24
Peak memory 202056 kb
Host smart-ee5d3137-6be9-4f60-9b57-c679ce1206df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815247573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2815247573
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4139316951
Short name T637
Test name
Test status
Simulation time 199615049845 ps
CPU time 58.93 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 202076 kb
Host smart-3c7d477d-dd1c-4911-bda7-38e54ecfc05a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139316951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4139316951
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2098601032
Short name T178
Test name
Test status
Simulation time 105252058971 ps
CPU time 443.25 seconds
Started Aug 18 05:42:28 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 202384 kb
Host smart-03b8aea7-8208-4faa-90f3-16266cb997db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098601032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2098601032
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3912484814
Short name T741
Test name
Test status
Simulation time 39204222729 ps
CPU time 68.31 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:43:53 PM PDT 24
Peak memory 201940 kb
Host smart-e17f713a-3988-4d33-a3df-594a58268e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912484814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3912484814
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3161604040
Short name T406
Test name
Test status
Simulation time 5214064766 ps
CPU time 6.71 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:42:46 PM PDT 24
Peak memory 201896 kb
Host smart-4b46dfc9-ff2d-4e45-b76c-c4bad24deef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161604040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3161604040
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.17787857
Short name T83
Test name
Test status
Simulation time 4285943372 ps
CPU time 6.03 seconds
Started Aug 18 05:42:34 PM PDT 24
Finished Aug 18 05:42:40 PM PDT 24
Peak memory 217416 kb
Host smart-1df2cabb-a684-476c-b39d-a57a6df60017
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.17787857
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1665120216
Short name T486
Test name
Test status
Simulation time 6031038438 ps
CPU time 4.63 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:42:51 PM PDT 24
Peak memory 201928 kb
Host smart-87d24ea6-b63e-4be9-8a2e-b00a1d42ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665120216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1665120216
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.308041694
Short name T511
Test name
Test status
Simulation time 410702598 ps
CPU time 1.61 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:42:48 PM PDT 24
Peak memory 201960 kb
Host smart-56a4800d-c222-4f35-b871-7a31619007aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308041694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.308041694
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3327731307
Short name T166
Test name
Test status
Simulation time 320194985229 ps
CPU time 111.8 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:44:58 PM PDT 24
Peak memory 202088 kb
Host smart-416222e6-552b-4461-9a9a-35ed7916bda9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327731307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3327731307
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.100619988
Short name T275
Test name
Test status
Simulation time 505578018695 ps
CPU time 1194.88 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 06:02:45 PM PDT 24
Peak memory 202112 kb
Host smart-8a6d80e9-75bb-4274-aef9-1c0ed660f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100619988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.100619988
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3734996480
Short name T121
Test name
Test status
Simulation time 495969125186 ps
CPU time 1096.49 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 06:01:05 PM PDT 24
Peak memory 202116 kb
Host smart-08454b85-4d68-4437-b051-66b6409813f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734996480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3734996480
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.433809250
Short name T516
Test name
Test status
Simulation time 487599723881 ps
CPU time 570.18 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:52:45 PM PDT 24
Peak memory 202052 kb
Host smart-585cd8b2-677c-4fc2-83fa-3c2e03285d69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=433809250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.433809250
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4053856648
Short name T153
Test name
Test status
Simulation time 486023868529 ps
CPU time 286.69 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:47:34 PM PDT 24
Peak memory 202168 kb
Host smart-3eb75f64-55da-438c-ab4b-7c499997a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053856648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4053856648
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3505551539
Short name T575
Test name
Test status
Simulation time 325931157860 ps
CPU time 709.64 seconds
Started Aug 18 05:42:58 PM PDT 24
Finished Aug 18 05:54:48 PM PDT 24
Peak memory 202084 kb
Host smart-4fcc9eec-ca0d-4667-917d-0f463fcea8df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505551539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3505551539
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3749369861
Short name T142
Test name
Test status
Simulation time 520255468010 ps
CPU time 312.53 seconds
Started Aug 18 05:42:48 PM PDT 24
Finished Aug 18 05:48:01 PM PDT 24
Peak memory 201952 kb
Host smart-670339eb-e0cb-49b0-8a72-a648061905b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749369861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3749369861
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3420799734
Short name T449
Test name
Test status
Simulation time 194662666864 ps
CPU time 28.76 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:43:05 PM PDT 24
Peak memory 202108 kb
Host smart-3c4b7fd4-e7c9-4721-9456-77667ee82671
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420799734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3420799734
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.660490448
Short name T337
Test name
Test status
Simulation time 130218667785 ps
CPU time 488.07 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 202340 kb
Host smart-1ede3584-4101-4376-aa5a-679de407c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660490448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.660490448
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2463528698
Short name T419
Test name
Test status
Simulation time 44307614876 ps
CPU time 12.57 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:43:26 PM PDT 24
Peak memory 201936 kb
Host smart-dc6da107-f87f-4751-b899-22e7cc5a0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463528698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2463528698
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3163319953
Short name T627
Test name
Test status
Simulation time 4196310757 ps
CPU time 11.59 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:43:03 PM PDT 24
Peak memory 201944 kb
Host smart-f2fa8ae6-009d-4b25-a881-d77dc1f9d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163319953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3163319953
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1837862317
Short name T713
Test name
Test status
Simulation time 5915092861 ps
CPU time 14.87 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:43:01 PM PDT 24
Peak memory 201940 kb
Host smart-f9885eea-ea2d-4d13-93a9-b226e2e9b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837862317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1837862317
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1856416943
Short name T579
Test name
Test status
Simulation time 10931771278 ps
CPU time 24.9 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:43:38 PM PDT 24
Peak memory 201928 kb
Host smart-bd122f27-2f9b-4633-95f2-721584ad20c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856416943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1856416943
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3249174076
Short name T32
Test name
Test status
Simulation time 10260012692 ps
CPU time 3.42 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:42:45 PM PDT 24
Peak memory 202228 kb
Host smart-c5f1f7f1-e4a0-4124-843d-bcf17f8d3eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249174076 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3249174076
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3065196667
Short name T634
Test name
Test status
Simulation time 539114198 ps
CPU time 0.98 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 201940 kb
Host smart-06423cff-99f7-414e-bb3b-d23e801f988a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065196667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3065196667
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3902188286
Short name T89
Test name
Test status
Simulation time 492202624220 ps
CPU time 220.73 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:46:55 PM PDT 24
Peak memory 202104 kb
Host smart-79e97355-1e06-4537-99d0-eafada88cda7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902188286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3902188286
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1083399412
Short name T412
Test name
Test status
Simulation time 336268667381 ps
CPU time 747.15 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:55:21 PM PDT 24
Peak memory 202152 kb
Host smart-ff4c5d67-ba84-4eb3-806e-f32de5786c5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083399412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1083399412
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3702409726
Short name T611
Test name
Test status
Simulation time 159274509542 ps
CPU time 378.87 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 202088 kb
Host smart-c8f5cf53-c7d7-4c12-a468-c6217371f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702409726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3702409726
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1954496897
Short name T434
Test name
Test status
Simulation time 493399520406 ps
CPU time 1118.84 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 06:01:28 PM PDT 24
Peak memory 202128 kb
Host smart-0ec20d75-8a9c-4681-86c0-abd28e938fdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954496897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1954496897
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2284059861
Short name T383
Test name
Test status
Simulation time 598420323175 ps
CPU time 277.67 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:47:31 PM PDT 24
Peak memory 202080 kb
Host smart-aeae9858-a340-4072-8410-8d670e12b555
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284059861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2284059861
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.501423371
Short name T631
Test name
Test status
Simulation time 95169004150 ps
CPU time 358.99 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 202352 kb
Host smart-73bd86af-d74c-4540-9e7d-79c7bd222d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501423371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.501423371
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2722849724
Short name T379
Test name
Test status
Simulation time 39090770847 ps
CPU time 38.41 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:44:02 PM PDT 24
Peak memory 201824 kb
Host smart-94611094-d55d-4389-b9cf-a65b8cd9c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722849724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2722849724
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2958865722
Short name T396
Test name
Test status
Simulation time 3084499250 ps
CPU time 8.28 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:04 PM PDT 24
Peak memory 201920 kb
Host smart-a50e49f2-61d9-433c-a725-8ecfc7bfbcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958865722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2958865722
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2920943567
Short name T488
Test name
Test status
Simulation time 5820582251 ps
CPU time 8.78 seconds
Started Aug 18 05:43:07 PM PDT 24
Finished Aug 18 05:43:16 PM PDT 24
Peak memory 201928 kb
Host smart-5468195e-fa13-4d1f-abc0-5d246c73ca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920943567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2920943567
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.599159689
Short name T754
Test name
Test status
Simulation time 3252026979 ps
CPU time 6.29 seconds
Started Aug 18 05:43:00 PM PDT 24
Finished Aug 18 05:43:06 PM PDT 24
Peak memory 202052 kb
Host smart-e93cfe1a-2b48-4a32-8374-8015cd4e59bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599159689 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.599159689
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1128392828
Short name T422
Test name
Test status
Simulation time 466103495 ps
CPU time 0.86 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:43:12 PM PDT 24
Peak memory 201944 kb
Host smart-8c6be6bd-37b3-4745-8471-2ce8bda963d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128392828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1128392828
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.685411509
Short name T518
Test name
Test status
Simulation time 336828944456 ps
CPU time 209.6 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:46:30 PM PDT 24
Peak memory 202148 kb
Host smart-57cb7c83-a4b1-4635-acf3-6ba36da27345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685411509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.685411509
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1949055586
Short name T400
Test name
Test status
Simulation time 497190554983 ps
CPU time 600.29 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:53:11 PM PDT 24
Peak memory 202096 kb
Host smart-24696b07-66a8-49b0-b8cb-75c7aab5244a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949055586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1949055586
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1610038520
Short name T491
Test name
Test status
Simulation time 167276051450 ps
CPU time 97.31 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:44:53 PM PDT 24
Peak memory 202024 kb
Host smart-c83004c1-5aa0-40ca-a7a3-be362bbbfaaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610038520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1610038520
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.4101672582
Short name T281
Test name
Test status
Simulation time 417520244567 ps
CPU time 937.93 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:58:51 PM PDT 24
Peak memory 202096 kb
Host smart-0187e486-c00c-4f49-b0d0-5eab4b059b16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101672582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.4101672582
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1340334965
Short name T667
Test name
Test status
Simulation time 407371467644 ps
CPU time 232.69 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:47:13 PM PDT 24
Peak memory 202088 kb
Host smart-61687243-825f-4d68-83ad-65b1bba6e331
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340334965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1340334965
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3919449195
Short name T342
Test name
Test status
Simulation time 120124113235 ps
CPU time 618.99 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:53:09 PM PDT 24
Peak memory 202336 kb
Host smart-8251c19f-edfa-4f2f-a77f-01258e6c9ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919449195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3919449195
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2884802491
Short name T389
Test name
Test status
Simulation time 41235021903 ps
CPU time 16.07 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:43:03 PM PDT 24
Peak memory 201884 kb
Host smart-b1492cbf-149b-4d99-80be-dcabd48b5235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884802491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2884802491
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.881949291
Short name T540
Test name
Test status
Simulation time 3153694541 ps
CPU time 6.11 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:43:09 PM PDT 24
Peak memory 201928 kb
Host smart-e4889da9-63a0-4f8c-bcff-c2d3947237a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881949291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.881949291
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1829958005
Short name T116
Test name
Test status
Simulation time 5833423691 ps
CPU time 15.06 seconds
Started Aug 18 05:42:55 PM PDT 24
Finished Aug 18 05:43:10 PM PDT 24
Peak memory 201912 kb
Host smart-55bd6bd0-a3a8-4309-ac05-257882cf8557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829958005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1829958005
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2116961367
Short name T521
Test name
Test status
Simulation time 389457933024 ps
CPU time 28.13 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:43:41 PM PDT 24
Peak memory 218092 kb
Host smart-f2d7e2c0-bc21-409b-afe3-2dbbfb352272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116961367 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2116961367
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1176021772
Short name T684
Test name
Test status
Simulation time 341301051 ps
CPU time 1.38 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:43:13 PM PDT 24
Peak memory 201944 kb
Host smart-19d7f442-6a95-4cc5-a14c-7490b3560161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176021772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1176021772
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4023031099
Short name T688
Test name
Test status
Simulation time 357935779906 ps
CPU time 767.53 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:55:59 PM PDT 24
Peak memory 202148 kb
Host smart-c26de0b9-f758-48f5-8a2d-59445d0ad177
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023031099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4023031099
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1006476896
Short name T746
Test name
Test status
Simulation time 184107079368 ps
CPU time 453.02 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 202156 kb
Host smart-1a1d0ea7-434a-4b9e-a9ac-f3a70d90ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006476896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1006476896
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.977091755
Short name T522
Test name
Test status
Simulation time 164805552695 ps
CPU time 92.28 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:44:30 PM PDT 24
Peak memory 202052 kb
Host smart-bcfa107a-cadc-420c-b1c0-8439b86112a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977091755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.977091755
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3584306540
Short name T698
Test name
Test status
Simulation time 164104619359 ps
CPU time 121.04 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:45:11 PM PDT 24
Peak memory 202080 kb
Host smart-2ed0f3d7-ca2d-49e1-bf39-f9850d0b7952
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584306540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3584306540
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1931043571
Short name T164
Test name
Test status
Simulation time 331448676982 ps
CPU time 75.83 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:44:37 PM PDT 24
Peak memory 202128 kb
Host smart-fec9624f-b286-46b2-a07e-410cc2ec7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931043571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1931043571
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.4067015421
Short name T415
Test name
Test status
Simulation time 317584042536 ps
CPU time 186.64 seconds
Started Aug 18 05:42:59 PM PDT 24
Finished Aug 18 05:46:05 PM PDT 24
Peak memory 202112 kb
Host smart-44d5bb36-e405-44e5-b39f-fecd1338da66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067015421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.4067015421
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1806901862
Short name T236
Test name
Test status
Simulation time 368589450124 ps
CPU time 798.1 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:56:24 PM PDT 24
Peak memory 202040 kb
Host smart-83144954-3c37-4211-ad77-b61bf89c10ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806901862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1806901862
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1321046244
Short name T519
Test name
Test status
Simulation time 404621989842 ps
CPU time 274.57 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:47:24 PM PDT 24
Peak memory 202088 kb
Host smart-c7ebdb56-8484-4e32-a0e6-626d0cc9cd0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321046244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1321046244
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3894698414
Short name T46
Test name
Test status
Simulation time 62182029971 ps
CPU time 264.64 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 202348 kb
Host smart-76eaf950-28e5-4ad0-8f3c-f269e7f48e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894698414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3894698414
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3087199280
Short name T649
Test name
Test status
Simulation time 43115307454 ps
CPU time 24.96 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:21 PM PDT 24
Peak memory 201944 kb
Host smart-9329d6a2-1f4a-4983-9d51-e59db6066079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087199280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3087199280
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1490499461
Short name T561
Test name
Test status
Simulation time 5305750064 ps
CPU time 12.64 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:43:17 PM PDT 24
Peak memory 201944 kb
Host smart-67153ea3-1a76-49e7-bf23-ed1bec966f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490499461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1490499461
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2771237816
Short name T401
Test name
Test status
Simulation time 6056484873 ps
CPU time 6.95 seconds
Started Aug 18 05:42:58 PM PDT 24
Finished Aug 18 05:43:05 PM PDT 24
Peak memory 201944 kb
Host smart-85372272-2867-4b2a-9d7b-866fab29430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771237816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2771237816
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1858936520
Short name T448
Test name
Test status
Simulation time 244127508467 ps
CPU time 423 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 202096 kb
Host smart-9100482a-7657-47f4-8b22-c80dc34bb370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858936520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1858936520
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.434960575
Short name T157
Test name
Test status
Simulation time 2510858248 ps
CPU time 6.31 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:43:17 PM PDT 24
Peak memory 202220 kb
Host smart-213fff94-3890-464a-b657-fe9bcc68b8e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434960575 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.434960575
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3512312930
Short name T470
Test name
Test status
Simulation time 309572096 ps
CPU time 0.76 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:43:07 PM PDT 24
Peak memory 201960 kb
Host smart-30230582-9d2f-409d-b5dd-4ebad59e1eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512312930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3512312930
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2581907594
Short name T315
Test name
Test status
Simulation time 326546811192 ps
CPU time 195.35 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:46:31 PM PDT 24
Peak memory 202112 kb
Host smart-d4047bc8-2b50-4d30-840b-67fb84d0548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581907594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2581907594
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3577615054
Short name T630
Test name
Test status
Simulation time 330424346519 ps
CPU time 800.19 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:56:30 PM PDT 24
Peak memory 202108 kb
Host smart-affeffac-61d3-4c2e-8dcb-a4f1f1ac51c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577615054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3577615054
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3573237109
Short name T577
Test name
Test status
Simulation time 324888750270 ps
CPU time 356.87 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:49:13 PM PDT 24
Peak memory 202092 kb
Host smart-5ce48e88-d1fa-4096-916d-8389c9a05563
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573237109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3573237109
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2259206131
Short name T232
Test name
Test status
Simulation time 167091356601 ps
CPU time 87.72 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:44:19 PM PDT 24
Peak memory 202096 kb
Host smart-e007be54-b01b-4516-9791-00d1eaaa0d8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259206131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2259206131
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1355854419
Short name T705
Test name
Test status
Simulation time 592475427236 ps
CPU time 77.72 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:44:31 PM PDT 24
Peak memory 202080 kb
Host smart-4ad8512e-d3a4-4f66-87dc-03dbd8bf8bbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355854419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1355854419
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1850410212
Short name T41
Test name
Test status
Simulation time 95855691192 ps
CPU time 391.52 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:49:27 PM PDT 24
Peak memory 202420 kb
Host smart-b8249677-505b-41c5-a010-1dbd775cd6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850410212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1850410212
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.56923283
Short name T390
Test name
Test status
Simulation time 41863667762 ps
CPU time 23.09 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:43:41 PM PDT 24
Peak memory 201892 kb
Host smart-62c8fefb-f747-4cd6-a6cf-d56d23bb9e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56923283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.56923283
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.893152810
Short name T586
Test name
Test status
Simulation time 5122004013 ps
CPU time 12.79 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:43:07 PM PDT 24
Peak memory 201920 kb
Host smart-9687ec4b-3514-4fb2-a1c1-a3e7147b0238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893152810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.893152810
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3248568036
Short name T624
Test name
Test status
Simulation time 5783720984 ps
CPU time 14.92 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:43:20 PM PDT 24
Peak memory 201908 kb
Host smart-4d0230bf-5a1c-43e9-8854-6ffeaf6be2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248568036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3248568036
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2360781648
Short name T787
Test name
Test status
Simulation time 168617585711 ps
CPU time 501.38 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 202316 kb
Host smart-455ddaf6-8b1a-48ce-a4cb-5bffa6a3b41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360781648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2360781648
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1450901880
Short name T34
Test name
Test status
Simulation time 5843922794 ps
CPU time 11.27 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 210508 kb
Host smart-d39f21c4-d17a-43e0-a31e-4a19f0d11b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450901880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1450901880
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3929650750
Short name T562
Test name
Test status
Simulation time 501996305 ps
CPU time 0.93 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:42:55 PM PDT 24
Peak memory 201964 kb
Host smart-4f2d15dd-c78d-479a-a4f7-cc91f25a95c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929650750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3929650750
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.296288878
Short name T545
Test name
Test status
Simulation time 223304372485 ps
CPU time 32.74 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:43:37 PM PDT 24
Peak memory 202124 kb
Host smart-7db78588-89ac-4dc9-b790-7bcc8936e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296288878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.296288878
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2497403193
Short name T490
Test name
Test status
Simulation time 332680644131 ps
CPU time 758.76 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:55:59 PM PDT 24
Peak memory 202172 kb
Host smart-c2a9cdbc-83a1-41e3-acb7-e0f762c252b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497403193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2497403193
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3432715890
Short name T271
Test name
Test status
Simulation time 486107480490 ps
CPU time 561.95 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:52:35 PM PDT 24
Peak memory 202120 kb
Host smart-ec3dab1c-7eb4-4263-91f9-4c36e21d77eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432715890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3432715890
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1983788783
Short name T646
Test name
Test status
Simulation time 492816260278 ps
CPU time 290.75 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 202112 kb
Host smart-0816871a-eedf-4ef9-83c8-0554efe0de38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983788783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1983788783
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3270802406
Short name T360
Test name
Test status
Simulation time 200633235165 ps
CPU time 429.14 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 202148 kb
Host smart-a0082517-aa47-4e75-a7ff-04091fef39fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270802406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3270802406
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3428774681
Short name T439
Test name
Test status
Simulation time 99549628883 ps
CPU time 389.95 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 202360 kb
Host smart-b86c4a45-6a9f-4a1a-abfd-6e39216fb457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428774681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3428774681
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1954536702
Short name T366
Test name
Test status
Simulation time 35320421525 ps
CPU time 80.75 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:44:22 PM PDT 24
Peak memory 201652 kb
Host smart-9c8d974d-a200-43a3-8280-2f11a6f3be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954536702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1954536702
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1832941492
Short name T393
Test name
Test status
Simulation time 3519602091 ps
CPU time 5.13 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:43:08 PM PDT 24
Peak memory 201832 kb
Host smart-833e311e-aedc-4d5c-b84f-cac6a0f00f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832941492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1832941492
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.968082510
Short name T440
Test name
Test status
Simulation time 5778807460 ps
CPU time 12.97 seconds
Started Aug 18 05:43:00 PM PDT 24
Finished Aug 18 05:43:13 PM PDT 24
Peak memory 201924 kb
Host smart-b01c0c18-b445-48b5-b7bf-9bd6246edafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968082510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.968082510
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.127278774
Short name T273
Test name
Test status
Simulation time 628402082302 ps
CPU time 573.16 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 210612 kb
Host smart-2cf89a1c-b281-4700-94e2-eddd1331eb47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127278774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
127278774
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3390216086
Short name T36
Test name
Test status
Simulation time 3953863664 ps
CPU time 9.72 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:43:04 PM PDT 24
Peak memory 210428 kb
Host smart-3e148641-b813-4d8f-9454-4790afa8b3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390216086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3390216086
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.645755756
Short name T707
Test name
Test status
Simulation time 438454658 ps
CPU time 0.83 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:43:26 PM PDT 24
Peak memory 201924 kb
Host smart-19f9b929-2afc-4aec-b4c6-336efe139ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645755756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.645755756
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1795283726
Short name T218
Test name
Test status
Simulation time 513673485291 ps
CPU time 1074.34 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 202100 kb
Host smart-cbf40cdd-3a6f-4200-93f5-36e1015de490
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795283726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1795283726
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3455959763
Short name T648
Test name
Test status
Simulation time 538120343741 ps
CPU time 639.76 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:53:49 PM PDT 24
Peak memory 202108 kb
Host smart-4e005813-c7c7-41a5-be9b-75f86baa6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455959763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3455959763
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1836804634
Short name T228
Test name
Test status
Simulation time 487314433649 ps
CPU time 576.75 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:52:29 PM PDT 24
Peak memory 202088 kb
Host smart-a1890767-d976-4b63-905a-1c1c31b1ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836804634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1836804634
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2139318526
Short name T416
Test name
Test status
Simulation time 165005274153 ps
CPU time 352.48 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:48:57 PM PDT 24
Peak memory 202092 kb
Host smart-55b91588-da5c-4c39-95e5-be2212af9bfd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139318526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2139318526
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4032736389
Short name T292
Test name
Test status
Simulation time 490170816035 ps
CPU time 295.8 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:47:49 PM PDT 24
Peak memory 202132 kb
Host smart-0052408e-36b9-4e66-a717-0a7a95b22d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032736389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4032736389
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1755252918
Short name T97
Test name
Test status
Simulation time 492883845450 ps
CPU time 610.75 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:53:01 PM PDT 24
Peak memory 202080 kb
Host smart-4e7b084a-8c30-4aff-91d5-821187cccf83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755252918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1755252918
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4261079682
Short name T156
Test name
Test status
Simulation time 183526625029 ps
CPU time 107.71 seconds
Started Aug 18 05:43:07 PM PDT 24
Finished Aug 18 05:44:55 PM PDT 24
Peak memory 202060 kb
Host smart-b552d1f1-b258-442b-b881-7bdbc688112d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261079682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4261079682
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2994612817
Short name T507
Test name
Test status
Simulation time 189634855891 ps
CPU time 396.24 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 202068 kb
Host smart-33d6151c-3550-46a3-8495-3714d4b9e53d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994612817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2994612817
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2749084660
Short name T497
Test name
Test status
Simulation time 90063877631 ps
CPU time 530.03 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:51:53 PM PDT 24
Peak memory 202360 kb
Host smart-21a98840-0b5e-4519-b505-cfec1d065a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749084660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2749084660
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.949616490
Short name T469
Test name
Test status
Simulation time 46424990625 ps
CPU time 56.49 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:44:13 PM PDT 24
Peak memory 201904 kb
Host smart-4ccc4986-2947-449e-9803-3587aab43837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949616490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.949616490
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2960829554
Short name T683
Test name
Test status
Simulation time 5302860437 ps
CPU time 3.34 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:43:21 PM PDT 24
Peak memory 201952 kb
Host smart-db88f27f-7c2d-47ee-a5d4-c5d5901ce147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960829554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2960829554
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2589773738
Short name T489
Test name
Test status
Simulation time 5895448022 ps
CPU time 10.37 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:43:23 PM PDT 24
Peak memory 201920 kb
Host smart-22c70cf6-864e-472c-b538-8786d0375a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589773738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2589773738
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1785041734
Short name T407
Test name
Test status
Simulation time 2616382453 ps
CPU time 5.68 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:43:15 PM PDT 24
Peak memory 202228 kb
Host smart-8b58c0c1-529a-4502-9a20-6a89261cb329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785041734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1785041734
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2868464270
Short name T651
Test name
Test status
Simulation time 413923294 ps
CPU time 1.51 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:43:11 PM PDT 24
Peak memory 201968 kb
Host smart-621c52e9-f303-4dd3-8b5f-474c36e823fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868464270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2868464270
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3769269795
Short name T119
Test name
Test status
Simulation time 197847934236 ps
CPU time 456.32 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 202084 kb
Host smart-41c5c16c-deb5-4652-9a9e-b321668d8f52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769269795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3769269795
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.697582228
Short name T163
Test name
Test status
Simulation time 328695702582 ps
CPU time 131.85 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:45:33 PM PDT 24
Peak memory 202116 kb
Host smart-70eed2ad-a8c0-4d44-97a6-dc01b9459676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697582228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.697582228
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3297418376
Short name T240
Test name
Test status
Simulation time 164641431852 ps
CPU time 110.93 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:44:57 PM PDT 24
Peak memory 202012 kb
Host smart-0aeeaf75-e333-477f-a979-f466a877b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297418376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3297418376
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2714739921
Short name T378
Test name
Test status
Simulation time 324347972270 ps
CPU time 498.52 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 202112 kb
Host smart-a04754f7-1773-46a9-8a8b-7e16f746c8b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714739921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2714739921
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2729783294
Short name T131
Test name
Test status
Simulation time 167146916557 ps
CPU time 136.5 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:45:14 PM PDT 24
Peak memory 202096 kb
Host smart-a2f6ca18-b268-4e5d-91ba-35a4b04fb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729783294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2729783294
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2261664786
Short name T137
Test name
Test status
Simulation time 169629773563 ps
CPU time 82.15 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:44:16 PM PDT 24
Peak memory 202120 kb
Host smart-0cc34775-16ef-48f9-8444-53f39027b09f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261664786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2261664786
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3986484029
Short name T120
Test name
Test status
Simulation time 371778361856 ps
CPU time 817.34 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 05:56:58 PM PDT 24
Peak memory 202112 kb
Host smart-c94538aa-6a95-49c1-9747-d5aaf9c81bcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986484029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3986484029
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.735220025
Short name T639
Test name
Test status
Simulation time 619961270957 ps
CPU time 1354.25 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 06:05:54 PM PDT 24
Peak memory 202076 kb
Host smart-c4e609de-0230-4c44-ab59-630f3c2efd29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735220025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.735220025
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2558893503
Short name T194
Test name
Test status
Simulation time 109508993797 ps
CPU time 351.97 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 202308 kb
Host smart-7e9bcdbe-5904-43c5-bcc4-20cdbae6e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558893503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2558893503
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1615626519
Short name T411
Test name
Test status
Simulation time 34643433561 ps
CPU time 85.05 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:44:44 PM PDT 24
Peak memory 201872 kb
Host smart-714d24a4-fe6b-466c-b709-204b1913bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615626519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1615626519
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1711619374
Short name T530
Test name
Test status
Simulation time 3364966844 ps
CPU time 1.36 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:43:06 PM PDT 24
Peak memory 201940 kb
Host smart-372c10b4-ee90-4e55-970f-1ba3325b145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711619374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1711619374
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4055219061
Short name T349
Test name
Test status
Simulation time 5666861585 ps
CPU time 4.06 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:43:28 PM PDT 24
Peak memory 201880 kb
Host smart-7f320a28-793a-461c-b411-49de1def46a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055219061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4055219061
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3384712703
Short name T563
Test name
Test status
Simulation time 69980888692 ps
CPU time 153.34 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:45:35 PM PDT 24
Peak memory 201784 kb
Host smart-79ea5bef-e3a3-4178-aafa-4825e6bb654f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384712703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3384712703
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1643888385
Short name T653
Test name
Test status
Simulation time 47896198162 ps
CPU time 15.03 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:43:29 PM PDT 24
Peak memory 211000 kb
Host smart-b13d8553-7996-496a-b3d9-169cb059a9f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643888385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1643888385
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4182601224
Short name T532
Test name
Test status
Simulation time 286897148 ps
CPU time 1.17 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 200544 kb
Host smart-a7eceac9-dc87-4af3-93da-2d4ef76a830d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182601224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4182601224
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.318717673
Short name T248
Test name
Test status
Simulation time 192648276138 ps
CPU time 9.17 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:43:34 PM PDT 24
Peak memory 202076 kb
Host smart-cc7369d0-eeb6-491a-85cf-37996d0bc9dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318717673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.318717673
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4229255010
Short name T303
Test name
Test status
Simulation time 494192840611 ps
CPU time 1073.33 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 06:01:14 PM PDT 24
Peak memory 202080 kb
Host smart-8c46bb0a-155d-4bea-afd9-6a56dc56209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229255010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4229255010
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1247007780
Short name T559
Test name
Test status
Simulation time 328047340330 ps
CPU time 210.71 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:46:39 PM PDT 24
Peak memory 202080 kb
Host smart-b7d8ac7c-e33e-456a-914a-95c883f0f7e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247007780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1247007780
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1990318054
Short name T301
Test name
Test status
Simulation time 331963845889 ps
CPU time 160.46 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:45:58 PM PDT 24
Peak memory 202148 kb
Host smart-76288228-57f0-4535-be61-da39b415fd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990318054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1990318054
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2046582321
Short name T359
Test name
Test status
Simulation time 330066992921 ps
CPU time 756.41 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:55:40 PM PDT 24
Peak memory 202252 kb
Host smart-0f4c9d31-5ad3-4365-a6bf-b3734fdd6d70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046582321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2046582321
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.941336372
Short name T724
Test name
Test status
Simulation time 519869973044 ps
CPU time 1140.12 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 06:02:06 PM PDT 24
Peak memory 202120 kb
Host smart-315524cc-76da-4828-91f4-2b0b511ca121
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941336372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.941336372
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2743159719
Short name T456
Test name
Test status
Simulation time 210934688836 ps
CPU time 65.79 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:44:22 PM PDT 24
Peak memory 202012 kb
Host smart-2ee61ea3-dee0-4fa4-b38b-e03ade306139
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743159719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2743159719
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2065859187
Short name T658
Test name
Test status
Simulation time 26160823379 ps
CPU time 49.23 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:44:19 PM PDT 24
Peak memory 201872 kb
Host smart-3fe3e963-d265-402a-a30c-c00d636ff0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065859187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2065859187
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.478876141
Short name T495
Test name
Test status
Simulation time 4105042737 ps
CPU time 2.96 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 202120 kb
Host smart-d4c2c871-b7c2-4986-8faa-e012b4d37cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478876141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.478876141
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3499420023
Short name T492
Test name
Test status
Simulation time 5981484765 ps
CPU time 4.43 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:43:15 PM PDT 24
Peak memory 201892 kb
Host smart-2574f7e4-9a05-406f-acac-6d2980bd75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499420023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3499420023
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3480540523
Short name T388
Test name
Test status
Simulation time 1909479146 ps
CPU time 4.85 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:43:18 PM PDT 24
Peak memory 202176 kb
Host smart-b6f11f26-6874-4d37-b7af-abb4547397f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480540523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3480540523
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1846525413
Short name T664
Test name
Test status
Simulation time 431720867 ps
CPU time 1.67 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:43:19 PM PDT 24
Peak memory 201944 kb
Host smart-587af384-1cc0-42ca-8d1d-4ced6b7d97b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846525413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1846525413
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.433564419
Short name T584
Test name
Test status
Simulation time 489018138253 ps
CPU time 1122.31 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 06:02:02 PM PDT 24
Peak memory 202108 kb
Host smart-5d929730-2da4-41b3-807b-1de934731535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433564419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.433564419
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4109101798
Short name T514
Test name
Test status
Simulation time 325572222462 ps
CPU time 808.49 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:56:47 PM PDT 24
Peak memory 202072 kb
Host smart-158960b0-2d96-4fc9-8ee2-9f42fe0e6dea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109101798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4109101798
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1879982150
Short name T169
Test name
Test status
Simulation time 474794306594 ps
CPU time 321.19 seconds
Started Aug 18 05:42:59 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 202092 kb
Host smart-8c14c3ed-4e27-452a-a115-afd6b14a587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879982150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1879982150
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1365493624
Short name T376
Test name
Test status
Simulation time 338923682204 ps
CPU time 257.45 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:47:27 PM PDT 24
Peak memory 202048 kb
Host smart-cde77c1e-6f9e-45af-8ecd-cceaa2ab17d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365493624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1365493624
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3902652210
Short name T313
Test name
Test status
Simulation time 336808482502 ps
CPU time 391.88 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:49:49 PM PDT 24
Peak memory 200716 kb
Host smart-6835ee2e-3472-4889-b7db-66ec8fbe91e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902652210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3902652210
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1397833544
Short name T207
Test name
Test status
Simulation time 386054389853 ps
CPU time 187.47 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:46:23 PM PDT 24
Peak memory 202060 kb
Host smart-f34345f3-0ecf-492c-9861-3a43029af583
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397833544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1397833544
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3725725903
Short name T535
Test name
Test status
Simulation time 86027054796 ps
CPU time 278.2 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 202408 kb
Host smart-528e4018-70ac-480d-af73-29be36167a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725725903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3725725903
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.146548273
Short name T377
Test name
Test status
Simulation time 30557579964 ps
CPU time 67.9 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:44:16 PM PDT 24
Peak memory 202128 kb
Host smart-f8be38da-36d2-4307-938b-0c3472f40c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146548273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.146548273
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.715385394
Short name T541
Test name
Test status
Simulation time 3507009442 ps
CPU time 9.09 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:43:11 PM PDT 24
Peak memory 201936 kb
Host smart-e813b535-cbb6-46cc-8351-319e74e674f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715385394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.715385394
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3827052718
Short name T405
Test name
Test status
Simulation time 5754677444 ps
CPU time 7.59 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:43:17 PM PDT 24
Peak memory 201940 kb
Host smart-4e94efe1-7673-4760-8f4c-da850823dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827052718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3827052718
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.227721670
Short name T670
Test name
Test status
Simulation time 67342666273 ps
CPU time 42 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:43:45 PM PDT 24
Peak memory 201940 kb
Host smart-7e6dd0d0-58e5-4488-b069-f04407370f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227721670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
227721670
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.228225647
Short name T2
Test name
Test status
Simulation time 2159727556 ps
CPU time 5.63 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:43:13 PM PDT 24
Peak memory 202060 kb
Host smart-3d2fac30-b565-4779-bd3f-2e954a1fb25d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228225647 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.228225647
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.591785373
Short name T4
Test name
Test status
Simulation time 344157881 ps
CPU time 0.97 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:42:40 PM PDT 24
Peak memory 201968 kb
Host smart-5b6073ce-0789-4429-9970-6cd9f6cac4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591785373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.591785373
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.778846609
Short name T758
Test name
Test status
Simulation time 355690603783 ps
CPU time 88.67 seconds
Started Aug 18 05:42:31 PM PDT 24
Finished Aug 18 05:44:00 PM PDT 24
Peak memory 202096 kb
Host smart-501da4e4-8436-460f-8d82-e516fc9dfe6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778846609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.778846609
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.462499663
Short name T755
Test name
Test status
Simulation time 164626723777 ps
CPU time 358.99 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:48:49 PM PDT 24
Peak memory 202084 kb
Host smart-e393240f-874e-47b9-9b19-719fa4df8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462499663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.462499663
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3648760652
Short name T241
Test name
Test status
Simulation time 499088603514 ps
CPU time 993.96 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:59:11 PM PDT 24
Peak memory 202112 kb
Host smart-e4d76d93-17b1-4ab6-8f79-27fb8e6bae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648760652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3648760652
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2451720223
Short name T350
Test name
Test status
Simulation time 328713282343 ps
CPU time 656.51 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:53:34 PM PDT 24
Peak memory 202092 kb
Host smart-07fa487f-0300-4578-8b4e-5683b0950f06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451720223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2451720223
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.413233569
Short name T431
Test name
Test status
Simulation time 161684252639 ps
CPU time 349.87 seconds
Started Aug 18 05:42:29 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 202160 kb
Host smart-7ab64565-d729-4d29-ab2d-efa8df1bf31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413233569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.413233569
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1711424917
Short name T404
Test name
Test status
Simulation time 492045490552 ps
CPU time 229.71 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:47:07 PM PDT 24
Peak memory 201984 kb
Host smart-8fd34631-245d-40a3-aa57-38fbdd36d1f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711424917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1711424917
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.377388458
Short name T168
Test name
Test status
Simulation time 553231849723 ps
CPU time 98.52 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:44:16 PM PDT 24
Peak memory 202076 kb
Host smart-9b383809-240e-4ec8-bf8c-550194e550e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377388458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.377388458
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3265978364
Short name T91
Test name
Test status
Simulation time 197939430395 ps
CPU time 84.02 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:44:00 PM PDT 24
Peak memory 202112 kb
Host smart-f68f3165-e756-4cad-a55f-ba1e40064a24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265978364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3265978364
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2254060966
Short name T589
Test name
Test status
Simulation time 28923643023 ps
CPU time 15.44 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 201928 kb
Host smart-aa3d8a9f-41ea-44d6-8f5c-a32cd3f37483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254060966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2254060966
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2603064178
Short name T799
Test name
Test status
Simulation time 3011142004 ps
CPU time 8.64 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:42:47 PM PDT 24
Peak memory 201928 kb
Host smart-712aa369-a3a1-4b0d-90ed-676b1615d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603064178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2603064178
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3961585905
Short name T63
Test name
Test status
Simulation time 7641721011 ps
CPU time 18.98 seconds
Started Aug 18 05:42:34 PM PDT 24
Finished Aug 18 05:42:53 PM PDT 24
Peak memory 218580 kb
Host smart-ba39be38-641e-480f-bc3c-b18b029a4403
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961585905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3961585905
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3173334941
Short name T369
Test name
Test status
Simulation time 5628223631 ps
CPU time 2.93 seconds
Started Aug 18 05:42:44 PM PDT 24
Finished Aug 18 05:42:47 PM PDT 24
Peak memory 201928 kb
Host smart-29b15545-d170-484e-b6ad-1a7b59c9bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173334941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3173334941
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.888436081
Short name T312
Test name
Test status
Simulation time 338582668034 ps
CPU time 390.21 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:49:16 PM PDT 24
Peak memory 202056 kb
Host smart-4b88361f-0d93-4e48-851c-f420a30167ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888436081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.888436081
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.767011203
Short name T367
Test name
Test status
Simulation time 387820523 ps
CPU time 1.11 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:43:12 PM PDT 24
Peak memory 201936 kb
Host smart-014d1c2d-86cb-4712-af14-fa7cd6e8f7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767011203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.767011203
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.178012750
Short name T796
Test name
Test status
Simulation time 193997661333 ps
CPU time 87.53 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:44:46 PM PDT 24
Peak memory 202124 kb
Host smart-d5f0e8ba-528c-4c2d-8bbd-63fd3795ed39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178012750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.178012750
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2177809229
Short name T291
Test name
Test status
Simulation time 355717044179 ps
CPU time 404.42 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 200656 kb
Host smart-92715e62-f925-4f9b-acb7-0ae115a62d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177809229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2177809229
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3743863316
Short name T239
Test name
Test status
Simulation time 331235295902 ps
CPU time 693.25 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:54:58 PM PDT 24
Peak memory 200656 kb
Host smart-4161e981-0b1a-4809-bf5e-6f38e5f49b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743863316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3743863316
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1980789653
Short name T565
Test name
Test status
Simulation time 485797119166 ps
CPU time 274.67 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 202124 kb
Host smart-9fb9a997-7d6d-4b61-bb74-01e86adcc96d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980789653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1980789653
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3820708286
Short name T494
Test name
Test status
Simulation time 319964885923 ps
CPU time 187.85 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:46:23 PM PDT 24
Peak memory 200672 kb
Host smart-ee97cd9d-42cc-4da1-9ecc-32c0abbd50ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820708286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3820708286
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.999954509
Short name T678
Test name
Test status
Simulation time 486589361651 ps
CPU time 98.16 seconds
Started Aug 18 05:43:08 PM PDT 24
Finished Aug 18 05:44:46 PM PDT 24
Peak memory 202012 kb
Host smart-7cf68afb-ad9f-445f-a696-034d214a8024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=999954509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.999954509
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1372281834
Short name T255
Test name
Test status
Simulation time 523517454725 ps
CPU time 1241.52 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 06:03:52 PM PDT 24
Peak memory 202012 kb
Host smart-7ea15682-b63c-4690-8262-be6173333b34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372281834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1372281834
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2247576289
Short name T652
Test name
Test status
Simulation time 598945158817 ps
CPU time 360.55 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:49:14 PM PDT 24
Peak memory 202048 kb
Host smart-2790d5ba-9436-463b-b5f2-d8021b690b1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247576289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2247576289
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2015253227
Short name T500
Test name
Test status
Simulation time 69305353919 ps
CPU time 406.68 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 202344 kb
Host smart-81a7fc77-5281-4ede-9d04-50629164a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015253227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2015253227
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3110238695
Short name T560
Test name
Test status
Simulation time 27035742181 ps
CPU time 30.69 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:43:45 PM PDT 24
Peak memory 201924 kb
Host smart-c08aae9f-07c5-4cd4-98ac-c61fd0f83950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110238695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3110238695
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2345659104
Short name T468
Test name
Test status
Simulation time 2762714785 ps
CPU time 2.32 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:43:06 PM PDT 24
Peak memory 201888 kb
Host smart-e072d097-d38d-41de-bd94-1537f92ed54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345659104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2345659104
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3423451656
Short name T466
Test name
Test status
Simulation time 5968541377 ps
CPU time 3.93 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:00 PM PDT 24
Peak memory 201944 kb
Host smart-31811d43-9126-45fa-995d-8eccc245146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423451656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3423451656
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4153454965
Short name T603
Test name
Test status
Simulation time 475752945 ps
CPU time 1.68 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:43:17 PM PDT 24
Peak memory 201952 kb
Host smart-d45ccc49-4fc4-4044-b116-483d51b0dfa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153454965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4153454965
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2589011827
Short name T252
Test name
Test status
Simulation time 568632493578 ps
CPU time 492.02 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 202088 kb
Host smart-657012ef-c11b-4dd1-933d-c27a43049d1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589011827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2589011827
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.144197488
Short name T628
Test name
Test status
Simulation time 167465419245 ps
CPU time 356.8 seconds
Started Aug 18 05:42:59 PM PDT 24
Finished Aug 18 05:49:01 PM PDT 24
Peak memory 202120 kb
Host smart-526186aa-5813-45e7-9056-a0381595bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144197488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.144197488
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.399931017
Short name T509
Test name
Test status
Simulation time 484545620326 ps
CPU time 1043.14 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 06:00:37 PM PDT 24
Peak memory 202100 kb
Host smart-b02cc407-5ae9-467f-a2f7-46e8d8187279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=399931017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.399931017
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3499469146
Short name T733
Test name
Test status
Simulation time 331187022543 ps
CPU time 185.62 seconds
Started Aug 18 05:43:27 PM PDT 24
Finished Aug 18 05:46:32 PM PDT 24
Peak memory 201964 kb
Host smart-a6bd2059-ff24-4456-addf-ebe317e52f44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499469146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3499469146
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4217675027
Short name T513
Test name
Test status
Simulation time 622085953487 ps
CPU time 1411.01 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 06:06:55 PM PDT 24
Peak memory 202064 kb
Host smart-0b2de066-f405-44f2-a19d-5bf79ed39af8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217675027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4217675027
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.57873144
Short name T188
Test name
Test status
Simulation time 124548594660 ps
CPU time 418.16 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:50:16 PM PDT 24
Peak memory 202328 kb
Host smart-d2148f0d-0e2c-40b2-8bdb-ff06954f60b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57873144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.57873144
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3075187754
Short name T596
Test name
Test status
Simulation time 29918051660 ps
CPU time 70.98 seconds
Started Aug 18 05:43:28 PM PDT 24
Finished Aug 18 05:44:39 PM PDT 24
Peak memory 201896 kb
Host smart-175b7eb8-1e08-4c71-bbf7-9df50cb3b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075187754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3075187754
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.681249366
Short name T689
Test name
Test status
Simulation time 4233368494 ps
CPU time 5.55 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:42:58 PM PDT 24
Peak memory 201928 kb
Host smart-69c5e464-8551-4fd2-b347-8034fe1208ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681249366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.681249366
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4189488930
Short name T528
Test name
Test status
Simulation time 5766928259 ps
CPU time 16.31 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:43:46 PM PDT 24
Peak memory 201892 kb
Host smart-a980f292-c0df-4533-910c-47e8d5cc93f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189488930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4189488930
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.170365315
Short name T343
Test name
Test status
Simulation time 2163420882 ps
CPU time 5.93 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:27 PM PDT 24
Peak memory 210608 kb
Host smart-eb6c7561-1fd7-4b3c-b925-e98946c3132f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170365315 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.170365315
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3819144188
Short name T397
Test name
Test status
Simulation time 447497597 ps
CPU time 1.4 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:43:19 PM PDT 24
Peak memory 201956 kb
Host smart-37e5e637-94ff-4db2-b75d-7ef92eb3d220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819144188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3819144188
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3131177849
Short name T768
Test name
Test status
Simulation time 427627333123 ps
CPU time 255.05 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 202112 kb
Host smart-4e57fb69-f886-4d1f-aaa6-ee7e932c7547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131177849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3131177849
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2381657783
Short name T600
Test name
Test status
Simulation time 499660691074 ps
CPU time 488.06 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 202156 kb
Host smart-3aa50e63-4f07-406c-9853-8ba50b8d5f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381657783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2381657783
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1682448955
Short name T601
Test name
Test status
Simulation time 169174309139 ps
CPU time 396.57 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 202028 kb
Host smart-14d3a7a9-17e4-4f08-9ae8-d3d84a57ecc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682448955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1682448955
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.665527090
Short name T761
Test name
Test status
Simulation time 165093398840 ps
CPU time 372.14 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 202116 kb
Host smart-1fbb7156-54f3-421c-af56-1bd5110455ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665527090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.665527090
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2886680787
Short name T714
Test name
Test status
Simulation time 491894135049 ps
CPU time 980.51 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:59:30 PM PDT 24
Peak memory 202116 kb
Host smart-19262d1c-6092-4f99-8684-eb9c9c24d56e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886680787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2886680787
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3045529004
Short name T539
Test name
Test status
Simulation time 612872172795 ps
CPU time 654.04 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:54:19 PM PDT 24
Peak memory 202088 kb
Host smart-d5f7033e-5279-4e99-a0d5-8dd03d26a33f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045529004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3045529004
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2540189007
Short name T44
Test name
Test status
Simulation time 116791603859 ps
CPU time 452.36 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 202212 kb
Host smart-25d36789-c5fb-4a9b-a9a4-2894d4b49c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540189007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2540189007
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3947692644
Short name T697
Test name
Test status
Simulation time 21034030104 ps
CPU time 45.67 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:43:56 PM PDT 24
Peak memory 201916 kb
Host smart-4d14405a-3ed5-428d-8ec8-91b2fa388ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947692644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3947692644
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.120525170
Short name T763
Test name
Test status
Simulation time 4793225121 ps
CPU time 3.61 seconds
Started Aug 18 05:43:27 PM PDT 24
Finished Aug 18 05:43:31 PM PDT 24
Peak memory 201928 kb
Host smart-8f06be83-1953-42f6-9b03-b621cf22d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120525170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.120525170
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3815848543
Short name T595
Test name
Test status
Simulation time 5955985944 ps
CPU time 1.54 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:43:16 PM PDT 24
Peak memory 201880 kb
Host smart-28dfee51-f170-456b-a2f9-db4a73aff81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815848543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3815848543
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1216715024
Short name T300
Test name
Test status
Simulation time 14253289469 ps
CPU time 21.31 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:43:35 PM PDT 24
Peak memory 217112 kb
Host smart-14d55a94-f3fa-4291-9259-349c742027fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216715024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1216715024
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3295817950
Short name T457
Test name
Test status
Simulation time 470522858 ps
CPU time 0.86 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:22 PM PDT 24
Peak memory 201952 kb
Host smart-94702695-ef4c-4df8-b2ed-46ede10351e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295817950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3295817950
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1678724739
Short name T170
Test name
Test status
Simulation time 165921325703 ps
CPU time 108.7 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:44:53 PM PDT 24
Peak memory 202100 kb
Host smart-4f345c64-f8a6-4bee-9f2d-fa9dd856d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678724739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1678724739
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2478615222
Short name T221
Test name
Test status
Simulation time 481444113147 ps
CPU time 1068.97 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 06:01:01 PM PDT 24
Peak memory 202280 kb
Host smart-68de4093-9b0f-458e-8432-ec2885f234d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478615222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2478615222
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3393528313
Short name T450
Test name
Test status
Simulation time 167708989622 ps
CPU time 40.73 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:44:05 PM PDT 24
Peak memory 202124 kb
Host smart-37a2c2ef-e566-4649-8438-30bac1c962ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393528313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3393528313
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3071414526
Short name T556
Test name
Test status
Simulation time 169678540792 ps
CPU time 92.83 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:44:39 PM PDT 24
Peak memory 202172 kb
Host smart-9978b377-ffa1-4400-bdb0-c29afd6218ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071414526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3071414526
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2766396205
Short name T347
Test name
Test status
Simulation time 163356845252 ps
CPU time 386.31 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:49:48 PM PDT 24
Peak memory 201952 kb
Host smart-0be1f1e2-ab39-49d1-a66a-0cc4adc7a561
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766396205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2766396205
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.984527166
Short name T256
Test name
Test status
Simulation time 358109530909 ps
CPU time 397.69 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 202100 kb
Host smart-f89a7f29-24c0-4626-8814-8df789b92636
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984527166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.984527166
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3425421917
Short name T353
Test name
Test status
Simulation time 203437585396 ps
CPU time 466.6 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:50:59 PM PDT 24
Peak memory 202100 kb
Host smart-cad18418-2c6b-4a84-9b9d-a7729d40a79a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425421917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3425421917
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2623508007
Short name T477
Test name
Test status
Simulation time 130131063711 ps
CPU time 385.36 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:49:49 PM PDT 24
Peak memory 202372 kb
Host smart-a775b046-48c6-49d9-9980-055c328c63d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623508007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2623508007
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.495274073
Short name T709
Test name
Test status
Simulation time 39482586862 ps
CPU time 22.78 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:43:54 PM PDT 24
Peak memory 201940 kb
Host smart-a1e5437b-fa1f-4e1a-aef1-b823e6156c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495274073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.495274073
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1767449889
Short name T598
Test name
Test status
Simulation time 4835766208 ps
CPU time 13.15 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 201940 kb
Host smart-268479f6-352d-4eb5-8d3e-6b412a1dc9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767449889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1767449889
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.639681929
Short name T739
Test name
Test status
Simulation time 5822658988 ps
CPU time 12.77 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:43:35 PM PDT 24
Peak memory 201908 kb
Host smart-86b2bc63-4bf0-4d86-97b2-090641162df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639681929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.639681929
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.610521724
Short name T593
Test name
Test status
Simulation time 165490829023 ps
CPU time 389.35 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:50:01 PM PDT 24
Peak memory 202128 kb
Host smart-790294dd-d8d2-4cae-b98c-471f2e890714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610521724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
610521724
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2091729473
Short name T673
Test name
Test status
Simulation time 435780115 ps
CPU time 0.84 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:22 PM PDT 24
Peak memory 201940 kb
Host smart-17dc59d6-6a35-43b6-a047-545e4838bf3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091729473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2091729473
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3296291991
Short name T290
Test name
Test status
Simulation time 370659753206 ps
CPU time 151 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:46:04 PM PDT 24
Peak memory 202060 kb
Host smart-fa2870cd-1bc1-4082-b850-a95fa559af84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296291991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3296291991
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.143838985
Short name T261
Test name
Test status
Simulation time 181254434083 ps
CPU time 187.77 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:46:31 PM PDT 24
Peak memory 202120 kb
Host smart-8f4fd6cf-bc9b-4965-bbcb-ee91041aa337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143838985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.143838985
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.167436600
Short name T259
Test name
Test status
Simulation time 162307708479 ps
CPU time 101.74 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:44:55 PM PDT 24
Peak memory 202128 kb
Host smart-ea5ff846-7b1c-4fea-84d6-70ce6ec80e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167436600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.167436600
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2824364201
Short name T616
Test name
Test status
Simulation time 330366037848 ps
CPU time 736.39 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 05:55:36 PM PDT 24
Peak memory 202128 kb
Host smart-48d28ffb-4074-4264-a498-5dc80ca67e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824364201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2824364201
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3233214221
Short name T139
Test name
Test status
Simulation time 496186814398 ps
CPU time 1035.21 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 06:00:34 PM PDT 24
Peak memory 202100 kb
Host smart-df295644-eec5-46a3-a4d2-ac98a91fdaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233214221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3233214221
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1887547182
Short name T681
Test name
Test status
Simulation time 334296827767 ps
CPU time 191.32 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:46:36 PM PDT 24
Peak memory 202112 kb
Host smart-ca90ed2d-a533-4a32-984a-ced11c7e93fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887547182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1887547182
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1381504749
Short name T251
Test name
Test status
Simulation time 355162740352 ps
CPU time 250.69 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:47:33 PM PDT 24
Peak memory 202096 kb
Host smart-480dbd29-4de6-4878-9153-bf7f65f2557e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381504749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1381504749
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3328110901
Short name T451
Test name
Test status
Simulation time 408646478702 ps
CPU time 846.12 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:57:26 PM PDT 24
Peak memory 202096 kb
Host smart-ea5fbdea-423f-4487-9734-f43a41495063
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328110901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3328110901
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4129526664
Short name T47
Test name
Test status
Simulation time 114678663069 ps
CPU time 475.35 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 202364 kb
Host smart-1a185855-501b-4e9b-8b53-79979621225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129526664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4129526664
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1570171370
Short name T461
Test name
Test status
Simulation time 32946240391 ps
CPU time 12.12 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:42 PM PDT 24
Peak memory 201920 kb
Host smart-a05a643d-9850-4233-96a2-a5cbd2380440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570171370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1570171370
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2883651017
Short name T433
Test name
Test status
Simulation time 3930399556 ps
CPU time 8.86 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:43:31 PM PDT 24
Peak memory 201924 kb
Host smart-10b51aad-0d1f-496e-bc05-2ea654e4e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883651017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2883651017
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2681264442
Short name T682
Test name
Test status
Simulation time 5726226778 ps
CPU time 7.57 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 201908 kb
Host smart-280816e8-0b7d-43b0-b0bf-e7e83c7be3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681264442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2681264442
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3786287954
Short name T133
Test name
Test status
Simulation time 509815970379 ps
CPU time 273.26 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 202096 kb
Host smart-311d7d71-4887-486e-b7ea-e937a18e3e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786287954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3786287954
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3919635962
Short name T323
Test name
Test status
Simulation time 142722502175 ps
CPU time 12.46 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:43:45 PM PDT 24
Peak memory 210516 kb
Host smart-4ed2192f-1923-4a1e-83dd-1fa862e4e7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919635962 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3919635962
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1157976347
Short name T669
Test name
Test status
Simulation time 516164865 ps
CPU time 1.25 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:43:15 PM PDT 24
Peak memory 201960 kb
Host smart-74faea61-b38c-4d2b-a913-de85f3ac9c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157976347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1157976347
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2604972699
Short name T272
Test name
Test status
Simulation time 324633950483 ps
CPU time 719.52 seconds
Started Aug 18 05:43:16 PM PDT 24
Finished Aug 18 05:55:16 PM PDT 24
Peak memory 202056 kb
Host smart-5dc126ce-e76f-4dbe-a9d3-98035fb35924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604972699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2604972699
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3315500283
Short name T368
Test name
Test status
Simulation time 327699943953 ps
CPU time 194.89 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:46:28 PM PDT 24
Peak memory 202096 kb
Host smart-e014035b-e000-432a-ad4d-0df86d8da6f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315500283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3315500283
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2395620252
Short name T499
Test name
Test status
Simulation time 328377362561 ps
CPU time 732.41 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:55:38 PM PDT 24
Peak memory 202056 kb
Host smart-33535264-96d6-413b-80d6-d9c5a5c64911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395620252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2395620252
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3511201643
Short name T531
Test name
Test status
Simulation time 499888954231 ps
CPU time 1197.53 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 06:03:13 PM PDT 24
Peak memory 202108 kb
Host smart-8e6ccb41-9fe8-4819-b14d-b8d423b5cd3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511201643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3511201643
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1052105406
Short name T749
Test name
Test status
Simulation time 603451054948 ps
CPU time 1437.61 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 06:07:17 PM PDT 24
Peak memory 202056 kb
Host smart-be051eba-3d53-4ee1-a110-4d115f6ec25d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052105406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1052105406
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1055384884
Short name T336
Test name
Test status
Simulation time 101724269814 ps
CPU time 398.86 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:50:01 PM PDT 24
Peak memory 202368 kb
Host smart-30f5a643-3327-4957-9765-e5e054442e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055384884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1055384884
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.451353084
Short name T432
Test name
Test status
Simulation time 46067796194 ps
CPU time 31.23 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:53 PM PDT 24
Peak memory 201940 kb
Host smart-69818b13-5dac-4dc6-9106-be10d145143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451353084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.451353084
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4291437870
Short name T357
Test name
Test status
Simulation time 2646222666 ps
CPU time 3.74 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:43:24 PM PDT 24
Peak memory 201920 kb
Host smart-93761500-baa4-4c4d-bff8-0a15f6e84862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291437870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4291437870
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.703202636
Short name T410
Test name
Test status
Simulation time 5789080089 ps
CPU time 6.56 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:43:26 PM PDT 24
Peak memory 201924 kb
Host smart-b9291e1e-8c0b-4b00-b3a1-bacee9cf4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703202636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.703202636
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4105882493
Short name T614
Test name
Test status
Simulation time 675521360575 ps
CPU time 794.91 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 202092 kb
Host smart-93822286-802b-4461-b889-16f63e452171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105882493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4105882493
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3055086743
Short name T20
Test name
Test status
Simulation time 45290261235 ps
CPU time 7.45 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 202184 kb
Host smart-9dc69fff-ffb5-4088-a583-773d995ac653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055086743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3055086743
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3708639201
Short name T604
Test name
Test status
Simulation time 424216292 ps
CPU time 0.73 seconds
Started Aug 18 05:43:15 PM PDT 24
Finished Aug 18 05:43:16 PM PDT 24
Peak memory 201944 kb
Host smart-e1772e34-c44f-4403-9c04-f3ed75b575dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708639201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3708639201
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2150615269
Short name T330
Test name
Test status
Simulation time 336482415963 ps
CPU time 245.71 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 05:47:26 PM PDT 24
Peak memory 202128 kb
Host smart-18515f3c-c417-4379-97e8-bacf9bec5a58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150615269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2150615269
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.771238857
Short name T671
Test name
Test status
Simulation time 503597053697 ps
CPU time 298.54 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 202100 kb
Host smart-97675dbf-d33c-49c1-9d07-3486bbbb661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771238857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.771238857
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2937952180
Short name T409
Test name
Test status
Simulation time 500412974913 ps
CPU time 543.38 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 202160 kb
Host smart-cbd7f35b-0e05-41b5-91af-392da90193da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937952180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2937952180
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1888221114
Short name T484
Test name
Test status
Simulation time 327449644951 ps
CPU time 744.22 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:55:47 PM PDT 24
Peak memory 202120 kb
Host smart-a51d3285-2893-4dc9-a869-aef6e5d49f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888221114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1888221114
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3826449336
Short name T778
Test name
Test status
Simulation time 163047694357 ps
CPU time 380.52 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:49:25 PM PDT 24
Peak memory 202092 kb
Host smart-40e7fb22-1fad-4bf7-a28c-c677a201435d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826449336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3826449336
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.753643338
Short name T325
Test name
Test status
Simulation time 568212425588 ps
CPU time 1412.16 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 06:06:58 PM PDT 24
Peak memory 202084 kb
Host smart-c735dc71-576b-40f8-8aba-79a62661cdf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753643338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.753643338
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.62015940
Short name T435
Test name
Test status
Simulation time 603543579993 ps
CPU time 222.44 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 202072 kb
Host smart-0c25246d-4479-40f1-bec3-095551340709
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62015940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
dc_ctrl_filters_wakeup_fixed.62015940
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1697903526
Short name T186
Test name
Test status
Simulation time 122874795959 ps
CPU time 653.84 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:54:19 PM PDT 24
Peak memory 202344 kb
Host smart-f6c3d936-fb24-41c7-9912-27ba44545ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697903526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1697903526
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2234400235
Short name T534
Test name
Test status
Simulation time 36561646297 ps
CPU time 23.35 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:53 PM PDT 24
Peak memory 201936 kb
Host smart-6b1d71e4-399e-4639-9214-a949736f3dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234400235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2234400235
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2353693868
Short name T625
Test name
Test status
Simulation time 2917956495 ps
CPU time 7.18 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:43:47 PM PDT 24
Peak memory 201940 kb
Host smart-2fca6fc7-595d-4346-bad9-3ec2324bb958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353693868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2353693868
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2448119489
Short name T679
Test name
Test status
Simulation time 5775472471 ps
CPU time 3.89 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:25 PM PDT 24
Peak memory 201840 kb
Host smart-14859aad-1e53-4927-ba11-7bf2b05739f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448119489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2448119489
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.532806838
Short name T549
Test name
Test status
Simulation time 329050419 ps
CPU time 0.78 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:43:25 PM PDT 24
Peak memory 201960 kb
Host smart-054915c2-98d6-4d4a-9c87-d4a1bad557a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532806838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.532806838
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1295471754
Short name T55
Test name
Test status
Simulation time 504479038370 ps
CPU time 472.55 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 202100 kb
Host smart-e8406543-7853-4b18-8caf-dce9a4c23c08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295471754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1295471754
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3157157738
Short name T269
Test name
Test status
Simulation time 526125105318 ps
CPU time 593.92 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:53:24 PM PDT 24
Peak memory 202140 kb
Host smart-d679cf0f-1b28-4d76-a8f7-4ce42ecb80b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157157738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3157157738
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1423232712
Short name T731
Test name
Test status
Simulation time 165366430943 ps
CPU time 200.95 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 202140 kb
Host smart-e8b8855c-db1b-40c6-b6eb-3e6d6f9ce97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423232712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1423232712
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3260015058
Short name T635
Test name
Test status
Simulation time 165044401542 ps
CPU time 190.18 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:46:28 PM PDT 24
Peak memory 202092 kb
Host smart-de0a6d61-d54e-47e0-956c-c0f10ec85404
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260015058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3260015058
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.261714790
Short name T147
Test name
Test status
Simulation time 160233804937 ps
CPU time 365.87 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:49:31 PM PDT 24
Peak memory 202064 kb
Host smart-57c276d8-f419-45ab-aec0-7ff049e1135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261714790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.261714790
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.339468772
Short name T420
Test name
Test status
Simulation time 334950212568 ps
CPU time 399.58 seconds
Started Aug 18 05:43:20 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 202072 kb
Host smart-d1055d57-d5dc-40a4-b32f-96f794ea8cde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339468772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.339468772
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1802214117
Short name T223
Test name
Test status
Simulation time 177000382567 ps
CPU time 404.35 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:50:08 PM PDT 24
Peak memory 202100 kb
Host smart-4bf0cfc3-152b-47ac-902b-ba026083685d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802214117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1802214117
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1757176219
Short name T751
Test name
Test status
Simulation time 402171300096 ps
CPU time 880.44 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:58:10 PM PDT 24
Peak memory 202092 kb
Host smart-3e292887-0a93-445b-a2fa-db500d79884c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757176219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1757176219
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3239945292
Short name T334
Test name
Test status
Simulation time 97736788285 ps
CPU time 399.4 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 202304 kb
Host smart-1ecce0ce-698b-410f-bbe1-50cb7f19488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239945292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3239945292
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1311901814
Short name T685
Test name
Test status
Simulation time 40850073965 ps
CPU time 22.9 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:52 PM PDT 24
Peak memory 201940 kb
Host smart-423058ba-6b80-4ebe-8d7d-d5d0253930d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311901814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1311901814
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3384839890
Short name T609
Test name
Test status
Simulation time 4812087183 ps
CPU time 3.51 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:43:28 PM PDT 24
Peak memory 201864 kb
Host smart-cfd01fee-b766-447f-962e-228ce0dfe908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384839890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3384839890
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.505818436
Short name T621
Test name
Test status
Simulation time 5649446121 ps
CPU time 5.27 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:43:31 PM PDT 24
Peak memory 202128 kb
Host smart-f0fbc234-369d-4c8f-a527-9f23c5a192b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505818436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.505818436
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3576669881
Short name T592
Test name
Test status
Simulation time 160853433609 ps
CPU time 80.14 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:44:54 PM PDT 24
Peak memory 201972 kb
Host smart-60d1102b-0e1a-48a5-af2c-835e484855f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576669881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3576669881
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2836733339
Short name T305
Test name
Test status
Simulation time 19855189154 ps
CPU time 25.91 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:44:05 PM PDT 24
Peak memory 217948 kb
Host smart-02aae057-5862-4fcc-a903-26c01ccad5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836733339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2836733339
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3610574110
Short name T728
Test name
Test status
Simulation time 386684160 ps
CPU time 1.12 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:43:42 PM PDT 24
Peak memory 201932 kb
Host smart-fa303dd3-90e4-4d3c-8fd2-5749915ac71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610574110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3610574110
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2163211866
Short name T526
Test name
Test status
Simulation time 168298023718 ps
CPU time 392.05 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 202096 kb
Host smart-420bfc0f-d7bc-4692-bd04-c7200df34b0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163211866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2163211866
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2195495286
Short name T693
Test name
Test status
Simulation time 155676414546 ps
CPU time 178.72 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:46:32 PM PDT 24
Peak memory 202160 kb
Host smart-e8742c01-1670-4d8a-b718-e6f13484ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195495286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2195495286
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.545981035
Short name T701
Test name
Test status
Simulation time 489677833556 ps
CPU time 303.06 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 202092 kb
Host smart-c26df513-321f-48bc-a451-5803cc3a28de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=545981035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.545981035
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3299222772
Short name T760
Test name
Test status
Simulation time 180738161961 ps
CPU time 168.58 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 05:46:24 PM PDT 24
Peak memory 202140 kb
Host smart-34204543-b43d-4faf-9a15-05242b7b140a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299222772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3299222772
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2354782357
Short name T86
Test name
Test status
Simulation time 198276393803 ps
CPU time 341.56 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:49:06 PM PDT 24
Peak memory 202092 kb
Host smart-b3e2bebc-68d7-4ce8-b5ce-64dbec8bf86b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354782357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2354782357
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2110526392
Short name T181
Test name
Test status
Simulation time 93059655181 ps
CPU time 416.18 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 202264 kb
Host smart-1b160752-7bbb-40ce-b094-faadb417e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110526392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2110526392
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1869489833
Short name T395
Test name
Test status
Simulation time 32049123250 ps
CPU time 19.79 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:43:59 PM PDT 24
Peak memory 201932 kb
Host smart-79437090-bc33-463f-87ef-ce307a72c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869489833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1869489833
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4007281569
Short name T748
Test name
Test status
Simulation time 5022297540 ps
CPU time 11.13 seconds
Started Aug 18 05:43:22 PM PDT 24
Finished Aug 18 05:43:33 PM PDT 24
Peak memory 201924 kb
Host smart-18a6be38-0099-4c62-8f21-ffa9ee8d2f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007281569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4007281569
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3831083390
Short name T453
Test name
Test status
Simulation time 5975169419 ps
CPU time 13.68 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:43:38 PM PDT 24
Peak memory 201940 kb
Host smart-2d2c1385-7d40-4e93-b2ec-120c1756ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831083390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3831083390
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4216806474
Short name T200
Test name
Test status
Simulation time 329690190439 ps
CPU time 660.52 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:54:35 PM PDT 24
Peak memory 202096 kb
Host smart-c9b1c932-4444-4848-a98f-0f9322e88af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216806474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4216806474
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2434020338
Short name T564
Test name
Test status
Simulation time 520788552 ps
CPU time 1.87 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:38 PM PDT 24
Peak memory 201960 kb
Host smart-fd03bf47-77df-40aa-b109-b5c8885eb683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434020338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2434020338
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2053696573
Short name T253
Test name
Test status
Simulation time 156470037429 ps
CPU time 95.66 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 05:44:55 PM PDT 24
Peak memory 202012 kb
Host smart-d199a10b-589a-4652-ad8e-31047fb02e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053696573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2053696573
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3509311676
Short name T124
Test name
Test status
Simulation time 166417446730 ps
CPU time 413.61 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:50:23 PM PDT 24
Peak memory 202036 kb
Host smart-f25c3926-3af3-4693-a351-a351b2ecbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509311676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3509311676
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1401526544
Short name T8
Test name
Test status
Simulation time 164220172848 ps
CPU time 103.7 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:45:13 PM PDT 24
Peak memory 202144 kb
Host smart-a61398c5-0e2b-4903-8dfc-36706ec7d320
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401526544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1401526544
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1021700309
Short name T691
Test name
Test status
Simulation time 325348082084 ps
CPU time 677.32 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:54:43 PM PDT 24
Peak memory 202100 kb
Host smart-5d024b41-9bff-4ac8-b892-bf10b9039229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021700309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1021700309
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.567633791
Short name T536
Test name
Test status
Simulation time 484523519442 ps
CPU time 1048.54 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 06:00:51 PM PDT 24
Peak memory 202100 kb
Host smart-e27cd2e2-0016-49ee-a823-782dd595cbaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=567633791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.567633791
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2182316854
Short name T304
Test name
Test status
Simulation time 542669967743 ps
CPU time 317.51 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:48:43 PM PDT 24
Peak memory 202036 kb
Host smart-fc5f9314-86c6-4c15-996d-40e465a931ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182316854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2182316854
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.289832025
Short name T557
Test name
Test status
Simulation time 402127838098 ps
CPU time 875.83 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:58:01 PM PDT 24
Peak memory 202108 kb
Host smart-e45aabf3-d9e3-49b6-902c-db1bf21b5079
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289832025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.289832025
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3561870716
Short name T185
Test name
Test status
Simulation time 102105864057 ps
CPU time 566 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:53:08 PM PDT 24
Peak memory 202356 kb
Host smart-8b220a5e-9e5a-4719-a9a7-bf44e17c4429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561870716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3561870716
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2057620968
Short name T710
Test name
Test status
Simulation time 22188211290 ps
CPU time 22.66 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:43:46 PM PDT 24
Peak memory 201944 kb
Host smart-a8ed6e3b-ff07-4aa3-8ef6-13af64be270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057620968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2057620968
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1468094706
Short name T362
Test name
Test status
Simulation time 5519408788 ps
CPU time 9.99 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 201908 kb
Host smart-17a1f309-995b-4df9-a47e-ad6d61475ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468094706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1468094706
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2050781171
Short name T753
Test name
Test status
Simulation time 5854601241 ps
CPU time 7.81 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:43:39 PM PDT 24
Peak memory 201936 kb
Host smart-0255b6bb-6dc5-4df3-8744-08853dc86b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050781171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2050781171
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3063526497
Short name T195
Test name
Test status
Simulation time 355851404202 ps
CPU time 404.26 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:50:14 PM PDT 24
Peak memory 201996 kb
Host smart-8f2bc7f7-c86d-40c3-9bd7-7f1c2d0ebbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063526497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3063526497
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.879903334
Short name T23
Test name
Test status
Simulation time 7172199711 ps
CPU time 10.7 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 210504 kb
Host smart-6c636f94-ce31-4bbd-b1bc-cdeb654f1688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879903334 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.879903334
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3893533453
Short name T773
Test name
Test status
Simulation time 410740803 ps
CPU time 0.7 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:42:46 PM PDT 24
Peak memory 201964 kb
Host smart-31d1f531-6f64-4d6c-87be-3b14d8a5cf29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893533453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3893533453
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2308915369
Short name T265
Test name
Test status
Simulation time 363944873231 ps
CPU time 181.38 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:45:40 PM PDT 24
Peak memory 202128 kb
Host smart-499de3ab-0545-4606-a9f7-8a0069e90dea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308915369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2308915369
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2650613818
Short name T148
Test name
Test status
Simulation time 165651281375 ps
CPU time 191.77 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:45:50 PM PDT 24
Peak memory 202108 kb
Host smart-fffbdf9f-43c1-42e0-ae0e-94bc58e8d77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650613818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2650613818
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1015714659
Short name T568
Test name
Test status
Simulation time 159861586910 ps
CPU time 95.11 seconds
Started Aug 18 05:42:54 PM PDT 24
Finished Aug 18 05:44:29 PM PDT 24
Peak memory 202140 kb
Host smart-55afdcc4-32dc-4634-a0c5-4b5147ffba56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015714659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1015714659
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1579093371
Short name T558
Test name
Test status
Simulation time 325041181446 ps
CPU time 357.28 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:48:40 PM PDT 24
Peak memory 202100 kb
Host smart-981868af-98d6-400e-9b34-56df30f5ea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579093371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1579093371
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3304878505
Short name T704
Test name
Test status
Simulation time 323552423935 ps
CPU time 352.43 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:48:54 PM PDT 24
Peak memory 202092 kb
Host smart-43207c40-8cc4-4d75-b035-d273cb440cfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304878505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3304878505
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4120516243
Short name T173
Test name
Test status
Simulation time 538006993957 ps
CPU time 331.01 seconds
Started Aug 18 05:42:34 PM PDT 24
Finished Aug 18 05:48:05 PM PDT 24
Peak memory 202072 kb
Host smart-aafb8d68-31e0-4303-af9e-45245f345af7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120516243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4120516243
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.833784494
Short name T580
Test name
Test status
Simulation time 612975099394 ps
CPU time 115.19 seconds
Started Aug 18 05:42:33 PM PDT 24
Finished Aug 18 05:44:28 PM PDT 24
Peak memory 202108 kb
Host smart-215f67b8-0706-4f02-95b6-6d9f92761f62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833784494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.833784494
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4089209308
Short name T26
Test name
Test status
Simulation time 132378576515 ps
CPU time 657.84 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:53:40 PM PDT 24
Peak memory 202380 kb
Host smart-278cc9ca-eb6b-4be2-b9df-27b7b182acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089209308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4089209308
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4230631668
Short name T472
Test name
Test status
Simulation time 28459510605 ps
CPU time 17.24 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:42:54 PM PDT 24
Peak memory 201936 kb
Host smart-0d854d19-4e5f-4682-a304-ed17fe40b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230631668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4230631668
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3680457172
Short name T506
Test name
Test status
Simulation time 4463199345 ps
CPU time 11.65 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:42:54 PM PDT 24
Peak memory 201932 kb
Host smart-7e4bae03-2097-4268-9d4c-9a732cbf398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680457172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3680457172
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4033404615
Short name T84
Test name
Test status
Simulation time 4123865941 ps
CPU time 2.18 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:42:45 PM PDT 24
Peak memory 217452 kb
Host smart-aa580ac2-1fb1-45ac-b2a5-353872971cb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033404615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4033404615
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2273936148
Short name T583
Test name
Test status
Simulation time 5979031029 ps
CPU time 7.61 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:42:52 PM PDT 24
Peak memory 201908 kb
Host smart-92754734-a586-4840-8b9e-7a8793cfc065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273936148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2273936148
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1609197837
Short name T770
Test name
Test status
Simulation time 361165385942 ps
CPU time 846.01 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 202068 kb
Host smart-0f29963d-6822-4d2e-ad23-5071e94d3df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609197837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1609197837
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4086384783
Short name T17
Test name
Test status
Simulation time 11045360374 ps
CPU time 21.01 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:43:13 PM PDT 24
Peak memory 210660 kb
Host smart-6ad2c1da-bd96-4c8c-a266-39d719d2ae2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086384783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4086384783
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.396074612
Short name T408
Test name
Test status
Simulation time 321678492 ps
CPU time 0.73 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:37 PM PDT 24
Peak memory 201960 kb
Host smart-f1a5dd3d-0703-43f9-8a66-1258505559f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396074612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.396074612
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2581611671
Short name T785
Test name
Test status
Simulation time 174164630637 ps
CPU time 63.4 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:44:35 PM PDT 24
Peak memory 202084 kb
Host smart-cb242397-e833-4647-9593-e8995f88d4ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581611671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2581611671
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1676319169
Short name T599
Test name
Test status
Simulation time 324473774875 ps
CPU time 362.4 seconds
Started Aug 18 05:43:43 PM PDT 24
Finished Aug 18 05:49:46 PM PDT 24
Peak memory 201988 kb
Host smart-d01ddd80-f005-4311-b7b0-34b72f26333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676319169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1676319169
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1280791487
Short name T132
Test name
Test status
Simulation time 501649358811 ps
CPU time 310.25 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:48:49 PM PDT 24
Peak memory 202116 kb
Host smart-1ecf33c9-412c-451f-a24f-69c7dab33646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280791487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1280791487
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1408459403
Short name T421
Test name
Test status
Simulation time 330664325888 ps
CPU time 382.78 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 202156 kb
Host smart-8b5cf630-3056-49e4-8b32-56e0dcc62e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408459403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1408459403
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.4207235479
Short name T665
Test name
Test status
Simulation time 162848445837 ps
CPU time 198.87 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 202052 kb
Host smart-0d91fb12-196b-44f7-98dc-43afe1c0be82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207235479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4207235479
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.257058028
Short name T165
Test name
Test status
Simulation time 164435172573 ps
CPU time 99.73 seconds
Started Aug 18 05:43:28 PM PDT 24
Finished Aug 18 05:45:08 PM PDT 24
Peak memory 202068 kb
Host smart-015c853b-828c-46fc-881d-61549c853daa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257058028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.257058028
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2622639361
Short name T310
Test name
Test status
Simulation time 473405210762 ps
CPU time 1075.09 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 06:01:30 PM PDT 24
Peak memory 201996 kb
Host smart-69198774-6454-4876-b610-7e62647727fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622639361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2622639361
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1318631122
Short name T42
Test name
Test status
Simulation time 76800781121 ps
CPU time 280.55 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 202348 kb
Host smart-db1067e1-10a5-4065-888c-04171a9f83ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318631122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1318631122
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3888226623
Short name T668
Test name
Test status
Simulation time 46380827523 ps
CPU time 101.71 seconds
Started Aug 18 05:43:29 PM PDT 24
Finished Aug 18 05:45:11 PM PDT 24
Peak memory 201892 kb
Host smart-a1c61553-77d8-46c9-874d-803c45d467cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888226623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3888226623
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3079325984
Short name T381
Test name
Test status
Simulation time 4563344767 ps
CPU time 4.16 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:43:35 PM PDT 24
Peak memory 201920 kb
Host smart-b2735e82-b6b8-41f3-b5cd-d2ab29539ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079325984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3079325984
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1968459836
Short name T687
Test name
Test status
Simulation time 5830874527 ps
CPU time 11.75 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:43:31 PM PDT 24
Peak memory 201936 kb
Host smart-5a3cf14d-c37a-4393-80b9-15075ce33a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968459836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1968459836
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.745540785
Short name T555
Test name
Test status
Simulation time 44047568685 ps
CPU time 27.66 seconds
Started Aug 18 05:43:37 PM PDT 24
Finished Aug 18 05:44:05 PM PDT 24
Peak memory 201936 kb
Host smart-95868f6a-f16d-4aa9-b407-073aa217674b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745540785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
745540785
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1336035252
Short name T21
Test name
Test status
Simulation time 166601404681 ps
CPU time 11.15 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:48 PM PDT 24
Peak memory 202108 kb
Host smart-f2917092-bfe3-4843-a8cc-472100dd2c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336035252 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1336035252
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2432897275
Short name T481
Test name
Test status
Simulation time 452436059 ps
CPU time 1.56 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:43:42 PM PDT 24
Peak memory 201960 kb
Host smart-4d08da26-d3a0-48fa-8180-8c1ce457a347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432897275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2432897275
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1961651301
Short name T605
Test name
Test status
Simulation time 164142333545 ps
CPU time 102.38 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:45:16 PM PDT 24
Peak memory 202052 kb
Host smart-d523ba6c-f45e-4496-9e89-91a796ab4471
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961651301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1961651301
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3013670639
Short name T620
Test name
Test status
Simulation time 192126745455 ps
CPU time 450.99 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 202104 kb
Host smart-fc47670c-4ef7-4598-abba-4e8af4830346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013670639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3013670639
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.449640178
Short name T752
Test name
Test status
Simulation time 164396015996 ps
CPU time 101.67 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:45:16 PM PDT 24
Peak memory 202172 kb
Host smart-fdd0af86-9f3b-4fe4-99b9-d7d16df5e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449640178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.449640178
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2273960095
Short name T146
Test name
Test status
Simulation time 165025136069 ps
CPU time 185.61 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 05:46:41 PM PDT 24
Peak memory 202136 kb
Host smart-b3cac5d5-9e01-45b5-9532-738b8294e83d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273960095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2273960095
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1748319304
Short name T798
Test name
Test status
Simulation time 161141148229 ps
CPU time 89.18 seconds
Started Aug 18 05:43:25 PM PDT 24
Finished Aug 18 05:44:55 PM PDT 24
Peak memory 202028 kb
Host smart-f1a8c660-3683-4335-95bb-d0a3da46f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748319304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1748319304
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1800407979
Short name T473
Test name
Test status
Simulation time 159241756045 ps
CPU time 66.51 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 202132 kb
Host smart-a152e79d-6aed-401e-b0a8-ddb46f9a0483
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800407979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1800407979
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2378194331
Short name T282
Test name
Test status
Simulation time 345485540181 ps
CPU time 851.61 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:57:57 PM PDT 24
Peak memory 202008 kb
Host smart-08feac16-f9c2-46b1-8c74-cf66adbae99f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378194331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2378194331
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3403590149
Short name T501
Test name
Test status
Simulation time 202056464005 ps
CPU time 78.96 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:45:04 PM PDT 24
Peak memory 202060 kb
Host smart-986582b3-157f-44fd-a48b-26eb377ff121
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403590149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3403590149
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1919612616
Short name T458
Test name
Test status
Simulation time 88540971733 ps
CPU time 322.99 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:49:03 PM PDT 24
Peak memory 202276 kb
Host smart-83431675-2fa1-49f4-bb64-f35c7931f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919612616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1919612616
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2024073144
Short name T574
Test name
Test status
Simulation time 30527204025 ps
CPU time 72.05 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:44:44 PM PDT 24
Peak memory 201928 kb
Host smart-7476aeab-c67e-4eba-8747-b7f28c9ab395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024073144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2024073144
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.988790743
Short name T423
Test name
Test status
Simulation time 4589511224 ps
CPU time 6.18 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:43:39 PM PDT 24
Peak memory 201908 kb
Host smart-5eb36c21-73a9-4798-a5cf-4dee2023d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988790743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.988790743
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3661633480
Short name T725
Test name
Test status
Simulation time 5789391393 ps
CPU time 13.16 seconds
Started Aug 18 05:43:30 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 201932 kb
Host smart-39081a02-9f27-46ef-9db5-7935409aba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661633480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3661633480
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3447818873
Short name T772
Test name
Test status
Simulation time 15014306300 ps
CPU time 31.09 seconds
Started Aug 18 05:43:37 PM PDT 24
Finished Aug 18 05:44:08 PM PDT 24
Peak memory 210556 kb
Host smart-535cf1ed-1a72-4913-833c-25f48bb082a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447818873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3447818873
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.431509491
Short name T85
Test name
Test status
Simulation time 469084314 ps
CPU time 0.73 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:37 PM PDT 24
Peak memory 201844 kb
Host smart-f328c391-f97c-4f7c-8135-616199cb125a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431509491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.431509491
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1323328647
Short name T284
Test name
Test status
Simulation time 169193095517 ps
CPU time 203.87 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:46:58 PM PDT 24
Peak memory 202012 kb
Host smart-8cc45a06-9580-401f-b007-648303692c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323328647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1323328647
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1707542020
Short name T294
Test name
Test status
Simulation time 333064490669 ps
CPU time 777.59 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:56:30 PM PDT 24
Peak memory 202008 kb
Host smart-a240918e-cf6d-4395-823e-5dc86e64bcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707542020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1707542020
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1447369268
Short name T399
Test name
Test status
Simulation time 327893146380 ps
CPU time 781.52 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:56:28 PM PDT 24
Peak memory 202164 kb
Host smart-57703950-c69e-43ad-b581-2d6cf191c3f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447369268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1447369268
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.170641678
Short name T517
Test name
Test status
Simulation time 162715600293 ps
CPU time 338.92 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:49:20 PM PDT 24
Peak memory 201996 kb
Host smart-653899ed-cb06-484f-b288-f66d9e553ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170641678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.170641678
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1023352899
Short name T581
Test name
Test status
Simulation time 332402304640 ps
CPU time 380.4 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 202092 kb
Host smart-bc3c897e-7092-4965-821e-95d728db4f3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023352899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1023352899
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.370751652
Short name T309
Test name
Test status
Simulation time 177304762960 ps
CPU time 396.38 seconds
Started Aug 18 05:43:24 PM PDT 24
Finished Aug 18 05:50:01 PM PDT 24
Peak memory 202124 kb
Host smart-cea848b3-0766-40c1-9807-cf3ce6a69bb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370751652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.370751652
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3917213010
Short name T402
Test name
Test status
Simulation time 400793037134 ps
CPU time 248.17 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 202156 kb
Host smart-d435e1e1-2f64-4ab1-b27c-be08577f4cf4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917213010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3917213010
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3273195297
Short name T587
Test name
Test status
Simulation time 80126198668 ps
CPU time 260 seconds
Started Aug 18 05:43:42 PM PDT 24
Finished Aug 18 05:48:02 PM PDT 24
Peak memory 202260 kb
Host smart-6eec5fde-2036-4550-8474-0f8a9902baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273195297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3273195297
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2459723418
Short name T606
Test name
Test status
Simulation time 40562821010 ps
CPU time 24.96 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:44:09 PM PDT 24
Peak memory 201832 kb
Host smart-f1fa82ee-099e-4c44-90ef-07b2a6c5fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459723418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2459723418
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.362775722
Short name T498
Test name
Test status
Simulation time 2921774641 ps
CPU time 2.32 seconds
Started Aug 18 05:43:27 PM PDT 24
Finished Aug 18 05:43:30 PM PDT 24
Peak memory 201888 kb
Host smart-e23b520f-ae57-411f-a8a8-1d53787bd225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362775722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.362775722
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1546139624
Short name T425
Test name
Test status
Simulation time 5860449724 ps
CPU time 15.13 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:43:57 PM PDT 24
Peak memory 201868 kb
Host smart-a8a21e3b-f3b0-4661-b633-d0ce26ff783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546139624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1546139624
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3368403771
Short name T118
Test name
Test status
Simulation time 168966587343 ps
CPU time 378.11 seconds
Started Aug 18 05:43:27 PM PDT 24
Finished Aug 18 05:49:45 PM PDT 24
Peak memory 202136 kb
Host smart-53970bfc-3c9c-4dbb-86d1-6fcea8f911b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368403771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3368403771
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.308344935
Short name T615
Test name
Test status
Simulation time 5276511947 ps
CPU time 6.38 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:43:41 PM PDT 24
Peak memory 201940 kb
Host smart-4d6e819d-cf28-461b-b5b2-411a855ed2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308344935 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.308344935
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1724408593
Short name T643
Test name
Test status
Simulation time 423110017 ps
CPU time 0.9 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 201944 kb
Host smart-768de234-83cd-4e7f-bb07-48ca952d24c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724408593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1724408593
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1185826652
Short name T322
Test name
Test status
Simulation time 404064058857 ps
CPU time 814.66 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:57:08 PM PDT 24
Peak memory 202104 kb
Host smart-6eb39173-e1d7-4ff3-991d-0621e43ae452
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185826652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1185826652
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.830488692
Short name T246
Test name
Test status
Simulation time 164013064166 ps
CPU time 332.79 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:48:56 PM PDT 24
Peak memory 202144 kb
Host smart-e34cb6cf-7abe-4c17-b142-addb6e2f394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830488692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.830488692
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.10852495
Short name T529
Test name
Test status
Simulation time 168125815800 ps
CPU time 336.49 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:49:02 PM PDT 24
Peak memory 202104 kb
Host smart-1a26bab4-7b3d-46dc-9f87-6f2212e044ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt
_fixed.10852495
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1016041798
Short name T445
Test name
Test status
Simulation time 162640157873 ps
CPU time 98.18 seconds
Started Aug 18 05:43:26 PM PDT 24
Finished Aug 18 05:45:04 PM PDT 24
Peak memory 202100 kb
Host smart-321ca9b7-1f1b-450f-9e2f-bce6e9be07ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016041798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1016041798
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3230797337
Short name T734
Test name
Test status
Simulation time 327853350472 ps
CPU time 354.82 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 201996 kb
Host smart-04178dee-aed8-4619-ad5c-be5e5eb4ac48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230797337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3230797337
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1004881232
Short name T493
Test name
Test status
Simulation time 188034372557 ps
CPU time 113.05 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:45:30 PM PDT 24
Peak memory 202076 kb
Host smart-b2ff166c-38a5-42bd-98be-3f441c36a4dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004881232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1004881232
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2414126777
Short name T363
Test name
Test status
Simulation time 595509795234 ps
CPU time 494.46 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:51:47 PM PDT 24
Peak memory 202100 kb
Host smart-e68dfe87-f7ff-44fa-aeaf-dad772b3178c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414126777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2414126777
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2875891459
Short name T48
Test name
Test status
Simulation time 88093615776 ps
CPU time 301.49 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:48:35 PM PDT 24
Peak memory 202348 kb
Host smart-11584964-15e8-4e88-b527-bdb02f51880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875891459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2875891459
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2828917874
Short name T354
Test name
Test status
Simulation time 22088958150 ps
CPU time 11.94 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:44:01 PM PDT 24
Peak memory 201892 kb
Host smart-fac3d2ef-0c3f-4e88-af35-15ae5556f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828917874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2828917874
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3209866212
Short name T619
Test name
Test status
Simulation time 4226251403 ps
CPU time 3.28 seconds
Started Aug 18 05:43:34 PM PDT 24
Finished Aug 18 05:43:38 PM PDT 24
Peak memory 201940 kb
Host smart-8b1d70c6-f55a-4d71-912c-a56320665e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209866212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3209866212
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1801686508
Short name T737
Test name
Test status
Simulation time 5490982616 ps
CPU time 6.62 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:43 PM PDT 24
Peak memory 201928 kb
Host smart-986207d6-b9d2-458f-a9d0-2d4d93d14a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801686508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1801686508
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2794288464
Short name T478
Test name
Test status
Simulation time 172601022373 ps
CPU time 111.54 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:45:39 PM PDT 24
Peak memory 202068 kb
Host smart-45e51172-2675-4377-9648-22cf999960ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794288464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2794288464
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.58247861
Short name T177
Test name
Test status
Simulation time 18593694530 ps
CPU time 7.87 seconds
Started Aug 18 05:43:43 PM PDT 24
Finished Aug 18 05:43:51 PM PDT 24
Peak memory 202276 kb
Host smart-aba2e552-6b4c-4045-a7dd-48a41ae7650d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58247861 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.58247861
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1410483100
Short name T666
Test name
Test status
Simulation time 312712107 ps
CPU time 0.9 seconds
Started Aug 18 05:43:37 PM PDT 24
Finished Aug 18 05:43:38 PM PDT 24
Peak memory 201920 kb
Host smart-2a696f2f-a5b1-41bc-8b34-8449a9c3698f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410483100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1410483100
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.343671497
Short name T297
Test name
Test status
Simulation time 165326887100 ps
CPU time 191.49 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 201976 kb
Host smart-ad52812e-34ca-4db1-bb5a-4cf1dc3f3c42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343671497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.343671497
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.419673791
Short name T27
Test name
Test status
Simulation time 169040558583 ps
CPU time 29.36 seconds
Started Aug 18 05:43:37 PM PDT 24
Finished Aug 18 05:44:07 PM PDT 24
Peak memory 202016 kb
Host smart-26ab4f72-d67a-4f0d-b4d3-28b4661d48ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419673791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.419673791
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3604915066
Short name T571
Test name
Test status
Simulation time 328622984118 ps
CPU time 794.94 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 202140 kb
Host smart-9b4c4140-4a1c-4f6d-96b4-640d6280d544
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604915066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3604915066
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1727966044
Short name T90
Test name
Test status
Simulation time 497947033490 ps
CPU time 1054.65 seconds
Started Aug 18 05:43:37 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 202160 kb
Host smart-fd5eed41-bded-4862-9f52-148a0a6874ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727966044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1727966044
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2486769219
Short name T548
Test name
Test status
Simulation time 489243583399 ps
CPU time 567.68 seconds
Started Aug 18 05:43:38 PM PDT 24
Finished Aug 18 05:53:06 PM PDT 24
Peak memory 202092 kb
Host smart-c9e919a1-ad31-4f71-8feb-fa169042b586
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486769219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2486769219
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2011552343
Short name T37
Test name
Test status
Simulation time 193471295196 ps
CPU time 89.93 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:45:16 PM PDT 24
Peak memory 201976 kb
Host smart-2e10dfe5-2a9d-4e27-a5b1-903b788f8494
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011552343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2011552343
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1758631495
Short name T428
Test name
Test status
Simulation time 196033234954 ps
CPU time 209.14 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:47:01 PM PDT 24
Peak memory 202032 kb
Host smart-da9db8e2-6627-414c-aaa5-c1f7f4e840e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758631495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1758631495
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.180912044
Short name T187
Test name
Test status
Simulation time 69570240303 ps
CPU time 297.1 seconds
Started Aug 18 05:43:23 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 202352 kb
Host smart-953fff37-8633-4c79-bb59-11e0b4bb04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180912044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.180912044
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1983695407
Short name T591
Test name
Test status
Simulation time 26729303770 ps
CPU time 63.98 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 201948 kb
Host smart-da20db89-0c40-491f-9a75-fa060ed5d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983695407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1983695407
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1273824115
Short name T375
Test name
Test status
Simulation time 4959062952 ps
CPU time 12.12 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 201940 kb
Host smart-b3d8c625-eac9-4bb9-a610-d1d33c546bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273824115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1273824115
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.818760236
Short name T9
Test name
Test status
Simulation time 5932037077 ps
CPU time 4.2 seconds
Started Aug 18 05:43:43 PM PDT 24
Finished Aug 18 05:43:47 PM PDT 24
Peak memory 201920 kb
Host smart-646411e9-4573-4b49-89ca-70a35e1edbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818760236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.818760236
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2247264087
Short name T280
Test name
Test status
Simulation time 495360821684 ps
CPU time 570.81 seconds
Started Aug 18 05:43:33 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 202160 kb
Host smart-0eb5f875-8996-4e5f-b05d-036456fdeae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247264087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2247264087
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2886389557
Short name T655
Test name
Test status
Simulation time 3857910353 ps
CPU time 4.48 seconds
Started Aug 18 05:43:21 PM PDT 24
Finished Aug 18 05:43:26 PM PDT 24
Peak memory 202060 kb
Host smart-e31fa269-102f-4599-8395-fae76ac68b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886389557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2886389557
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.526122328
Short name T791
Test name
Test status
Simulation time 373443640 ps
CPU time 1.48 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:43:43 PM PDT 24
Peak memory 201940 kb
Host smart-df84db1c-e44c-439c-9377-359e1bcdbf3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526122328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.526122328
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1035456431
Short name T229
Test name
Test status
Simulation time 185198836441 ps
CPU time 394.43 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 202120 kb
Host smart-7b8ad7b4-8d4c-4f8a-8b71-a5d6e1abf001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035456431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1035456431
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.540555599
Short name T503
Test name
Test status
Simulation time 487905628644 ps
CPU time 1190.73 seconds
Started Aug 18 05:43:31 PM PDT 24
Finished Aug 18 06:03:23 PM PDT 24
Peak memory 202100 kb
Host smart-dadc130a-d4e3-4d5f-ab84-f36be6684c9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540555599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.540555599
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3102865354
Short name T30
Test name
Test status
Simulation time 327471355276 ps
CPU time 194.44 seconds
Started Aug 18 05:43:32 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 202108 kb
Host smart-7d3faa38-843a-4417-b28a-a4a04e596dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102865354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3102865354
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.242888427
Short name T551
Test name
Test status
Simulation time 481866671500 ps
CPU time 160.31 seconds
Started Aug 18 05:43:42 PM PDT 24
Finished Aug 18 05:46:22 PM PDT 24
Peak memory 202084 kb
Host smart-8e1b9c51-327c-45e6-9dc5-e4be476008e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=242888427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.242888427
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2550077077
Short name T647
Test name
Test status
Simulation time 175543451478 ps
CPU time 407.08 seconds
Started Aug 18 05:43:28 PM PDT 24
Finished Aug 18 05:50:16 PM PDT 24
Peak memory 202156 kb
Host smart-ac7dffc7-5f18-4413-b4ed-0bdad469cdbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550077077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2550077077
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.932991582
Short name T764
Test name
Test status
Simulation time 196802929515 ps
CPU time 283.69 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 202076 kb
Host smart-153584c8-def1-46f6-a23d-c836d0def13e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932991582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.932991582
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2903138019
Short name T695
Test name
Test status
Simulation time 71912430382 ps
CPU time 235.88 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:47:32 PM PDT 24
Peak memory 202332 kb
Host smart-8c90c93a-c0a8-4bae-a1d4-032b4ff49078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903138019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2903138019
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2125531065
Short name T546
Test name
Test status
Simulation time 39457497441 ps
CPU time 27.15 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:44:13 PM PDT 24
Peak memory 201944 kb
Host smart-4f4a82e5-6bbc-404d-89b8-7038e7724704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125531065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2125531065
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.849442316
Short name T358
Test name
Test status
Simulation time 3993467403 ps
CPU time 3.22 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:43:48 PM PDT 24
Peak memory 201940 kb
Host smart-263267e1-8bbf-4bc8-bae1-3927ec517dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849442316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.849442316
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3158780642
Short name T784
Test name
Test status
Simulation time 6105897581 ps
CPU time 13.69 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 05:43:55 PM PDT 24
Peak memory 201908 kb
Host smart-71c80262-713f-4d20-b402-be99fbcdc589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158780642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3158780642
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4010723463
Short name T161
Test name
Test status
Simulation time 91896540425 ps
CPU time 19.89 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:44:08 PM PDT 24
Peak memory 210728 kb
Host smart-c70f53b0-0ead-40e5-9e8a-1adcf0e164ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010723463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4010723463
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1625642410
Short name T496
Test name
Test status
Simulation time 318788345 ps
CPU time 0.81 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:43:44 PM PDT 24
Peak memory 201908 kb
Host smart-37ae9b8a-44fa-46ad-b890-2d5b0e15e0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625642410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1625642410
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1288834149
Short name T659
Test name
Test status
Simulation time 184859141619 ps
CPU time 421.69 seconds
Started Aug 18 05:43:47 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 202124 kb
Host smart-3babe328-5298-470b-addd-8d9bdab0be08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288834149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1288834149
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4030231136
Short name T382
Test name
Test status
Simulation time 331192530471 ps
CPU time 163.86 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:46:21 PM PDT 24
Peak memory 202156 kb
Host smart-bd92dd10-69a9-47aa-a80e-66653e29e5fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030231136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4030231136
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.517385627
Short name T134
Test name
Test status
Simulation time 329258629055 ps
CPU time 175.62 seconds
Started Aug 18 05:43:39 PM PDT 24
Finished Aug 18 05:46:34 PM PDT 24
Peak memory 202116 kb
Host smart-e56fabd6-6775-4824-9b2c-f13d993af4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517385627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.517385627
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4293426431
Short name T776
Test name
Test status
Simulation time 163371636448 ps
CPU time 343.67 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:49:32 PM PDT 24
Peak memory 202072 kb
Host smart-6f97ce02-1196-43eb-aab6-a8959cad0e3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293426431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4293426431
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.386290200
Short name T588
Test name
Test status
Simulation time 368776599395 ps
CPU time 444.65 seconds
Started Aug 18 05:43:40 PM PDT 24
Finished Aug 18 05:51:05 PM PDT 24
Peak memory 202124 kb
Host smart-fdff2b9c-06a7-4db3-bc26-d287c908af59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386290200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.386290200
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4204084117
Short name T567
Test name
Test status
Simulation time 590676789480 ps
CPU time 1204.35 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 202056 kb
Host smart-12efae4c-f803-4c54-9df5-db1006ca768a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204084117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4204084117
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1729840520
Short name T590
Test name
Test status
Simulation time 130685940345 ps
CPU time 659.19 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:54:46 PM PDT 24
Peak memory 202356 kb
Host smart-37d15b19-5f07-4811-b38a-1aebab69d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729840520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1729840520
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2699569202
Short name T345
Test name
Test status
Simulation time 34443724514 ps
CPU time 81.57 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 05:44:57 PM PDT 24
Peak memory 201932 kb
Host smart-c3790cb6-30de-4b59-9153-5e81bae1f0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699569202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2699569202
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3178015097
Short name T656
Test name
Test status
Simulation time 4181607982 ps
CPU time 2.66 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:43:49 PM PDT 24
Peak memory 201916 kb
Host smart-03a44450-6446-4b20-857e-7bb825e6f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178015097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3178015097
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3721610561
Short name T437
Test name
Test status
Simulation time 6126100184 ps
CPU time 1.8 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:43:48 PM PDT 24
Peak memory 201892 kb
Host smart-39ca61d4-20c9-4e28-b52e-893054f8fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721610561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3721610561
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.592945959
Short name T45
Test name
Test status
Simulation time 284261794215 ps
CPU time 697.76 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:55:27 PM PDT 24
Peak memory 202316 kb
Host smart-eece5c56-4540-4cc6-b26d-a26befc99132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592945959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
592945959
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.751555568
Short name T585
Test name
Test status
Simulation time 3653411943 ps
CPU time 4.02 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:43:40 PM PDT 24
Peak memory 202048 kb
Host smart-fa2238d7-2a8b-41e4-aa2e-1175833f0638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751555568 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.751555568
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.796129365
Short name T525
Test name
Test status
Simulation time 288129187 ps
CPU time 1.35 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:43:50 PM PDT 24
Peak memory 201964 kb
Host smart-ec470cd3-de46-48a1-a60f-ac5c05b09294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796129365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.796129365
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2746774811
Short name T254
Test name
Test status
Simulation time 492312592493 ps
CPU time 322.42 seconds
Started Aug 18 05:43:43 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 202100 kb
Host smart-c7ee8d47-04be-4e8f-8a97-62c19e2bb66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746774811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2746774811
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2048459526
Short name T508
Test name
Test status
Simulation time 323672143530 ps
CPU time 359.81 seconds
Started Aug 18 05:43:36 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 202092 kb
Host smart-fe6af318-4d31-41ec-a2d5-32dad7f977c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048459526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2048459526
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1813792968
Short name T316
Test name
Test status
Simulation time 502758528056 ps
CPU time 1189.66 seconds
Started Aug 18 05:43:41 PM PDT 24
Finished Aug 18 06:03:31 PM PDT 24
Peak memory 202104 kb
Host smart-becb70e0-b62e-4aa5-a390-cadae087de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813792968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1813792968
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1239004100
Short name T505
Test name
Test status
Simulation time 492276170650 ps
CPU time 532.05 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:52:40 PM PDT 24
Peak memory 202032 kb
Host smart-3460cc21-6f82-4289-9ea6-3ebc8df4688a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239004100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1239004100
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4009367014
Short name T779
Test name
Test status
Simulation time 591751058196 ps
CPU time 1211.98 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 202084 kb
Host smart-6e4c0c4d-7f31-450e-bff3-cecfcd1d8871
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009367014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4009367014
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.704460171
Short name T387
Test name
Test status
Simulation time 401369644650 ps
CPU time 925.35 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:59:11 PM PDT 24
Peak memory 202112 kb
Host smart-3346ea35-97ca-43aa-be99-be1130f8c0b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704460171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.704460171
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1030455358
Short name T570
Test name
Test status
Simulation time 66558169677 ps
CPU time 353.61 seconds
Started Aug 18 05:43:35 PM PDT 24
Finished Aug 18 05:49:29 PM PDT 24
Peak memory 202400 kb
Host smart-517bc440-530f-43f2-abac-da156341f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030455358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1030455358
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2437158137
Short name T700
Test name
Test status
Simulation time 37635395833 ps
CPU time 18.31 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:44:05 PM PDT 24
Peak memory 201928 kb
Host smart-a04e8179-eb07-440b-9a28-095b97abb1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437158137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2437158137
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1926288312
Short name T721
Test name
Test status
Simulation time 4595230060 ps
CPU time 6.24 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:43:52 PM PDT 24
Peak memory 201936 kb
Host smart-f6bd4a17-4e4c-4e9a-878d-43062cab58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926288312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1926288312
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1318973943
Short name T618
Test name
Test status
Simulation time 5679441844 ps
CPU time 13.24 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:43:58 PM PDT 24
Peak memory 201928 kb
Host smart-b3e355cb-94a8-47d0-8e00-1fdf83ba5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318973943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1318973943
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1371278058
Short name T617
Test name
Test status
Simulation time 164380653275 ps
CPU time 382.98 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 202140 kb
Host smart-72a33616-b4c2-4977-a8d2-00a7b66f7f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371278058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1371278058
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3810206259
Short name T231
Test name
Test status
Simulation time 22363552017 ps
CPU time 45.88 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:44:31 PM PDT 24
Peak memory 210720 kb
Host smart-9daafa8a-497a-45d9-84df-e6fcd92c2848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810206259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3810206259
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3167702398
Short name T771
Test name
Test status
Simulation time 344784694 ps
CPU time 0.82 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:43:46 PM PDT 24
Peak memory 201900 kb
Host smart-d187843d-8842-4725-8b40-ca08474aac2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167702398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3167702398
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3303767970
Short name T524
Test name
Test status
Simulation time 163931773071 ps
CPU time 203.04 seconds
Started Aug 18 05:43:52 PM PDT 24
Finished Aug 18 05:47:15 PM PDT 24
Peak memory 202128 kb
Host smart-86310b0b-2c38-4cfb-ae26-fc9989693c31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303767970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3303767970
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.268569267
Short name T344
Test name
Test status
Simulation time 491788797551 ps
CPU time 1074.27 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 06:01:40 PM PDT 24
Peak memory 202116 kb
Host smart-05fe980d-4e58-4458-8049-a0ee7cf2c0dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=268569267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.268569267
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1804535465
Short name T320
Test name
Test status
Simulation time 330865576128 ps
CPU time 206.66 seconds
Started Aug 18 05:43:55 PM PDT 24
Finished Aug 18 05:47:22 PM PDT 24
Peak memory 202288 kb
Host smart-0bfe9852-0212-4421-97db-c4b001ec5ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804535465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1804535465
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.754751674
Short name T542
Test name
Test status
Simulation time 486292589807 ps
CPU time 1058.61 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 202068 kb
Host smart-0eadee7e-c5f0-4ba4-a28a-50fbcc707021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754751674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.754751674
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2156527185
Short name T130
Test name
Test status
Simulation time 202288475478 ps
CPU time 457.8 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:51:29 PM PDT 24
Peak memory 201996 kb
Host smart-7604a1b7-1342-4e57-8036-4b0ed92d8609
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156527185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2156527185
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.480629616
Short name T538
Test name
Test status
Simulation time 207428558869 ps
CPU time 50.55 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:44:37 PM PDT 24
Peak memory 202080 kb
Host smart-030465d9-393d-4321-8834-22f6697a7adb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480629616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.480629616
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3386299296
Short name T49
Test name
Test status
Simulation time 81234855536 ps
CPU time 280.03 seconds
Started Aug 18 05:43:44 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 202368 kb
Host smart-55d6ce2d-b887-4b76-8c25-33eb73dbb453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386299296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3386299296
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.536009692
Short name T729
Test name
Test status
Simulation time 32564261561 ps
CPU time 35.71 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:44:25 PM PDT 24
Peak memory 201928 kb
Host smart-c7afddee-ba56-45f5-92ab-8b67b6206fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536009692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.536009692
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1187318560
Short name T485
Test name
Test status
Simulation time 5011199933 ps
CPU time 11.77 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:44:02 PM PDT 24
Peak memory 201920 kb
Host smart-a44732a9-1f24-479c-aeef-865156fc65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187318560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1187318560
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1059606253
Short name T750
Test name
Test status
Simulation time 6047045976 ps
CPU time 14.47 seconds
Started Aug 18 05:43:47 PM PDT 24
Finished Aug 18 05:44:02 PM PDT 24
Peak memory 201944 kb
Host smart-57b7ec70-339e-4000-bff0-96e17f64dfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059606253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1059606253
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2308941834
Short name T274
Test name
Test status
Simulation time 5830090503 ps
CPU time 8.15 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:43:54 PM PDT 24
Peak memory 202212 kb
Host smart-80fff2aa-b510-4ff2-b2a9-e092472fdeb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308941834 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2308941834
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4210249944
Short name T384
Test name
Test status
Simulation time 425065901 ps
CPU time 0.79 seconds
Started Aug 18 05:43:46 PM PDT 24
Finished Aug 18 05:43:47 PM PDT 24
Peak memory 201784 kb
Host smart-f44e60d8-6599-4faa-8a4e-abcc8b296653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210249944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4210249944
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1573075278
Short name T267
Test name
Test status
Simulation time 560700623850 ps
CPU time 189.83 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:46:59 PM PDT 24
Peak memory 202016 kb
Host smart-e8896c83-3883-4b2a-82c3-3c10b4d0bb78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573075278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1573075278
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.814209118
Short name T712
Test name
Test status
Simulation time 166309424758 ps
CPU time 97.74 seconds
Started Aug 18 05:43:57 PM PDT 24
Finished Aug 18 05:45:34 PM PDT 24
Peak memory 202116 kb
Host smart-9936aac6-a92a-4383-ac06-2fea24f56ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814209118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.814209118
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1131992605
Short name T744
Test name
Test status
Simulation time 166818279599 ps
CPU time 398.09 seconds
Started Aug 18 05:43:45 PM PDT 24
Finished Aug 18 05:50:23 PM PDT 24
Peak memory 202108 kb
Host smart-e787011b-b470-4378-b366-dbbefde58ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131992605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1131992605
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3680197519
Short name T608
Test name
Test status
Simulation time 168939704623 ps
CPU time 36.99 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:44:26 PM PDT 24
Peak memory 202128 kb
Host smart-b5fefeed-390f-4664-98cc-a66eace6e90b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680197519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3680197519
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.720277680
Short name T552
Test name
Test status
Simulation time 324388856239 ps
CPU time 718.88 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:55:49 PM PDT 24
Peak memory 202056 kb
Host smart-6d91e8ba-5092-42f4-8b12-4cc95849b955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720277680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.720277680
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.4139796405
Short name T677
Test name
Test status
Simulation time 318360366879 ps
CPU time 181.37 seconds
Started Aug 18 05:43:47 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 201988 kb
Host smart-6c22cbb1-0e64-4bf9-9a5f-29fd5a3f1cb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139796405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.4139796405
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2999386336
Short name T686
Test name
Test status
Simulation time 612510801052 ps
CPU time 1404.64 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 06:07:16 PM PDT 24
Peak memory 202140 kb
Host smart-809ed119-6262-448d-b4f2-793cd643284f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999386336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2999386336
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2456710205
Short name T789
Test name
Test status
Simulation time 144903337415 ps
CPU time 750.26 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:56:29 PM PDT 24
Peak memory 202356 kb
Host smart-ce10fcbd-0510-44e9-a0f6-7db89497ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456710205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2456710205
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4011279007
Short name T459
Test name
Test status
Simulation time 45464705754 ps
CPU time 53.66 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:44:41 PM PDT 24
Peak memory 201840 kb
Host smart-39b0e8c0-527c-4c7f-aaa5-2c3ecca85eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011279007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4011279007
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1194278419
Short name T727
Test name
Test status
Simulation time 4965247699 ps
CPU time 3.25 seconds
Started Aug 18 05:43:48 PM PDT 24
Finished Aug 18 05:43:51 PM PDT 24
Peak memory 201944 kb
Host smart-17a425dc-95b8-4192-810d-34b5026cb9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194278419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1194278419
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1680027948
Short name T95
Test name
Test status
Simulation time 5760349104 ps
CPU time 1.63 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:43:53 PM PDT 24
Peak memory 201880 kb
Host smart-5fe668ee-9257-4036-a378-43ff7dfb3012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680027948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1680027948
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.4107811450
Short name T602
Test name
Test status
Simulation time 435022651739 ps
CPU time 1017.14 seconds
Started Aug 18 05:43:56 PM PDT 24
Finished Aug 18 06:00:53 PM PDT 24
Peak memory 212696 kb
Host smart-5c27ef7f-2479-4c9c-9ef2-3b553f15bb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107811450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.4107811450
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3903720960
Short name T715
Test name
Test status
Simulation time 413103752 ps
CPU time 1.02 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:42:39 PM PDT 24
Peak memory 201960 kb
Host smart-3991fbc4-7003-4172-9f3d-3fe7fe5d88a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903720960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3903720960
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.677512018
Short name T582
Test name
Test status
Simulation time 504336742754 ps
CPU time 224.79 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 202076 kb
Host smart-899c32f0-b049-4d74-9901-65217c937a49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677512018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.677512018
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3674552774
Short name T208
Test name
Test status
Simulation time 559027530153 ps
CPU time 1152.22 seconds
Started Aug 18 05:42:34 PM PDT 24
Finished Aug 18 06:01:47 PM PDT 24
Peak memory 202076 kb
Host smart-7239b971-a4aa-482d-95a5-d2e1afef193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674552774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3674552774
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3643237607
Short name T328
Test name
Test status
Simulation time 163729506920 ps
CPU time 105.74 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:44:38 PM PDT 24
Peak memory 202088 kb
Host smart-e45c4440-c2d3-4308-888e-a16b33c28de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643237607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3643237607
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3056801810
Short name T650
Test name
Test status
Simulation time 328086721326 ps
CPU time 194.13 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:46:00 PM PDT 24
Peak memory 202136 kb
Host smart-5be64800-e110-4a18-963e-6a00bf44d141
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056801810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3056801810
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2294098937
Short name T413
Test name
Test status
Simulation time 335758314560 ps
CPU time 418.1 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 202068 kb
Host smart-c4073724-fec2-410e-9fe6-413e85ac4bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294098937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2294098937
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3625705463
Short name T149
Test name
Test status
Simulation time 333081056414 ps
CPU time 203.06 seconds
Started Aug 18 05:42:58 PM PDT 24
Finished Aug 18 05:46:21 PM PDT 24
Peak memory 202080 kb
Host smart-222020c9-6cb1-4e62-a163-15eb973103b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625705463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3625705463
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3620100773
Short name T515
Test name
Test status
Simulation time 168858331391 ps
CPU time 394.65 seconds
Started Aug 18 05:43:00 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 202100 kb
Host smart-919152fc-3561-4baa-8758-eba5f17744ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620100773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3620100773
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2547199134
Short name T475
Test name
Test status
Simulation time 612276850812 ps
CPU time 1285.9 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 06:04:13 PM PDT 24
Peak memory 202008 kb
Host smart-a3a70b36-e6fb-447b-b10f-1445ed4cef5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547199134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2547199134
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3198593624
Short name T88
Test name
Test status
Simulation time 136573069923 ps
CPU time 636.21 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:53:28 PM PDT 24
Peak memory 202308 kb
Host smart-c8e8b461-701e-47cf-989b-a7c9ccf0cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198593624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3198593624
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1119002853
Short name T398
Test name
Test status
Simulation time 28589521275 ps
CPU time 17.03 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:42:53 PM PDT 24
Peak memory 201892 kb
Host smart-71372749-f556-4745-9d06-efb041f3f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119002853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1119002853
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.760572819
Short name T512
Test name
Test status
Simulation time 4600510939 ps
CPU time 11.96 seconds
Started Aug 18 05:42:50 PM PDT 24
Finished Aug 18 05:43:02 PM PDT 24
Peak memory 201828 kb
Host smart-37592201-04dd-4b74-9dae-48c5da06a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760572819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.760572819
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2282561946
Short name T62
Test name
Test status
Simulation time 4205435775 ps
CPU time 5.46 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:42:47 PM PDT 24
Peak memory 217384 kb
Host smart-c69adf80-2277-448d-9063-47dbc1d92393
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282561946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2282561946
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3554654042
Short name T355
Test name
Test status
Simulation time 5880536843 ps
CPU time 3.57 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:42:50 PM PDT 24
Peak memory 202128 kb
Host smart-12b2c137-9f2b-453d-92fe-2cf84a5c0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554654042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3554654042
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.622168455
Short name T572
Test name
Test status
Simulation time 196698772694 ps
CPU time 118.89 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:44:41 PM PDT 24
Peak memory 202144 kb
Host smart-3ab18739-d47c-4afd-8611-2fd8c113a9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622168455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.622168455
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2711378844
Short name T24
Test name
Test status
Simulation time 2546719499 ps
CPU time 6.74 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:43:04 PM PDT 24
Peak memory 210440 kb
Host smart-58e1e1b7-048f-452e-a8d4-d821ad883561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711378844 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2711378844
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2537677040
Short name T474
Test name
Test status
Simulation time 410472383 ps
CPU time 1.55 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:43:53 PM PDT 24
Peak memory 201960 kb
Host smart-da0880bf-f9ab-4707-875c-5dbd109e0371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537677040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2537677040
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1477374646
Short name T703
Test name
Test status
Simulation time 166432774466 ps
CPU time 97.71 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:45:29 PM PDT 24
Peak memory 202136 kb
Host smart-d050d908-d556-405e-a837-928aa1af88ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477374646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1477374646
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.89911059
Short name T5
Test name
Test status
Simulation time 181123092054 ps
CPU time 108.4 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:45:42 PM PDT 24
Peak memory 202100 kb
Host smart-6c5f0252-3096-4f97-b05e-720c2173cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89911059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.89911059
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1402025766
Short name T660
Test name
Test status
Simulation time 158244473685 ps
CPU time 329.26 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:49:20 PM PDT 24
Peak memory 202104 kb
Host smart-fb4d3095-b5cf-4aba-aae3-f3dbd69e7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402025766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1402025766
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2446163725
Short name T385
Test name
Test status
Simulation time 491133743921 ps
CPU time 1234.38 seconds
Started Aug 18 05:43:56 PM PDT 24
Finished Aug 18 06:04:30 PM PDT 24
Peak memory 202316 kb
Host smart-af033beb-c412-4261-937e-1af1d2dfd639
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446163725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2446163725
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1721272377
Short name T244
Test name
Test status
Simulation time 494594635602 ps
CPU time 883.58 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 202108 kb
Host smart-33df9091-1d76-4c17-9fa3-9c5f77be52da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721272377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1721272377
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3478427114
Short name T640
Test name
Test status
Simulation time 163932005230 ps
CPU time 132.9 seconds
Started Aug 18 05:43:50 PM PDT 24
Finished Aug 18 05:46:03 PM PDT 24
Peak memory 202112 kb
Host smart-b7f73032-7288-489e-9add-9029486c3816
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478427114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3478427114
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3824409857
Short name T788
Test name
Test status
Simulation time 372984621579 ps
CPU time 873 seconds
Started Aug 18 05:43:49 PM PDT 24
Finished Aug 18 05:58:23 PM PDT 24
Peak memory 202096 kb
Host smart-cea442ff-23cd-46e7-b44e-914fb9dea486
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824409857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3824409857
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1892236782
Short name T719
Test name
Test status
Simulation time 616599512054 ps
CPU time 744.59 seconds
Started Aug 18 05:43:51 PM PDT 24
Finished Aug 18 05:56:16 PM PDT 24
Peak memory 202080 kb
Host smart-c0352bc0-2c02-49ea-a219-e0a540ff2801
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892236782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1892236782
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4116525121
Short name T708
Test name
Test status
Simulation time 88404746363 ps
CPU time 301.11 seconds
Started Aug 18 05:43:47 PM PDT 24
Finished Aug 18 05:48:49 PM PDT 24
Peak memory 202280 kb
Host smart-0dd850aa-58f9-4a78-80ce-7c2cf33d9cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116525121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4116525121
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.700859162
Short name T676
Test name
Test status
Simulation time 36860821585 ps
CPU time 21.47 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 05:44:20 PM PDT 24
Peak memory 201924 kb
Host smart-b18e42fc-8d9d-47cc-b381-0b17c56649dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700859162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.700859162
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4222780961
Short name T464
Test name
Test status
Simulation time 4054891889 ps
CPU time 2.91 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:43:57 PM PDT 24
Peak memory 201936 kb
Host smart-39bebadf-c435-4fbb-87ec-454899feefa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222780961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4222780961
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3879784450
Short name T661
Test name
Test status
Simulation time 6074840374 ps
CPU time 8.21 seconds
Started Aug 18 05:43:57 PM PDT 24
Finished Aug 18 05:44:05 PM PDT 24
Peak memory 202132 kb
Host smart-4c0c9904-37f9-4544-b3b4-b7de1ddab182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879784450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3879784450
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3555287087
Short name T790
Test name
Test status
Simulation time 85116371965 ps
CPU time 22.23 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:44:16 PM PDT 24
Peak memory 202212 kb
Host smart-293d97af-e143-4b77-95be-5999d3256403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555287087 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3555287087
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3068481402
Short name T694
Test name
Test status
Simulation time 439574321 ps
CPU time 0.87 seconds
Started Aug 18 05:43:57 PM PDT 24
Finished Aug 18 05:43:58 PM PDT 24
Peak memory 201944 kb
Host smart-439fb620-0b43-46b7-8112-2c4854b554c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068481402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3068481402
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2794458375
Short name T766
Test name
Test status
Simulation time 522759207164 ps
CPU time 326.53 seconds
Started Aug 18 05:43:53 PM PDT 24
Finished Aug 18 05:49:20 PM PDT 24
Peak memory 202096 kb
Host smart-27004493-6009-442e-9711-ee05b2fa67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794458375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2794458375
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1665258749
Short name T243
Test name
Test status
Simulation time 479961110192 ps
CPU time 1031.89 seconds
Started Aug 18 05:43:56 PM PDT 24
Finished Aug 18 06:01:08 PM PDT 24
Peak memory 202112 kb
Host smart-a6d27cc3-a8c6-4054-a185-238c10b87d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665258749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1665258749
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3640693510
Short name T159
Test name
Test status
Simulation time 488374482549 ps
CPU time 303.36 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 05:49:02 PM PDT 24
Peak memory 202156 kb
Host smart-63425273-cf00-4613-8447-2d9b733891d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640693510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3640693510
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.11447178
Short name T743
Test name
Test status
Simulation time 160008740928 ps
CPU time 370.94 seconds
Started Aug 18 05:43:53 PM PDT 24
Finished Aug 18 05:50:04 PM PDT 24
Peak memory 202096 kb
Host smart-d400fde6-8d6d-4904-a2b2-71255ab66fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11447178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.11447178
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2693750201
Short name T612
Test name
Test status
Simulation time 330579350102 ps
CPU time 173.69 seconds
Started Aug 18 05:43:53 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 202040 kb
Host smart-ddc4ee2c-cad0-4730-9db6-7b621c6c4631
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693750201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2693750201
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3199188594
Short name T722
Test name
Test status
Simulation time 183571593856 ps
CPU time 42.5 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 202096 kb
Host smart-86794d16-b86d-475e-ae7e-eaf75e68b44d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199188594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3199188594
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.754090158
Short name T351
Test name
Test status
Simulation time 614710690678 ps
CPU time 1372.3 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 06:06:51 PM PDT 24
Peak memory 202120 kb
Host smart-02b322a1-c0c9-4d28-953b-b20166a6e8d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754090158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.754090158
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1720137884
Short name T180
Test name
Test status
Simulation time 104145251241 ps
CPU time 349.61 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:49:48 PM PDT 24
Peak memory 202328 kb
Host smart-d273282f-64ba-4261-8c04-9e0b8f525fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720137884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1720137884
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1925548352
Short name T430
Test name
Test status
Simulation time 31828719951 ps
CPU time 78.97 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:45:21 PM PDT 24
Peak memory 201944 kb
Host smart-b1c48bf4-e35e-4c7f-90d1-91fd594415d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925548352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1925548352
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.164763992
Short name T623
Test name
Test status
Simulation time 4279608139 ps
CPU time 10.49 seconds
Started Aug 18 05:43:55 PM PDT 24
Finished Aug 18 05:44:06 PM PDT 24
Peak memory 201780 kb
Host smart-bcca0567-20c9-42c2-8504-0af82337136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164763992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.164763992
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1551031517
Short name T10
Test name
Test status
Simulation time 5611947429 ps
CPU time 6.81 seconds
Started Aug 18 05:43:55 PM PDT 24
Finished Aug 18 05:44:02 PM PDT 24
Peak memory 201936 kb
Host smart-d9bdfed5-7e3d-44c4-bc1e-b76d6d57475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551031517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1551031517
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3702847415
Short name T22
Test name
Test status
Simulation time 5220325435 ps
CPU time 12.61 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:44:06 PM PDT 24
Peak memory 210472 kb
Host smart-3929349d-cc92-403d-9aad-8cebb3985138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702847415 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3702847415
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1048914823
Short name T672
Test name
Test status
Simulation time 322890173 ps
CPU time 1.36 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:44:04 PM PDT 24
Peak memory 201908 kb
Host smart-379eaab2-02df-4db7-a1ea-432ca0e55427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048914823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1048914823
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.685686259
Short name T175
Test name
Test status
Simulation time 413056410508 ps
CPU time 228.58 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 202104 kb
Host smart-d105b570-95db-4062-af43-48218465353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685686259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.685686259
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2010456945
Short name T569
Test name
Test status
Simulation time 164067318026 ps
CPU time 385.07 seconds
Started Aug 18 05:43:57 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 202164 kb
Host smart-758101a6-de3d-4cce-9f41-7714d193bdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010456945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2010456945
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1120501895
Short name T622
Test name
Test status
Simulation time 164684216552 ps
CPU time 386.31 seconds
Started Aug 18 05:44:00 PM PDT 24
Finished Aug 18 05:50:26 PM PDT 24
Peak memory 202048 kb
Host smart-297e80bf-75b5-4965-b22f-cac71f2430a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120501895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1120501895
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.791945953
Short name T155
Test name
Test status
Simulation time 492330081293 ps
CPU time 379.41 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:50:17 PM PDT 24
Peak memory 202092 kb
Host smart-a8a8d122-6fc2-4daf-a545-b0297140ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791945953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.791945953
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.664980251
Short name T765
Test name
Test status
Simulation time 497083113302 ps
CPU time 512.57 seconds
Started Aug 18 05:43:54 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 202048 kb
Host smart-ce998a60-e689-4b6c-823c-a6e0d590a555
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=664980251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.664980251
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1209697679
Short name T324
Test name
Test status
Simulation time 405099756314 ps
CPU time 354.84 seconds
Started Aug 18 05:44:04 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 202096 kb
Host smart-bd0d1543-095e-4b5c-bdab-6c25bf1a6688
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209697679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1209697679
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2367094903
Short name T742
Test name
Test status
Simulation time 402238975452 ps
CPU time 946.44 seconds
Started Aug 18 05:43:56 PM PDT 24
Finished Aug 18 05:59:43 PM PDT 24
Peak memory 202148 kb
Host smart-6ec5c092-4d6a-4cbc-8b3b-2cc2af69bc60
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367094903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2367094903
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2819165998
Short name T96
Test name
Test status
Simulation time 33881974022 ps
CPU time 9.81 seconds
Started Aug 18 05:43:59 PM PDT 24
Finished Aug 18 05:44:08 PM PDT 24
Peak memory 201892 kb
Host smart-6983edb2-3e1f-42b6-969c-a49bf21dbeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819165998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2819165998
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3880608915
Short name T454
Test name
Test status
Simulation time 4921809788 ps
CPU time 11.01 seconds
Started Aug 18 05:43:57 PM PDT 24
Finished Aug 18 05:44:08 PM PDT 24
Peak memory 201904 kb
Host smart-8a2d522a-7ad8-4937-bb61-6560aea64459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880608915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3880608915
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4002009330
Short name T429
Test name
Test status
Simulation time 5672650616 ps
CPU time 13.17 seconds
Started Aug 18 05:43:58 PM PDT 24
Finished Aug 18 05:44:11 PM PDT 24
Peak memory 201924 kb
Host smart-9c1d43c1-c365-43f2-8745-76d701b70ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002009330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4002009330
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3370012398
Short name T341
Test name
Test status
Simulation time 1898489130965 ps
CPU time 1339.95 seconds
Started Aug 18 05:44:03 PM PDT 24
Finished Aug 18 06:06:23 PM PDT 24
Peak memory 210580 kb
Host smart-226dbaff-5bc0-4303-8d59-3192bfc6497b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370012398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3370012398
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.686384774
Short name T226
Test name
Test status
Simulation time 5568925063 ps
CPU time 4.18 seconds
Started Aug 18 05:44:01 PM PDT 24
Finished Aug 18 05:44:06 PM PDT 24
Peak memory 210424 kb
Host smart-54f0f3fd-c93f-4af3-8894-364936129171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686384774 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.686384774
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2178526611
Short name T786
Test name
Test status
Simulation time 456811603 ps
CPU time 0.88 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:44:21 PM PDT 24
Peak memory 201908 kb
Host smart-5e7be032-4302-449d-a7c6-546be2799d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178526611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2178526611
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3810434884
Short name T263
Test name
Test status
Simulation time 165047167494 ps
CPU time 379.76 seconds
Started Aug 18 05:44:04 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 202140 kb
Host smart-bc3286ef-60e1-4723-9072-e4345dd5a27d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810434884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3810434884
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3888977983
Short name T212
Test name
Test status
Simulation time 529215263373 ps
CPU time 1275.72 seconds
Started Aug 18 05:44:01 PM PDT 24
Finished Aug 18 06:05:17 PM PDT 24
Peak memory 202104 kb
Host smart-56d451a7-79bb-4119-8f5f-20c8e9c51dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888977983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3888977983
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2615930880
Short name T471
Test name
Test status
Simulation time 167518009506 ps
CPU time 104.65 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:45:46 PM PDT 24
Peak memory 202088 kb
Host smart-b65908af-01e1-4096-a4f2-606e80a6eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615930880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2615930880
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1250648177
Short name T443
Test name
Test status
Simulation time 487653023483 ps
CPU time 338.64 seconds
Started Aug 18 05:44:00 PM PDT 24
Finished Aug 18 05:49:39 PM PDT 24
Peak memory 202036 kb
Host smart-e4f39d48-96e0-46c0-9ba9-01e2868a8b1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250648177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1250648177
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.948501677
Short name T444
Test name
Test status
Simulation time 489015523407 ps
CPU time 302.34 seconds
Started Aug 18 05:44:03 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 202072 kb
Host smart-faec2e3b-ed69-4f7b-b60a-a363b09be2f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=948501677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.948501677
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.137292305
Short name T285
Test name
Test status
Simulation time 609192345063 ps
CPU time 1300.45 seconds
Started Aug 18 05:44:03 PM PDT 24
Finished Aug 18 06:05:44 PM PDT 24
Peak memory 202140 kb
Host smart-46788ff9-1a0b-485f-a28b-9cced011e9a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137292305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.137292305
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2405239530
Short name T573
Test name
Test status
Simulation time 202100712455 ps
CPU time 118.42 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:46:00 PM PDT 24
Peak memory 202096 kb
Host smart-0ffcfd38-3698-49d4-9161-0565789da92c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405239530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2405239530
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4219217954
Short name T626
Test name
Test status
Simulation time 133866663657 ps
CPU time 705.45 seconds
Started Aug 18 05:44:01 PM PDT 24
Finished Aug 18 05:55:46 PM PDT 24
Peak memory 202388 kb
Host smart-6c675785-143b-4243-9c49-ad727716b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219217954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4219217954
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3476731079
Short name T361
Test name
Test status
Simulation time 43208829319 ps
CPU time 50.22 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:44:52 PM PDT 24
Peak memory 201912 kb
Host smart-087dab08-7bdd-4aa1-9427-7e32ef3bdd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476731079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3476731079
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2413532828
Short name T352
Test name
Test status
Simulation time 2954653705 ps
CPU time 6.97 seconds
Started Aug 18 05:44:06 PM PDT 24
Finished Aug 18 05:44:13 PM PDT 24
Peak memory 201928 kb
Host smart-35c40a76-b84d-4ca8-b2a6-55fd2012253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413532828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2413532828
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3770992833
Short name T452
Test name
Test status
Simulation time 5757637663 ps
CPU time 10.19 seconds
Started Aug 18 05:44:03 PM PDT 24
Finished Aug 18 05:44:14 PM PDT 24
Peak memory 201924 kb
Host smart-53b198d7-a5ba-4cd7-9559-a81ad0aa4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770992833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3770992833
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1299093937
Short name T735
Test name
Test status
Simulation time 335334732864 ps
CPU time 672.68 seconds
Started Aug 18 05:44:02 PM PDT 24
Finished Aug 18 05:55:15 PM PDT 24
Peak memory 202080 kb
Host smart-6ad709fc-cc64-468f-887a-68753dc6cacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299093937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1299093937
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.825628929
Short name T33
Test name
Test status
Simulation time 5135158403 ps
CPU time 6.02 seconds
Started Aug 18 05:44:01 PM PDT 24
Finished Aug 18 05:44:07 PM PDT 24
Peak memory 202240 kb
Host smart-fc599861-23d7-421b-98ed-c0b33c239e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825628929 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.825628929
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1413134903
Short name T576
Test name
Test status
Simulation time 447849262 ps
CPU time 1.61 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:44:21 PM PDT 24
Peak memory 201964 kb
Host smart-3664200b-f1ef-4e12-a01c-014e367b90ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413134903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1413134903
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.4121802381
Short name T217
Test name
Test status
Simulation time 164973858481 ps
CPU time 176.79 seconds
Started Aug 18 05:44:17 PM PDT 24
Finished Aug 18 05:47:14 PM PDT 24
Peak memory 202084 kb
Host smart-5a8e5c34-317a-4406-b0e0-9ba1e92002f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121802381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4121802381
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1089220528
Short name T227
Test name
Test status
Simulation time 164635429966 ps
CPU time 66.08 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:45:25 PM PDT 24
Peak memory 202000 kb
Host smart-6ba8dffb-7152-4516-83e9-7d7cc2808c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089220528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1089220528
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.370673400
Short name T476
Test name
Test status
Simulation time 494603545478 ps
CPU time 107.23 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:46:08 PM PDT 24
Peak memory 202080 kb
Host smart-2d370a37-d492-40aa-b3de-485751bdb3b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=370673400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.370673400
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.964378467
Short name T520
Test name
Test status
Simulation time 494886267595 ps
CPU time 578.62 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:53:58 PM PDT 24
Peak memory 202088 kb
Host smart-4965194c-0648-4ced-80b5-1dfe0df4b7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964378467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.964378467
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3382325096
Short name T594
Test name
Test status
Simulation time 325441821701 ps
CPU time 206.94 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 202056 kb
Host smart-99e8f16d-efc2-41a3-bb74-44ee68eba827
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382325096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3382325096
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1626744023
Short name T154
Test name
Test status
Simulation time 351832745175 ps
CPU time 200.09 seconds
Started Aug 18 05:44:25 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 202284 kb
Host smart-9ac6ec7c-1668-4591-a0c0-d05367a28588
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626744023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1626744023
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1808742534
Short name T554
Test name
Test status
Simulation time 394500548027 ps
CPU time 827.2 seconds
Started Aug 18 05:44:18 PM PDT 24
Finished Aug 18 05:58:05 PM PDT 24
Peak memory 202036 kb
Host smart-a51b7030-8c7c-4cef-a73d-dc20c57bd32d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808742534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1808742534
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3078104820
Short name T43
Test name
Test status
Simulation time 111894357711 ps
CPU time 623.73 seconds
Started Aug 18 05:44:17 PM PDT 24
Finished Aug 18 05:54:41 PM PDT 24
Peak memory 202348 kb
Host smart-c754f469-b824-4da2-b96a-fc13f9887b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078104820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3078104820
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.386564369
Short name T371
Test name
Test status
Simulation time 26393603125 ps
CPU time 62.88 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:45:22 PM PDT 24
Peak memory 201772 kb
Host smart-c8e8213c-6d6d-4ef3-b295-0a27cc2ede9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386564369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.386564369
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1202533170
Short name T547
Test name
Test status
Simulation time 4918023980 ps
CPU time 3.59 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:44:26 PM PDT 24
Peak memory 201936 kb
Host smart-8e26ecb1-3c0d-46a8-a832-0c3ba57597cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202533170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1202533170
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2898115239
Short name T792
Test name
Test status
Simulation time 5591252636 ps
CPU time 13.01 seconds
Started Aug 18 05:44:23 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 201824 kb
Host smart-5039696b-2acd-4308-afc1-b650ddd6212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898115239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2898115239
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3905452331
Short name T287
Test name
Test status
Simulation time 501350003783 ps
CPU time 505.51 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:52:44 PM PDT 24
Peak memory 210576 kb
Host smart-0e56aff2-90eb-4954-a36b-b4787385b743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905452331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3905452331
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2676152808
Short name T18
Test name
Test status
Simulation time 6411699945 ps
CPU time 10.76 seconds
Started Aug 18 05:44:16 PM PDT 24
Finished Aug 18 05:44:27 PM PDT 24
Peak memory 202092 kb
Host smart-4f716bec-de7a-4914-bc3e-74afd242c6a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676152808 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2676152808
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4233795214
Short name T370
Test name
Test status
Simulation time 499365384 ps
CPU time 0.86 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:44:22 PM PDT 24
Peak memory 201956 kb
Host smart-dfbae3e1-89d9-43c9-aa68-e43e4866da2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233795214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4233795214
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1911985868
Short name T726
Test name
Test status
Simulation time 332283693518 ps
CPU time 176.91 seconds
Started Aug 18 05:44:23 PM PDT 24
Finished Aug 18 05:47:20 PM PDT 24
Peak memory 202000 kb
Host smart-55336d58-2fda-4fcb-bf12-b0707091a5ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911985868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1911985868
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1097874839
Short name T717
Test name
Test status
Simulation time 164487774042 ps
CPU time 92.62 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:45:54 PM PDT 24
Peak memory 202124 kb
Host smart-9afdcf2e-e7c4-4005-8766-116d9afa9676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097874839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1097874839
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3729465329
Short name T392
Test name
Test status
Simulation time 329996782622 ps
CPU time 165.8 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 202120 kb
Host smart-ee28d7d1-62f9-4633-aecc-33eb524d921b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729465329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3729465329
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2468837227
Short name T237
Test name
Test status
Simulation time 330032336514 ps
CPU time 757.37 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 202008 kb
Host smart-5ac0a2da-faa4-479f-ba6f-b8e51d9dbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468837227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2468837227
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4015318234
Short name T29
Test name
Test status
Simulation time 496289033070 ps
CPU time 1090.35 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 06:02:30 PM PDT 24
Peak memory 202084 kb
Host smart-f82b0e32-8740-43c2-8330-5e98fee65236
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015318234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4015318234
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2669270923
Short name T11
Test name
Test status
Simulation time 177654783815 ps
CPU time 382.68 seconds
Started Aug 18 05:44:18 PM PDT 24
Finished Aug 18 05:50:41 PM PDT 24
Peak memory 201944 kb
Host smart-1ef3514e-1374-4928-ad4c-21a0e96ab2c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669270923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2669270923
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1760030356
Short name T745
Test name
Test status
Simulation time 605340619818 ps
CPU time 352.7 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 202104 kb
Host smart-b7caaaa2-da80-4e92-a144-bd1e8c4c1227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760030356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1760030356
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2939285894
Short name T781
Test name
Test status
Simulation time 72597439006 ps
CPU time 209.99 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:47:52 PM PDT 24
Peak memory 202356 kb
Host smart-8a5f3d11-b6f7-41e1-a734-18f0e87c5950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939285894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2939285894
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.885547793
Short name T504
Test name
Test status
Simulation time 41201668032 ps
CPU time 23.33 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:44:44 PM PDT 24
Peak memory 201924 kb
Host smart-baca1feb-7648-4d90-9889-947366d4578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885547793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.885547793
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1225353854
Short name T386
Test name
Test status
Simulation time 4252286873 ps
CPU time 5.92 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:44:27 PM PDT 24
Peak memory 201912 kb
Host smart-14717b6e-0db8-4654-8ca5-8ab07e4dc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225353854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1225353854
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3749733076
Short name T797
Test name
Test status
Simulation time 5805055265 ps
CPU time 13.12 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:44:33 PM PDT 24
Peak memory 201924 kb
Host smart-c56a39ab-abc1-4ec6-b0e4-4378a6ee51d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749733076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3749733076
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3159007360
Short name T125
Test name
Test status
Simulation time 210854985144 ps
CPU time 34.32 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:44:53 PM PDT 24
Peak memory 202104 kb
Host smart-22f641f5-97aa-492e-ab40-c8e1362156c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159007360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3159007360
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.804792552
Short name T543
Test name
Test status
Simulation time 304473411 ps
CPU time 1.34 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:44:23 PM PDT 24
Peak memory 201956 kb
Host smart-926960de-d0d9-40c2-95ba-953124f153ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804792552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.804792552
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.626857480
Short name T202
Test name
Test status
Simulation time 176671784597 ps
CPU time 375.94 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:50:35 PM PDT 24
Peak memory 202116 kb
Host smart-599a4b17-9a47-4fec-aa01-ece8992622d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626857480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.626857480
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3851477658
Short name T674
Test name
Test status
Simulation time 326797060437 ps
CPU time 757.68 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 201996 kb
Host smart-4a316c25-747e-4452-9c81-0bf98d23ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851477658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3851477658
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.516391722
Short name T198
Test name
Test status
Simulation time 494776611191 ps
CPU time 526.69 seconds
Started Aug 18 05:44:18 PM PDT 24
Finished Aug 18 05:53:05 PM PDT 24
Peak memory 202124 kb
Host smart-115b0976-18b7-4639-bcff-ed118ff7655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516391722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.516391722
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.18575963
Short name T794
Test name
Test status
Simulation time 500012200409 ps
CPU time 1098.7 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 06:02:39 PM PDT 24
Peak memory 202144 kb
Host smart-25af5f72-380d-4914-b16c-e191d2c04c81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt
_fixed.18575963
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3647456331
Short name T455
Test name
Test status
Simulation time 333208993807 ps
CPU time 109.18 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:46:12 PM PDT 24
Peak memory 202076 kb
Host smart-28336bbe-7a68-4b2c-b987-ace0fe23be15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647456331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3647456331
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2229295023
Short name T759
Test name
Test status
Simulation time 375224750622 ps
CPU time 844.31 seconds
Started Aug 18 05:44:18 PM PDT 24
Finished Aug 18 05:58:23 PM PDT 24
Peak memory 202048 kb
Host smart-ad554b66-3a3a-4d83-8b41-4fa18f3756e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229295023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2229295023
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1813015708
Short name T418
Test name
Test status
Simulation time 202749447712 ps
CPU time 470.45 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 202136 kb
Host smart-a60828d0-06c0-427e-8fd0-59b058ee66ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813015708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1813015708
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2766782985
Short name T738
Test name
Test status
Simulation time 66608060356 ps
CPU time 325.22 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:49:44 PM PDT 24
Peak memory 202420 kb
Host smart-ed98b209-b02b-430e-87c2-957689b0257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766782985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2766782985
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4237743185
Short name T6
Test name
Test status
Simulation time 42973035382 ps
CPU time 52.31 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:45:13 PM PDT 24
Peak memory 201936 kb
Host smart-fbb1973f-0f99-4052-ba1e-1dda0f2ce638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237743185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4237743185
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1088983918
Short name T403
Test name
Test status
Simulation time 4339991508 ps
CPU time 11.14 seconds
Started Aug 18 05:44:25 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 202128 kb
Host smart-3e6b3d2c-6578-432a-b430-0f492aa695ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088983918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1088983918
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3991377216
Short name T438
Test name
Test status
Simulation time 5818590060 ps
CPU time 3.42 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:44:24 PM PDT 24
Peak memory 201904 kb
Host smart-ea21806d-1707-4e20-bd70-d3a9baae4090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991377216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3991377216
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.421385431
Short name T31
Test name
Test status
Simulation time 362160688742 ps
CPU time 202.13 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:47:41 PM PDT 24
Peak memory 202128 kb
Host smart-569b3357-a6c6-44ee-bf78-751662df9182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421385431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
421385431
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1180463090
Short name T638
Test name
Test status
Simulation time 525565508 ps
CPU time 1.66 seconds
Started Aug 18 05:44:27 PM PDT 24
Finished Aug 18 05:44:29 PM PDT 24
Peak memory 201960 kb
Host smart-e33476df-fca4-4501-9c9c-48e2fa4813ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180463090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1180463090
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.970409775
Short name T642
Test name
Test status
Simulation time 166262735563 ps
CPU time 79.22 seconds
Started Aug 18 05:44:27 PM PDT 24
Finished Aug 18 05:45:46 PM PDT 24
Peak memory 202156 kb
Host smart-2ff02eeb-6f39-4ab5-b3d6-47cc9d3591f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970409775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.970409775
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3131297717
Short name T286
Test name
Test status
Simulation time 332622739386 ps
CPU time 162.97 seconds
Started Aug 18 05:44:19 PM PDT 24
Finished Aug 18 05:47:02 PM PDT 24
Peak memory 202124 kb
Host smart-a24f2a3c-84a1-4110-bad3-c40ee3b08abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131297717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3131297717
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1442988179
Short name T414
Test name
Test status
Simulation time 495390812236 ps
CPU time 1184.24 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 06:04:05 PM PDT 24
Peak memory 202092 kb
Host smart-a51e7d52-aea3-42b4-80bc-893ea861a1c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442988179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1442988179
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2598881097
Short name T696
Test name
Test status
Simulation time 322415439524 ps
CPU time 48.65 seconds
Started Aug 18 05:44:22 PM PDT 24
Finished Aug 18 05:45:11 PM PDT 24
Peak memory 202076 kb
Host smart-0efc5d17-5da7-44f1-9a9a-bf919519b896
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598881097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2598881097
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4073880168
Short name T782
Test name
Test status
Simulation time 166576100995 ps
CPU time 341.15 seconds
Started Aug 18 05:44:20 PM PDT 24
Finished Aug 18 05:50:01 PM PDT 24
Peak memory 202072 kb
Host smart-cd5f9177-354f-428e-b70e-9e6eec37cdf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073880168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4073880168
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3929033921
Short name T769
Test name
Test status
Simulation time 612302759935 ps
CPU time 150.4 seconds
Started Aug 18 05:44:29 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 202068 kb
Host smart-34dfcb34-1b84-438f-9795-264403b9bd4b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929033921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3929033921
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1214262536
Short name T487
Test name
Test status
Simulation time 91113464113 ps
CPU time 417.46 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 202360 kb
Host smart-635c76ac-870e-4b32-80da-25f7db2885bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214262536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1214262536
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3603068017
Short name T632
Test name
Test status
Simulation time 34488031539 ps
CPU time 13.67 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:44:47 PM PDT 24
Peak memory 201928 kb
Host smart-00aa4b02-f148-404d-86f9-29e0c7baf28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603068017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3603068017
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.446581806
Short name T723
Test name
Test status
Simulation time 3471948309 ps
CPU time 2.53 seconds
Started Aug 18 05:44:29 PM PDT 24
Finished Aug 18 05:44:31 PM PDT 24
Peak memory 201824 kb
Host smart-b87bed1f-b9c6-46e7-95fe-a472db2ea5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446581806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.446581806
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.511230838
Short name T706
Test name
Test status
Simulation time 5947279783 ps
CPU time 4.36 seconds
Started Aug 18 05:44:21 PM PDT 24
Finished Aug 18 05:44:26 PM PDT 24
Peak memory 201920 kb
Host smart-18109ea4-bc44-4af3-8e4a-18f1803d8588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511230838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.511230838
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2207852872
Short name T326
Test name
Test status
Simulation time 330836913500 ps
CPU time 774.98 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:57:28 PM PDT 24
Peak memory 202096 kb
Host smart-1ddca848-71c1-4723-9033-42acfe040eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207852872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2207852872
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2562817082
Short name T465
Test name
Test status
Simulation time 7465731060 ps
CPU time 13.78 seconds
Started Aug 18 05:44:25 PM PDT 24
Finished Aug 18 05:44:39 PM PDT 24
Peak memory 210676 kb
Host smart-c926e038-36db-4e0d-a87f-c450c062ac26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562817082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2562817082
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.409878042
Short name T69
Test name
Test status
Simulation time 561077434 ps
CPU time 0.85 seconds
Started Aug 18 05:44:31 PM PDT 24
Finished Aug 18 05:44:32 PM PDT 24
Peak memory 201960 kb
Host smart-87937548-dafd-4011-a6f6-5de422575a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409878042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.409878042
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2038548525
Short name T740
Test name
Test status
Simulation time 169227107044 ps
CPU time 287.42 seconds
Started Aug 18 05:44:26 PM PDT 24
Finished Aug 18 05:49:13 PM PDT 24
Peak memory 202060 kb
Host smart-f75317a5-d0cc-4a16-a31d-1603751a3912
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038548525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2038548525
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2457048681
Short name T123
Test name
Test status
Simulation time 353098074967 ps
CPU time 207.15 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:48:00 PM PDT 24
Peak memory 202004 kb
Host smart-a302a3d7-46c1-4f74-aafd-789373eacfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457048681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2457048681
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4172984551
Short name T544
Test name
Test status
Simulation time 499439809077 ps
CPU time 1183.3 seconds
Started Aug 18 05:44:28 PM PDT 24
Finished Aug 18 06:04:12 PM PDT 24
Peak memory 202068 kb
Host smart-8c13f373-d9c4-43e8-a6da-f67e4ee5b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172984551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4172984551
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.114261340
Short name T578
Test name
Test status
Simulation time 491087647974 ps
CPU time 1205.08 seconds
Started Aug 18 05:44:28 PM PDT 24
Finished Aug 18 06:04:34 PM PDT 24
Peak memory 202136 kb
Host smart-09d107fc-edb7-41c4-b5de-e44ba0a7069f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114261340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.114261340
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3941746521
Short name T756
Test name
Test status
Simulation time 327084284651 ps
CPU time 403.54 seconds
Started Aug 18 05:44:29 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 202008 kb
Host smart-f0a0e34c-e7f3-4c1b-b4c1-f29e945f9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941746521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3941746521
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3023751174
Short name T373
Test name
Test status
Simulation time 328586481849 ps
CPU time 196.54 seconds
Started Aug 18 05:44:25 PM PDT 24
Finished Aug 18 05:47:42 PM PDT 24
Peak memory 202132 kb
Host smart-b8e0f344-5fbc-4e1b-ad07-6aa5bcfd4262
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023751174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3023751174
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.515437380
Short name T553
Test name
Test status
Simulation time 205150740712 ps
CPU time 451.58 seconds
Started Aug 18 05:44:28 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 202112 kb
Host smart-499d11bf-efb4-4768-b122-a3ea55dd8827
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515437380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.515437380
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1037645642
Short name T380
Test name
Test status
Simulation time 34662873420 ps
CPU time 81.45 seconds
Started Aug 18 05:44:27 PM PDT 24
Finished Aug 18 05:45:48 PM PDT 24
Peak memory 201880 kb
Host smart-f15abdde-ffee-45ba-b969-67cb5613fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037645642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1037645642
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1779767701
Short name T644
Test name
Test status
Simulation time 3815513617 ps
CPU time 2.89 seconds
Started Aug 18 05:44:26 PM PDT 24
Finished Aug 18 05:44:29 PM PDT 24
Peak memory 201940 kb
Host smart-9d30480d-49b9-4ae2-9a08-53cecb08a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779767701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1779767701
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3266729594
Short name T767
Test name
Test status
Simulation time 5905008945 ps
CPU time 6.04 seconds
Started Aug 18 05:44:28 PM PDT 24
Finished Aug 18 05:44:34 PM PDT 24
Peak memory 201944 kb
Host smart-5d37dad7-624c-4169-870e-0c4b4d4b31c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266729594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3266729594
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2961734759
Short name T783
Test name
Test status
Simulation time 202420290391 ps
CPU time 100.98 seconds
Started Aug 18 05:44:29 PM PDT 24
Finished Aug 18 05:46:10 PM PDT 24
Peak memory 201996 kb
Host smart-122697cf-9cd8-45c0-95ca-c05159ea7d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961734759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2961734759
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1356605092
Short name T35
Test name
Test status
Simulation time 1257266451 ps
CPU time 5.91 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:44:39 PM PDT 24
Peak memory 201932 kb
Host smart-f2958c23-a94c-4ab6-9d1e-d6fce64ddbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356605092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1356605092
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2014549961
Short name T657
Test name
Test status
Simulation time 289899409 ps
CPU time 0.91 seconds
Started Aug 18 05:44:42 PM PDT 24
Finished Aug 18 05:44:43 PM PDT 24
Peak memory 201836 kb
Host smart-387ab485-221e-47fc-825d-e36233a171f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014549961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2014549961
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1966427497
Short name T633
Test name
Test status
Simulation time 353845932778 ps
CPU time 455.52 seconds
Started Aug 18 05:44:31 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 202104 kb
Host smart-942ddc0b-28e0-4943-a429-e8c9dd89c70c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966427497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1966427497
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2724455547
Short name T692
Test name
Test status
Simulation time 514905353347 ps
CPU time 332.31 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 202100 kb
Host smart-403cd6b9-bee5-4f8d-85aa-cac749902a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724455547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2724455547
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2264156424
Short name T446
Test name
Test status
Simulation time 166011788146 ps
CPU time 98.17 seconds
Started Aug 18 05:44:30 PM PDT 24
Finished Aug 18 05:46:09 PM PDT 24
Peak memory 202100 kb
Host smart-2bde5b95-8aee-4bab-abc6-8533de0f1952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264156424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2264156424
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.711805137
Short name T145
Test name
Test status
Simulation time 163580932071 ps
CPU time 194.65 seconds
Started Aug 18 05:44:32 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 202116 kb
Host smart-a2e204b9-f3cf-44a6-b0d3-8ca1655ec9b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711805137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.711805137
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3197469554
Short name T460
Test name
Test status
Simulation time 339854111733 ps
CPU time 775.42 seconds
Started Aug 18 05:44:36 PM PDT 24
Finished Aug 18 05:57:32 PM PDT 24
Peak memory 202136 kb
Host smart-2643646c-6f43-40cf-8755-2118211c66c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197469554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3197469554
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3028185214
Short name T510
Test name
Test status
Simulation time 164494924050 ps
CPU time 377.98 seconds
Started Aug 18 05:44:32 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 202028 kb
Host smart-f3d6d47d-9e2f-4430-844c-95692144293a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028185214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3028185214
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2704171598
Short name T607
Test name
Test status
Simulation time 554355728148 ps
CPU time 347.94 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 202072 kb
Host smart-0286bc65-8a6c-4b05-9424-4a2171dff323
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704171598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2704171598
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1155981340
Short name T680
Test name
Test status
Simulation time 580750399395 ps
CPU time 1301.46 seconds
Started Aug 18 05:44:32 PM PDT 24
Finished Aug 18 06:06:13 PM PDT 24
Peak memory 202100 kb
Host smart-0d5145bc-bec8-4cbc-9d0b-4fdca9e09468
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155981340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1155981340
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2373672225
Short name T447
Test name
Test status
Simulation time 25712959755 ps
CPU time 31.89 seconds
Started Aug 18 05:44:31 PM PDT 24
Finished Aug 18 05:45:03 PM PDT 24
Peak memory 201936 kb
Host smart-f1e56d3a-4a85-42bf-b445-7590bd06aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373672225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2373672225
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3355168722
Short name T442
Test name
Test status
Simulation time 3481071369 ps
CPU time 2.86 seconds
Started Aug 18 05:44:33 PM PDT 24
Finished Aug 18 05:44:36 PM PDT 24
Peak memory 201924 kb
Host smart-d2ffcf48-cbdf-41e0-bdf6-8ef437018439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355168722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3355168722
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2388774264
Short name T795
Test name
Test status
Simulation time 5841789039 ps
CPU time 7.28 seconds
Started Aug 18 05:44:32 PM PDT 24
Finished Aug 18 05:44:40 PM PDT 24
Peak memory 201940 kb
Host smart-6d7e086d-ecb8-445e-a1bd-88f5a4142ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388774264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2388774264
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4056626700
Short name T314
Test name
Test status
Simulation time 171720209854 ps
CPU time 98.31 seconds
Started Aug 18 05:44:42 PM PDT 24
Finished Aug 18 05:46:20 PM PDT 24
Peak memory 202128 kb
Host smart-7a18f45a-1a96-4be5-9d8b-8fe96f6c34e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056626700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4056626700
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.63505035
Short name T70
Test name
Test status
Simulation time 386436146 ps
CPU time 1.06 seconds
Started Aug 18 05:42:29 PM PDT 24
Finished Aug 18 05:42:30 PM PDT 24
Peak memory 201948 kb
Host smart-ffc654e2-fd5e-43f7-bdb3-c838ae2b85aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63505035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.63505035
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.842433697
Short name T298
Test name
Test status
Simulation time 161536855647 ps
CPU time 95.27 seconds
Started Aug 18 05:42:42 PM PDT 24
Finished Aug 18 05:44:18 PM PDT 24
Peak memory 202144 kb
Host smart-0267dc3b-84bf-41c5-a5cc-94e1ea7f4cf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842433697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.842433697
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.794339242
Short name T775
Test name
Test status
Simulation time 343204499151 ps
CPU time 380.48 seconds
Started Aug 18 05:42:44 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 202128 kb
Host smart-820c6f7a-9ed8-413b-a600-89a78eff87b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794339242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.794339242
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3652230746
Short name T523
Test name
Test status
Simulation time 159328275176 ps
CPU time 186.52 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:46:04 PM PDT 24
Peak memory 202064 kb
Host smart-4ccdb0fa-9526-4a24-8805-a327029145e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652230746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3652230746
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.983493951
Short name T641
Test name
Test status
Simulation time 158624971270 ps
CPU time 202.09 seconds
Started Aug 18 05:42:48 PM PDT 24
Finished Aug 18 05:46:10 PM PDT 24
Peak memory 202136 kb
Host smart-e87c4ce9-771a-47be-87d8-9bdf0c8faa8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983493951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.983493951
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.298964688
Short name T732
Test name
Test status
Simulation time 478232881652 ps
CPU time 1090.76 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 06:01:15 PM PDT 24
Peak memory 202100 kb
Host smart-552cb68e-8bfe-46db-95cc-ec81f46e7818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298964688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.298964688
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.821400630
Short name T127
Test name
Test status
Simulation time 161253908959 ps
CPU time 43.03 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:43:25 PM PDT 24
Peak memory 202080 kb
Host smart-dc071277-2b48-4b54-8f2c-381b8c178cf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=821400630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.821400630
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2163712211
Short name T233
Test name
Test status
Simulation time 535194182352 ps
CPU time 664.47 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:54:06 PM PDT 24
Peak memory 201784 kb
Host smart-3245f328-da67-4b70-b3a1-745acc84dcbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163712211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2163712211
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1492222336
Short name T480
Test name
Test status
Simulation time 202895643850 ps
CPU time 106.19 seconds
Started Aug 18 05:43:17 PM PDT 24
Finished Aug 18 05:45:04 PM PDT 24
Peak memory 202112 kb
Host smart-8afbb657-fdae-4180-a102-b5f0813522db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492222336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1492222336
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3857947156
Short name T191
Test name
Test status
Simulation time 83131399211 ps
CPU time 463.34 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:50:27 PM PDT 24
Peak memory 202364 kb
Host smart-3812787f-7492-4193-842b-ae0a2be81c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857947156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3857947156
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3132342841
Short name T527
Test name
Test status
Simulation time 28514995899 ps
CPU time 5.87 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:43:08 PM PDT 24
Peak memory 201868 kb
Host smart-8d9f514f-6a2f-4572-85c5-b943909ff52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132342841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3132342841
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3252985689
Short name T663
Test name
Test status
Simulation time 2814492416 ps
CPU time 6.65 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:42:48 PM PDT 24
Peak memory 201928 kb
Host smart-1f7c3f5a-cd6e-4681-a03f-d80ff08ab226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252985689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3252985689
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2620284416
Short name T365
Test name
Test status
Simulation time 5996381102 ps
CPU time 4.34 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:01 PM PDT 24
Peak memory 201892 kb
Host smart-347c4b55-3d37-4ed4-87ae-f6dfc8af6330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620284416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2620284416
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3850183959
Short name T317
Test name
Test status
Simulation time 172001603554 ps
CPU time 382.5 seconds
Started Aug 18 05:42:35 PM PDT 24
Finished Aug 18 05:48:57 PM PDT 24
Peak memory 202128 kb
Host smart-d6ff4554-5707-4606-93c0-60db4d3d51ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850183959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3850183959
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2476994868
Short name T60
Test name
Test status
Simulation time 67249362927 ps
CPU time 28.89 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:43:15 PM PDT 24
Peak memory 210420 kb
Host smart-dabc6fa9-abdf-4419-9a0b-c75c3dd1d15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476994868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2476994868
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2998153392
Short name T482
Test name
Test status
Simulation time 477256666 ps
CPU time 1.65 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:42:48 PM PDT 24
Peak memory 201904 kb
Host smart-e7f7b61c-b3a4-4d42-b67a-74a59129aa75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998153392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2998153392
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1495417417
Short name T224
Test name
Test status
Simulation time 525898633272 ps
CPU time 852.58 seconds
Started Aug 18 05:42:30 PM PDT 24
Finished Aug 18 05:56:43 PM PDT 24
Peak memory 202128 kb
Host smart-87695ee1-b214-4c8a-bd8d-5dbaad167b3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495417417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1495417417
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1448082881
Short name T711
Test name
Test status
Simulation time 167660396068 ps
CPU time 343.46 seconds
Started Aug 18 05:42:38 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 202036 kb
Host smart-748bb07e-0b56-451f-aba6-bafd57a4a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448082881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1448082881
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1368160616
Short name T308
Test name
Test status
Simulation time 325537805478 ps
CPU time 766.8 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:55:44 PM PDT 24
Peak memory 202060 kb
Host smart-2f0bccd9-fb92-4032-b6bc-01bf4031a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368160616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1368160616
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.542468914
Short name T427
Test name
Test status
Simulation time 331984391974 ps
CPU time 806.93 seconds
Started Aug 18 05:42:58 PM PDT 24
Finished Aug 18 05:56:25 PM PDT 24
Peak memory 202044 kb
Host smart-534df6ff-89ea-48f5-8651-be07cc34eadd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=542468914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.542468914
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.34493931
Short name T329
Test name
Test status
Simulation time 167249112179 ps
CPU time 346.79 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 202116 kb
Host smart-ce0c66b4-fc2d-481b-9515-6e2d5ce07c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34493931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.34493931
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1769327074
Short name T662
Test name
Test status
Simulation time 480113853187 ps
CPU time 210.62 seconds
Started Aug 18 05:42:48 PM PDT 24
Finished Aug 18 05:46:19 PM PDT 24
Peak memory 202096 kb
Host smart-03090e11-e293-4049-8cf9-d66d458d60ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769327074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1769327074
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2405894204
Short name T777
Test name
Test status
Simulation time 194556673157 ps
CPU time 478.23 seconds
Started Aug 18 05:42:48 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 202048 kb
Host smart-abc371d7-e5e2-4755-815d-741fece36be0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405894204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2405894204
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3318073253
Short name T184
Test name
Test status
Simulation time 94888470166 ps
CPU time 322.42 seconds
Started Aug 18 05:42:57 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 202204 kb
Host smart-5e1ad694-c8e2-4dc6-a2b8-d14bb932289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318073253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3318073253
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.735451079
Short name T654
Test name
Test status
Simulation time 30469072554 ps
CPU time 66.63 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:43:57 PM PDT 24
Peak memory 201944 kb
Host smart-6ee8a059-b785-4e4e-a766-8dbc78728528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735451079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.735451079
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2267917282
Short name T613
Test name
Test status
Simulation time 5132288754 ps
CPU time 12.83 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:42:50 PM PDT 24
Peak memory 201944 kb
Host smart-eed824c7-48d3-45cd-94e6-b3e35b654e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267917282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2267917282
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.51086843
Short name T629
Test name
Test status
Simulation time 6021481751 ps
CPU time 13.94 seconds
Started Aug 18 05:42:36 PM PDT 24
Finished Aug 18 05:42:50 PM PDT 24
Peak memory 201968 kb
Host smart-8870a2d3-89e0-4a2b-b2ae-6a9c7ef7dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51086843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.51086843
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3148866239
Short name T183
Test name
Test status
Simulation time 244525754722 ps
CPU time 834.4 seconds
Started Aug 18 05:42:47 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 210444 kb
Host smart-6616fabf-55e4-4a04-b6da-09bdd3c7d934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148866239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3148866239
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.744597214
Short name T250
Test name
Test status
Simulation time 21800837569 ps
CPU time 28.76 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:43:21 PM PDT 24
Peak memory 210540 kb
Host smart-46ed635e-565a-4bb5-926d-70c04fb40d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744597214 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.744597214
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3710118499
Short name T566
Test name
Test status
Simulation time 538054520 ps
CPU time 0.93 seconds
Started Aug 18 05:43:14 PM PDT 24
Finished Aug 18 05:43:15 PM PDT 24
Peak memory 201944 kb
Host smart-88abec91-171a-4565-9e80-2c2b855cab80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710118499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3710118499
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2808477930
Short name T210
Test name
Test status
Simulation time 328222200370 ps
CPU time 732.88 seconds
Started Aug 18 05:42:39 PM PDT 24
Finished Aug 18 05:54:52 PM PDT 24
Peak memory 202100 kb
Host smart-d262a332-2db1-4f21-b7bc-ef281e0a5dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808477930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2808477930
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1087775703
Short name T247
Test name
Test status
Simulation time 165225461819 ps
CPU time 193.47 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:46:05 PM PDT 24
Peak memory 202060 kb
Host smart-006dc571-589a-4682-a658-3376b05326de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087775703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1087775703
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.640215722
Short name T426
Test name
Test status
Simulation time 332448138043 ps
CPU time 510.58 seconds
Started Aug 18 05:42:37 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 202116 kb
Host smart-a0515d5e-9073-49b1-81c1-c63732c5e6de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=640215722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.640215722
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.205337492
Short name T279
Test name
Test status
Simulation time 498919074125 ps
CPU time 147.66 seconds
Started Aug 18 05:42:52 PM PDT 24
Finished Aug 18 05:45:19 PM PDT 24
Peak memory 202048 kb
Host smart-517bda7b-19e1-4b53-86d1-c8debf40bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205337492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.205337492
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2835347990
Short name T391
Test name
Test status
Simulation time 490709952184 ps
CPU time 232.7 seconds
Started Aug 18 05:42:41 PM PDT 24
Finished Aug 18 05:46:34 PM PDT 24
Peak memory 202028 kb
Host smart-7c255212-cb62-45e0-bb27-6ae51bb12db2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835347990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2835347990
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.362717749
Short name T209
Test name
Test status
Simulation time 179086161626 ps
CPU time 404.49 seconds
Started Aug 18 05:42:55 PM PDT 24
Finished Aug 18 05:49:49 PM PDT 24
Peak memory 201980 kb
Host smart-ec88b037-fbb1-4f88-bc5f-f6b0d7f3ddab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362717749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.362717749
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3722060163
Short name T206
Test name
Test status
Simulation time 213681571313 ps
CPU time 511.15 seconds
Started Aug 18 05:42:48 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 202116 kb
Host smart-1db4fef8-4ce3-4425-84b3-082e05e6379c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722060163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3722060163
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.455993850
Short name T339
Test name
Test status
Simulation time 81566164975 ps
CPU time 416.45 seconds
Started Aug 18 05:42:53 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 202400 kb
Host smart-a1b60de0-5d8d-4ac9-a253-8e9a8b0ef917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455993850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.455993850
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2996734496
Short name T346
Test name
Test status
Simulation time 37519973773 ps
CPU time 83.22 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:44:06 PM PDT 24
Peak memory 201940 kb
Host smart-5afc3c3a-2353-4f01-9405-f953e1fe24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996734496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2996734496
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1555166443
Short name T597
Test name
Test status
Simulation time 3286292250 ps
CPU time 4.28 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:00 PM PDT 24
Peak memory 201936 kb
Host smart-f45641f8-fd4d-47bd-859e-dad18135f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555166443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1555166443
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1307859145
Short name T356
Test name
Test status
Simulation time 5798968269 ps
CPU time 15.57 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:43:05 PM PDT 24
Peak memory 201772 kb
Host smart-d29d0b37-4a36-4225-8717-90787aba92aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307859145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1307859145
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.148383296
Short name T441
Test name
Test status
Simulation time 5557277919 ps
CPU time 14.48 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:43:17 PM PDT 24
Peak memory 201908 kb
Host smart-f1ebea07-9dd4-4c58-bb96-4fa1fd2f16e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148383296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.148383296
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3117935459
Short name T260
Test name
Test status
Simulation time 8748884706 ps
CPU time 13.7 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:43:20 PM PDT 24
Peak memory 210768 kb
Host smart-66fd0251-f6c4-4d44-b21b-67f4bb7961b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117935459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3117935459
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3706062685
Short name T747
Test name
Test status
Simulation time 440111262 ps
CPU time 0.86 seconds
Started Aug 18 05:43:05 PM PDT 24
Finished Aug 18 05:43:06 PM PDT 24
Peak memory 201944 kb
Host smart-01f4f584-d797-480e-8402-cab402f3ae31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706062685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3706062685
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1217337350
Short name T215
Test name
Test status
Simulation time 517815069571 ps
CPU time 453.36 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:50:25 PM PDT 24
Peak memory 202148 kb
Host smart-1ac0d6f6-e711-41fa-88a8-bc38e242628c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217337350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1217337350
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1588342437
Short name T730
Test name
Test status
Simulation time 485743110606 ps
CPU time 1109.34 seconds
Started Aug 18 05:43:19 PM PDT 24
Finished Aug 18 06:01:49 PM PDT 24
Peak memory 202148 kb
Host smart-eee7d0a8-0b81-4744-ac36-dc6a5fe7f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588342437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1588342437
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1566891925
Short name T87
Test name
Test status
Simulation time 327504987771 ps
CPU time 734.1 seconds
Started Aug 18 05:43:11 PM PDT 24
Finished Aug 18 05:55:25 PM PDT 24
Peak memory 202084 kb
Host smart-038b5cb1-1baa-4855-afc4-3e6cfa939468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566891925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1566891925
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2981711356
Short name T28
Test name
Test status
Simulation time 160092123593 ps
CPU time 30.36 seconds
Started Aug 18 05:43:06 PM PDT 24
Finished Aug 18 05:43:36 PM PDT 24
Peak memory 202128 kb
Host smart-13cd478e-0354-46a7-ae8a-d8a0d786a74a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981711356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2981711356
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.830706950
Short name T467
Test name
Test status
Simulation time 497441201052 ps
CPU time 450.45 seconds
Started Aug 18 05:42:45 PM PDT 24
Finished Aug 18 05:50:16 PM PDT 24
Peak memory 201940 kb
Host smart-3abfcfee-d958-4219-9426-d1a95755857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830706950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.830706950
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2387000041
Short name T462
Test name
Test status
Simulation time 331812556642 ps
CPU time 200.03 seconds
Started Aug 18 05:43:09 PM PDT 24
Finished Aug 18 05:46:33 PM PDT 24
Peak memory 202028 kb
Host smart-f3c16607-8ba3-4b19-ae2b-2865a68eea64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387000041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2387000041
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2178225307
Short name T327
Test name
Test status
Simulation time 382172488416 ps
CPU time 214.63 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 202084 kb
Host smart-5bc13bcb-6264-4a9e-aece-bae9d9811ba0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178225307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2178225307
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1338917580
Short name T793
Test name
Test status
Simulation time 404854077052 ps
CPU time 955.1 seconds
Started Aug 18 05:43:00 PM PDT 24
Finished Aug 18 05:58:56 PM PDT 24
Peak memory 202096 kb
Host smart-580fa441-369b-40b9-9aaa-d3b898fdc469
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338917580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1338917580
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1077421975
Short name T550
Test name
Test status
Simulation time 86991832318 ps
CPU time 309.2 seconds
Started Aug 18 05:43:18 PM PDT 24
Finished Aug 18 05:48:27 PM PDT 24
Peak memory 202360 kb
Host smart-19a4d817-aa1b-4f7e-b1d0-b7a6edb8d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077421975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1077421975
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.912974093
Short name T144
Test name
Test status
Simulation time 25012357782 ps
CPU time 38.34 seconds
Started Aug 18 05:42:56 PM PDT 24
Finished Aug 18 05:43:34 PM PDT 24
Peak memory 201932 kb
Host smart-3fafea3a-7d1d-455a-bac7-da9285004724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912974093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.912974093
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1159916009
Short name T348
Test name
Test status
Simulation time 4088721800 ps
CPU time 2.92 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:42:54 PM PDT 24
Peak memory 201928 kb
Host smart-d3fc6b4d-d0f7-4d87-aca8-15280d3ab4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159916009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1159916009
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1910146375
Short name T502
Test name
Test status
Simulation time 6106063681 ps
CPU time 2.19 seconds
Started Aug 18 05:43:12 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 201824 kb
Host smart-d74620ed-299a-4402-93a1-7fecee6e1990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910146375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1910146375
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3390059311
Short name T720
Test name
Test status
Simulation time 2285044264 ps
CPU time 5.67 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:42:57 PM PDT 24
Peak memory 202092 kb
Host smart-0fe37c86-eeb8-41e5-a9b7-f1da19a303b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390059311 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3390059311
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1700627033
Short name T718
Test name
Test status
Simulation time 532247236 ps
CPU time 1.2 seconds
Started Aug 18 05:42:43 PM PDT 24
Finished Aug 18 05:42:44 PM PDT 24
Peak memory 201964 kb
Host smart-c08cbaac-be09-4448-a205-f8110d271513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700627033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1700627033
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.175445698
Short name T126
Test name
Test status
Simulation time 325890012485 ps
CPU time 405.96 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:49:57 PM PDT 24
Peak memory 202096 kb
Host smart-2731d2eb-7f62-4289-b04f-909e3f5dd08d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175445698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.175445698
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4089463846
Short name T699
Test name
Test status
Simulation time 194545329297 ps
CPU time 418.8 seconds
Started Aug 18 05:42:58 PM PDT 24
Finished Aug 18 05:49:57 PM PDT 24
Peak memory 202160 kb
Host smart-60337e11-1265-4212-a76f-cc1de3b09c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089463846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4089463846
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1112785091
Short name T757
Test name
Test status
Simulation time 167905815028 ps
CPU time 197.96 seconds
Started Aug 18 05:42:46 PM PDT 24
Finished Aug 18 05:46:04 PM PDT 24
Peak memory 202032 kb
Host smart-fb04da06-c5ad-4605-b2df-45743774f7e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112785091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1112785091
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2408099500
Short name T463
Test name
Test status
Simulation time 168181380246 ps
CPU time 95.6 seconds
Started Aug 18 05:42:51 PM PDT 24
Finished Aug 18 05:44:27 PM PDT 24
Peak memory 201936 kb
Host smart-26b7ff5c-4388-468a-a5dc-3d3f862cdaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408099500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2408099500
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.143879627
Short name T394
Test name
Test status
Simulation time 319075293836 ps
CPU time 365.97 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:49:19 PM PDT 24
Peak memory 202080 kb
Host smart-cdb79620-d827-42e1-a7a5-46738c0a2f92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=143879627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.143879627
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3661308517
Short name T162
Test name
Test status
Simulation time 550297744031 ps
CPU time 325.24 seconds
Started Aug 18 05:42:44 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 202064 kb
Host smart-0350ddc4-5abf-4371-9227-c353fbc5ffd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661308517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3661308517
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3695561836
Short name T417
Test name
Test status
Simulation time 425856267588 ps
CPU time 144.09 seconds
Started Aug 18 05:43:03 PM PDT 24
Finished Aug 18 05:45:28 PM PDT 24
Peak memory 202008 kb
Host smart-28d6f078-bc87-4233-ae71-f93ebdee7ced
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695561836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3695561836
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1961008395
Short name T192
Test name
Test status
Simulation time 99570979679 ps
CPU time 307.56 seconds
Started Aug 18 05:43:10 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 202364 kb
Host smart-cb7a3a8f-fc12-4ac4-a438-eba2ceb9e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961008395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1961008395
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3919003614
Short name T374
Test name
Test status
Simulation time 34399767989 ps
CPU time 19.74 seconds
Started Aug 18 05:42:49 PM PDT 24
Finished Aug 18 05:43:09 PM PDT 24
Peak memory 201940 kb
Host smart-026c7300-4dd7-44eb-b9f4-9e529b79d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919003614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3919003614
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.397656171
Short name T479
Test name
Test status
Simulation time 2695622632 ps
CPU time 7.48 seconds
Started Aug 18 05:43:01 PM PDT 24
Finished Aug 18 05:43:09 PM PDT 24
Peak memory 201916 kb
Host smart-469088e0-e4ef-49c3-9f97-ab5f11f1c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397656171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.397656171
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3658903030
Short name T716
Test name
Test status
Simulation time 6263285283 ps
CPU time 4.62 seconds
Started Aug 18 05:43:13 PM PDT 24
Finished Aug 18 05:43:18 PM PDT 24
Peak memory 201912 kb
Host smart-d0e5e6a6-3cc5-4708-bfb4-3445175178cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658903030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3658903030
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3539509402
Short name T335
Test name
Test status
Simulation time 459367265752 ps
CPU time 904.17 seconds
Started Aug 18 05:43:02 PM PDT 24
Finished Aug 18 05:58:06 PM PDT 24
Peak memory 210532 kb
Host smart-74be9bcf-355c-4bb2-b7a2-e05f07351c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539509402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3539509402
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1766749161
Short name T780
Test name
Test status
Simulation time 31761236510 ps
CPU time 9.69 seconds
Started Aug 18 05:43:04 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 212008 kb
Host smart-58570398-08d7-462e-ad10-3597a37a5f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766749161 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1766749161
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%