Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5582	1			T3	6		T7	71		T9	107
testmodes[AdcCtrlTestmodeNormal]	4860	1			T1	2		T2	2		T7	58
testmodes[AdcCtrlTestmodeLowpower]	4865	1			T3	2		T5	1		T6	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2842	1			T3	4		T7	39		T9	30
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1474	1			T7	17		T9	41		T12	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1158	1			T3	2		T7	14		T9	36
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1471	1			T7	14		T9	37		T31	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1835	1			T1	1		T2	1		T7	25
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1213	1			T7	19		T9	33		T31	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1145	1			T3	1		T7	18		T9	40
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1230	1			T7	16		T9	29		T31	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2239	1			T6	2		T7	21		T9	27