Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19681

1

T1

1

T2

2

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3299

1

T1

1

T6

33

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17289

1

T3

10

T6

19

T7

184

auto[1]

5691

1

T1

2

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T203	3		-	-		-	-
values[0]	15	1			T1	1		T81	1		T204	13
values[1]	484	1			T8	17		T9	19		T10	11
values[2]	596	1			T93	15		T165	9		T137	1
values[3]	623	1			T7	1		T9	1		T11	2
values[4]	2869	1			T2	2		T5	15		T21	37
values[5]	582	1			T10	12		T122	1		T137	1
values[6]	801	1			T29	21		T30	19		T93	12
values[7]	745	1			T1	1		T11	2		T122	1
values[8]	674	1			T6	19		T161	16		T123	5
values[9]	1160	1			T3	3		T6	14		T30	19
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T1	1		T8	17		T9	19
values[1]	625	1			T9	1		T12	3		T144	32
values[2]	601	1			T7	1		T11	2		T29	51
values[3]	2778	1			T2	2		T5	15		T21	37
values[4]	754	1			T10	12		T29	21		T30	8
values[5]	698	1			T30	11		T93	12		T119	8
values[6]	656	1			T1	1		T11	2		T122	1
values[7]	698	1			T6	19		T120	5		T123	5
values[8]	857	1			T3	3		T6	14		T30	19
values[9]	189	1			T136	5		T205	13		T206	18
minimum	14455	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	1		T8	1		T9	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	11		T11	11		T165	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	1		T12	2		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T175	11		T22	1		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	12		T139	1		T207	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T11	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T2	2		T5	15		T21	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T173	1		T130	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T30	8		T138	13		T208	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	12		T29	11		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	11		T25	3		T209	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T93	1		T119	8		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T126	8		T146	1		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T11	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T120	1		T123	5		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	19		T140	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	2		T119	4		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	14		T30	19		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T136	1		T205	13		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T206	1		T181	6		T69	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14329	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T67	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	16		T9	14		T93	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	13		T153	12		T128	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T144	15		T141	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T175	11		T23	6		T66	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	14		T139	13		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T29	13		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T143	32		T159	9		T94	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T173	10		T130	9		T156	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	2		T208	14		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	10		T119	10		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T209	12		T22	7		T212	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T93	11		T139	14		T92	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T126	4		T27	1		T213	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T11	1		T124	8		T126	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	4		T152	2		T147	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T147	3		T214	14		T215	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T119	7		T181	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T93	2		T26	2		T129	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T136	4		T206	10		T216	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T206	6		T181	5		T217	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T67	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T203	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T1	1		T81	1		T204	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T8	1		T9	5		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	11		T11	11		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T93	1		T137	1		T161	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	9		T153	13		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	1		T174	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T11	1		T29	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T2	2		T5	15		T21	37
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T173	1		T130	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T122	1		T137	1		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	12		T126	23		T156	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T30	19		T209	14		T90	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	11		T93	1		T119	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T25	3		T146	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T11	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T123	5		T126	8		T179	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	19		T161	16		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	2		T119	4		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T6	14		T30	19		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T204	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	16		T9	14		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	13		T128	10		T84	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T93	14		T144	15		T141	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T153	12		T152	8		T175	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T210	4		T216	7		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	1		T29	13		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T29	14		T143	32		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T173	10		T130	9		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T138	2		T208	14		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T126	5		T156	27		T68	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T209	12		T90	18		T22	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	10		T93	11		T119	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T27	1		T213	5		T67	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T139	14		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T126	4		T147	15		T214	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T126	11		T174	11		T214	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	1		T119	7		T136	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T93	2		T26	2		T206	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	1		T8	17		T9	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	1		T11	14		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T12	2		T144	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T175	12		T22	1		T23	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	15		T139	14		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T11	2		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T2	2		T5	1		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T173	11		T130	10		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	1		T138	3		T208	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T29	11		T119	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	1		T25	3		T209	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T93	12		T119	1		T139	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T126	5		T146	1		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T11	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T120	5		T123	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	2		T140	1		T147	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	2		T119	8		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T30	1		T93	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T136	5		T205	1		T206	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T206	7		T181	6		T69	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14452	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T67	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T9	4		T161	9		T63	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	10		T11	10		T165	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	1		T144	16		T141	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T175	10		T219	14		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T29	11		T207	9		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	11		T157	11		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T5	14		T21	34		T117	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T153	7		T220	2		T221	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	7		T138	12		T208	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	11		T29	10		T119	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	10		T209	13		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T119	7		T123	13		T125	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T126	7		T27	1		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T161	15		T140	10		T124	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T123	4		T179	2		T223	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	17		T140	2		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T119	3		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	13		T30	18		T123	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T205	12		T149	15		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T181	5		T217	8		T224	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T203	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T1	1		T81	1		T204	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	17		T9	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	1		T11	14		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T93	15		T137	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T165	1		T153	13		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T174	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	1		T11	2		T29	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	2		T5	1		T21	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T173	11		T130	10		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T122	1		T137	1		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T126	6		T156	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T30	2		T209	13		T90	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	11		T93	12		T119	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	3		T146	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T11	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	1		T126	5		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	2		T161	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T3	2		T119	8		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T6	1		T30	1		T93	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T203	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T204	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T9	4		T12	1		T63	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	10		T11	10		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T161	9		T144	16		T141	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T165	8		T153	12		T152	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T210	4		T63	6		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T29	11		T157	11		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T5	14		T21	34		T29	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	7		T220	2		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T138	12		T208	6		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T126	22		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	17		T209	13		T90	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	10		T119	14		T161	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	1		T176	4		T226	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T124	8		T125	7		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T123	4		T126	7		T179	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	17		T161	15		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	1		T119	3		T205	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	13		T30	18		T123	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17317

1

T1

1

T3

10

T6

12

auto[ADC_CTRL_FILTER_COND_OUT]

5663

1

T1

1

T2

2

T5

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17119

1

T1

1

T3

10

T6

19

auto[1]

5861

1

T1

1

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T10	12		T228	10		T229	12
values[0]	26	1			T214	8		T230	2		T229	16
values[1]	693	1			T9	19		T29	46		T117	29
values[2]	555	1			T1	1		T11	2		T30	8
values[3]	696	1			T8	17		T11	24		T93	15
values[4]	469	1			T1	1		T9	1		T10	11
values[5]	720	1			T6	7		T7	1		T30	19
values[6]	796	1			T3	3		T12	3		T173	11
values[7]	719	1			T119	18		T122	1		T126	28
values[8]	784	1			T6	14		T165	9		T13	1
values[9]	3060	1			T2	2		T5	15		T6	12
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	782	1			T9	19		T29	46		T117	29
values[1]	2861	1			T1	1		T2	2		T5	15
values[2]	649	1			T1	1		T9	1		T10	11
values[3]	486	1			T6	7		T30	19		T121	1
values[4]	612	1			T7	1		T119	8		T136	5
values[5]	842	1			T3	3		T12	3		T173	11
values[6]	801	1			T165	9		T119	18		T120	5
values[7]	673	1			T6	14		T30	11		T13	1
values[8]	626	1			T6	12		T10	12		T11	2
values[9]	180	1			T231	2		T232	29		T151	1
minimum	14468	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	5		T29	12		T138	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T29	11		T117	14		T208	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T8	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1651	1			T2	2		T5	15		T21	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	1		T11	11		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	1		T10	11		T93	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	4		T174	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	7		T30	19		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T119	8		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	1		T123	20		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	2		T173	1		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	2		T207	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T119	8		T120	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T165	9		T233	1		T209	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	11		T13	1		T126	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	14		T139	1		T128	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	12		T11	1		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	12		T29	12		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T231	1		T232	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T232	12		T234	1		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14341	1			T3	7		T7	183		T9	307
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	14		T29	13		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T29	10		T117	15		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	16		T11	1		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	942	1			T143	32		T159	9		T94	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	13		T93	14		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T93	13		T181	5		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	2		T63	7		T67	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T23	6		T236	5		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T136	4		T130	9		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T90	18		T92	3		T216	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T173	10		T119	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T156	15		T67	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T119	10		T120	4		T126	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T209	12		T157	12		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T126	4		T220	5		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T139	14		T128	19		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T144	15		T206	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	14		T124	8		T92	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T231	1		T232	1		T238	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T232	15		T239	12		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	3		T25	2		T156	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T228	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T10	12		T229	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T214	3		T230	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	5		T29	12		T138	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T29	11		T117	14		T208	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	1		T11	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	8		T207	10		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T8	1		T11	11		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T93	2		T125	8		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T93	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T10	11		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	1		T136	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	7		T30	19		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	2		T173	1		T119	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	2		T207	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	8		T122	1		T126	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T209	14		T158	1		T179	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T126	15		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	14		T165	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	12		T11	1		T30	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1655	1			T2	2		T5	15		T21	37
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T228	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T214	5		T230	1		T229	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T9	14		T29	13		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	10		T117	15		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T156	12		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T241	9		T148	2		T242	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	16		T11	13		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T93	13		T27	1		T181	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T93	14		T153	12		T213	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T23	6		T236	5		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	4		T139	13		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T90	18		T92	3		T216	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T173	10		T119	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T156	15		T22	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T119	10		T126	5		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T209	12		T227	13		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T126	11		T231	13		T170	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	14		T157	12		T128	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T144	15		T126	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	975	1			T29	14		T143	32		T159	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4