Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19380

1

T1

1

T2

2

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3600

1

T1

1

T6

19

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17542

1

T1

2

T3

7

T6

7

auto[1]

5438

1

T2

2

T3

3

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T266	1		T248	22		-	-
values[0]	75	1			T252	15		T280	4		T312	15
values[1]	795	1			T6	26		T9	19		T29	51
values[2]	521	1			T10	12		T11	2		T29	21
values[3]	721	1			T137	1		T123	20		T140	3
values[4]	591	1			T1	1		T3	3		T6	7
values[5]	581	1			T136	5		T121	1		T141	5
values[6]	664	1			T11	2		T30	8		T117	29
values[7]	434	1			T1	1		T10	11		T93	3
values[8]	2851	1			T2	2		T5	15		T11	24
values[9]	1296	1			T7	1		T8	17		T9	1
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	964	1			T6	26		T9	19		T29	51
values[1]	645	1			T10	12		T11	2		T30	19
values[2]	565	1			T3	3		T29	21		T137	1
values[3]	553	1			T1	1		T93	15		T119	18
values[4]	746	1			T6	7		T30	8		T117	29
values[5]	586	1			T10	11		T11	2		T93	3
values[6]	2673	1			T1	1		T2	2		T5	15
values[7]	606	1			T12	3		T30	11		T165	9
values[8]	914	1			T7	1		T137	1		T138	15
values[9]	271	1			T8	17		T9	1		T144	32
minimum	14457	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	14		T9	5		T29	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	12		T29	12		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	12		T30	19		T123	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	1		T173	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	2		T137	1		T140	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	11		T125	11		T214	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T122	1		T124	9		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T93	1		T119	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	8		T136	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	7		T117	14		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T93	1		T117	1		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	11		T11	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T1	1		T2	2		T5	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	1		T161	10		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T165	9		T161	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	11		T139	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T137	1		T140	11		T129	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T7	1		T138	13		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T153	13		T92	2		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T8	1		T9	1		T144	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14335	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T123	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	14		T29	13		T120	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	14		T93	11		T211	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T208	14		T250	2		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T173	10		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T3	1		T126	5		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T29	10		T214	5		T23	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T124	8		T27	1		T256	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T93	14		T119	10		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	4		T209	12		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T117	15		T119	7		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T93	2		T156	15		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T213	5		T220	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T11	13		T143	32		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T130	9		T156	12		T152	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	1		T156	13		T147	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	14		T175	11		T260	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T129	7		T214	14		T67	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T138	2		T206	10		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T153	12		T92	12		T22	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	16		T144	15		T128	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	3		T25	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T252	15		T312	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T280	4		T275	9		T249	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	14		T9	5		T29	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	12		T29	12		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	12		T30	19		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T29	11		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T137	1		T123	20		T140	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T125	11		T126	15		T214	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	2		T122	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T6	7		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T136	1		T209	14		T179	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T121	1		T141	2		T90	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	8		T132	1		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T117	14		T119	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	1		T93	1		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T130	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T2	2		T5	15		T11	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T30	11		T139	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T165	9		T137	1		T161	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T7	1		T8	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T248	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T275	7		T317	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	14		T29	13		T126	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	14		T93	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T120	4		T208	14		T232	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T29	10		T173	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T124	8		T126	5		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T126	11		T214	5		T150	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	1		T27	1		T256	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	14		T119	10		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T136	4		T209	12		T63	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	3		T90	33		T92	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	5		T84	5		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	1		T117	15		T119	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T93	2		T156	15		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T130	9		T152	1		T147	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T11	13		T12	1		T143	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	14		T156	12		T175	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T153	12		T129	7		T92	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T8	16		T138	2		T144	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	1		T9	15		T29	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	1		T29	15		T93	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	1		T30	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	2		T173	11		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	2		T137	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	11		T125	1		T214	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T122	1		T124	9		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T93	15		T119	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	1		T136	5		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T117	16		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T93	3		T117	1		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	1		T11	2		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T1	1		T2	2		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T130	10		T161	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	2		T165	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T30	1		T139	15		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T137	1		T140	1		T129	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T7	1		T138	3		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T153	13		T92	14		T22	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T8	17		T9	1		T144	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14445	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T123	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	13		T9	4		T29	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	11		T29	11		T119	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	11		T30	18		T123	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T126	14		T142	1		T172	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	1		T140	2		T126	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	10		T125	10		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T124	8		T27	1		T256	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T119	7		T207	9		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	7		T209	13		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	6		T117	13		T119	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T123	13		T153	7		T219	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	10		T140	8		T246	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T5	14		T11	10		T21	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T161	9		T156	13		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T165	8		T161	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T30	10		T175	10		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	10		T129	6		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T138	12		T157	11		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T153	12		T63	6		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	16		T127	9		T128	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T265	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T123	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T252	1		T312	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T280	1		T275	8		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T9	15		T29	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T29	15		T93	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	1		T30	1		T120	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T29	11		T173	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	1		T123	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T125	1		T126	12		T214	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	2		T122	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T6	1		T93	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T136	5		T209	13		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T121	1		T141	4		T90	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	1		T132	1		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	2		T117	16		T119	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T93	3		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T130	10		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	2		T5	1		T11	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	1		T139	15		T156	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T165	1		T137	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T7	1		T8	17		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T252	14		T312	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T280	3		T275	8		T249	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	13		T9	4		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	11		T29	11		T119	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	11		T30	18		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T29	10		T142	1		T204	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T123	19		T140	2		T124	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	10		T126	14		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T3	1		T27	1		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	6		T119	7		T207	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T209	13		T179	2		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	1		T90	26		T244	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	7		T123	13		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T117	13		T119	3		T161	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T161	7		T149	4		T76	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	10		T16	2		T246	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T5	14		T11	10		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	10		T156	13		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T165	8		T161	15		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T138	12		T144	16		T127	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30