Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19355

1

T1

2

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3625

1

T3

3

T6

33

T9

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17405

1

T1

1

T3

8

T6

19

auto[1]

5575

1

T1

1

T2

2

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	478	1			T3	2		T7	3		T9	19
values[0]	6	1			T267	2		T270	1		T224	3
values[1]	737	1			T10	11		T29	26		T146	1
values[2]	2749	1			T2	2		T5	15		T6	12
values[3]	921	1			T6	7		T8	17		T9	1
values[4]	566	1			T3	3		T11	26		T30	11
values[5]	585	1			T1	1		T6	14		T7	1
values[6]	576	1			T1	1		T122	1		T25	3
values[7]	577	1			T9	19		T10	12		T119	11
values[8]	812	1			T29	21		T93	3		T173	11
values[9]	850	1			T119	8		T130	10		T122	1
minimum	14123	1			T3	5		T7	180		T9	288

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	590	1			T10	11		T29	26		T146	1
values[1]	2833	1			T2	2		T5	15		T6	12
values[2]	756	1			T6	7		T8	17		T11	2
values[3]	602	1			T3	3		T6	14		T11	24
values[4]	620	1			T1	1		T7	1		T30	19
values[5]	520	1			T1	1		T119	11		T122	1
values[6]	649	1			T9	19		T10	12		T29	21
values[7]	713	1			T173	11		T13	1		T144	32
values[8]	856	1			T119	8		T130	10		T122	1
values[9]	83	1			T23	7		T268	1		T266	1
minimum	14758	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	11		T29	12		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T175	2		T227	10		T70	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T2	2		T5	15		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	12		T12	2		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T93	1		T117	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	7		T11	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	11		T117	1		T119	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	2		T6	14		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T7	1		T161	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	19		T158	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T1	1		T119	4		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T122	1		T125	8		T127	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	12		T123	14		T208	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	5		T29	11		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T206	1		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T173	1		T144	17		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T138	13		T233	1		T128	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T119	8		T130	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T238	1		T269	13		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T23	1		T268	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14421	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T209	14		T215	9		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	14		T206	10		T128	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T227	13		T260	13		T215	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T11	1		T143	32		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T147	3		T214	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	16		T93	14		T117	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T29	13		T129	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	13		T119	10		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	1		T139	13		T124	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	2		T216	12		T63	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	15		T148	2		T219	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T119	7		T150	7		T278	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T213	5		T250	2		T305	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T208	14		T156	12		T92	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	14		T29	10		T93	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T206	6		T84	5		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T173	10		T144	15		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T138	2		T128	10		T92	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T130	9		T156	15		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T238	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T23	6		T168	10		T277	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T209	12		T215	8		T238	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T3	2		T7	3		T9	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T161	16		T15	2		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T270	1		T224	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	11		T29	12		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T209	14		T175	1		T227	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T2	2		T5	15		T21	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	12		T12	2		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	1		T9	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	7		T29	12		T129	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	11		T117	1		T119	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	2		T11	1		T30	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T7	1		T123	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	14		T30	19		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	1		T25	3		T161	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T122	1		T125	8		T127	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	12		T119	4		T208	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	5		T120	1		T123	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T123	14		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T29	11		T93	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T138	13		T128	11		T84	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T119	8		T130	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14022	1			T3	5		T7	180		T9	288
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T92	3		T168	4		T318	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T294	11		T319	9		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	14		T206	10		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T209	12		T227	13		T260	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	881	1			T143	32		T159	9		T94	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	1		T147	3		T305	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	16		T11	1		T93	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T29	13		T129	7		T90	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	13		T119	10		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	1		T11	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	2		T216	12		T63	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T219	4		T231	1		T150	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T150	7		T278	1		T279	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	15		T213	5		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T119	7		T208	14		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	14		T120	4		T153	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	6		T181	5		T212	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	10		T93	2		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	2		T128	10		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T130	9		T156	28		T141	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	1		T29	15		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T175	2		T227	14		T70	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T2	2		T5	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T12	2		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	17		T93	15		T117	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	1		T11	2		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	14		T117	1		T119	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	2		T6	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T7	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T158	1		T147	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	1		T119	8		T25	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	1		T125	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	1		T123	1		T208	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	15		T29	11		T93	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T206	7		T84	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T173	11		T144	16		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T138	3		T233	1		T128	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T119	1		T130	10		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T238	6		T269	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T23	7		T268	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14501	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T209	13		T215	9		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	10		T29	11		T128	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T227	9		T215	17		T290	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T5	14		T21	34		T126	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	11		T12	1		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T117	13		T207	9		T126	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	6		T29	11		T30	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	10		T119	7		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T6	13		T165	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T161	9		T123	4		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	18		T219	6		T251	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T119	3		T150	9		T278	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T125	7		T127	12		T264	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	11		T123	13		T208	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	4		T29	10		T123	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T212	2		T219	6		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T144	16		T211	10		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	12		T128	10		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T119	7		T161	15		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T269	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T168	17		T284	2		T285	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T157	11		T179	2		T256	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T209	13		T215	8		T267	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T3	2		T7	3		T9	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T161	1		T15	1		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T267	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T270	1		T224	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	1		T29	15		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T209	13		T175	1		T227	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T2	2		T5	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T12	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T8	17		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	1		T29	14		T129	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	14		T117	1		T119	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	2		T11	2		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T7	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	1		T30	1		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T1	1		T25	3		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	1		T125	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T119	8		T208	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	15		T120	5		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T123	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	11		T93	3		T173	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	3		T128	11		T84	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T119	1		T130	10		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14123	1			T3	5		T7	180		T9	288
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T269	12		T168	10		T274	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T161	15		T15	1		T273	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T224	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	10		T29	11		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T209	13		T227	9		T215	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T5	14		T21	34		T126	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	11		T12	1		T30	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T117	13		T207	9		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	6		T29	11		T129	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T11	10		T119	7		T126	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T30	10		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T123	4		T140	8		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	13		T30	18		T246	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T161	9		T150	9		T278	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T125	7		T127	12		T250	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T10	11		T119	3		T208	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	4		T123	19		T153	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T123	13		T140	2		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T29	10		T144	16		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T138	12		T128	10		T220	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T119	7		T156	12		T141	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30