Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19688

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3292

1

T1

1

T3

3

T6

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17450

1

T3

10

T6

12

T7

183

auto[1]

5530

1

T1

2

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	171	1			T137	1		T125	11		T152	21
values[0]	17	1			T11	2		T252	15		-	-
values[1]	630	1			T30	11		T121	1		T25	3
values[2]	664	1			T3	3		T10	12		T93	15
values[3]	715	1			T6	12		T7	1		T29	21
values[4]	772	1			T1	1		T9	19		T10	11
values[5]	2780	1			T1	1		T2	2		T5	15
values[6]	741	1			T117	29		T120	5		T139	15
values[7]	671	1			T8	17		T29	25		T93	3
values[8]	651	1			T12	3		T119	18		T137	1
values[9]	740	1			T6	21		T9	1		T173	11
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	595	1			T30	11		T130	10		T121	1
values[1]	711	1			T3	3		T7	1		T10	12
values[2]	689	1			T1	1		T6	12		T11	2
values[3]	2981	1			T2	2		T5	15		T9	19
values[4]	611	1			T1	1		T11	24		T165	9
values[5]	715	1			T8	17		T117	29		T120	5
values[6]	765	1			T29	25		T93	3		T119	18
values[7]	492	1			T9	1		T12	3		T137	1
values[8]	691	1			T6	7		T173	11		T119	11
values[9]	118	1			T6	14		T119	8		T123	5
minimum	14612	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T30	11		T140	11		T127	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	1		T121	1		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	12		T132	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	2		T7	1		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T6	12		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	11		T30	19		T161	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T2	2		T5	15		T9	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	11		T93	1		T144	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	11		T165	9		T211	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T207	10		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T120	1		T161	10		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T117	14		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T93	1		T119	8		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	12		T122	1		T90	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T137	1		T123	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	2		T138	13		T126	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	1		T139	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	7		T173	1		T119	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T119	8		T126	23		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T6	14		T123	5		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14398	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T11	1		T231	1		T267	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T153	5		T241	9		T149	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T130	9		T214	5		T254	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T208	14		T213	5		T256	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T93	14		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T136	4		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	10		T152	1		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T9	14		T29	14		T143	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T93	11		T144	15		T126	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	13		T211	10		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T156	12		T147	4		T321	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T120	4		T124	8		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	16		T117	15		T139	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T93	2		T119	10		T206	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T29	13		T90	15		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T129	7		T181	10		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	1		T138	2		T126	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T139	13		T152	8		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T173	10		T119	7		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T126	5		T176	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T92	9		T210	4		T204	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T11	1		T231	1		T267	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	1		T125	11		T152	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T92	1		T252	9		T212	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T252	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T30	11		T140	11		T127	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T121	1		T25	3		T214	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	12		T132	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	2		T93	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	12		T117	1		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	1		T29	11		T30	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T9	5		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	11		T93	1		T144	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T2	2		T5	15		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T206	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T120	1		T124	9		T141	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T117	14		T139	1		T207	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T93	1		T122	1		T161	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T29	12		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T119	8		T137	1		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	2		T138	13		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	1		T119	8		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	21		T173	1		T119	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T152	8		T204	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T92	9		T212	5		T210	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T11	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	5		T241	9		T67	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T214	5		T255	14		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	12		T213	5		T256	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T93	14		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T208	14		T27	1		T84	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	10		T156	13		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	14		T11	1		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T93	11		T144	15		T126	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T11	13		T143	32		T159	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T147	4		T237	8		T176	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	4		T124	8		T141	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T117	15		T139	14		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T93	2		T206	6		T128	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	16		T29	13		T90	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	10		T129	7		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	1		T138	2		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T139	13		T126	5		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T173	10		T119	7		T126	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T30	1		T140	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	10		T121	1		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	1		T132	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	2		T7	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T6	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	11		T30	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	2		T5	1		T9	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	1		T93	12		T144	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	14		T165	1		T211	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T207	1		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T120	5		T161	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	17		T117	16		T139	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T93	3		T119	11		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	14		T122	1		T90	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	1		T137	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T138	3		T126	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	1		T139	14		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	1		T173	11		T119	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T119	1		T126	6		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T6	1		T123	1		T92	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14485	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T11	2		T231	2		T267	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T30	10		T140	10		T127	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T247	10		T214	2		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T10	11		T208	6		T256	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T30	7		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	11		T161	15		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	10		T30	18		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T5	14		T9	4		T21	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	10		T144	16		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	10		T165	8		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T207	9		T156	13		T264	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T161	9		T124	8		T63	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	13		T125	7		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T119	7		T128	10		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	11		T90	9		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T123	13		T129	6		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	1		T138	12		T126	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T125	10		T152	12		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	6		T119	3		T123	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T119	7		T126	22		T176	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T6	13		T123	4		T210	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T127	9		T322	14		T299	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T267	11		T323	6		T315	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T137	1		T125	1		T152	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T92	10		T252	1		T212	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T11	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	1		T140	1		T127	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T121	1		T25	3		T214	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	1		T132	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	2		T93	15		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T117	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T29	11		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T9	15		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	1		T93	12		T144	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	2		T5	1		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	1		T206	1		T147	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	5		T124	9		T141	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T117	16		T139	15		T207	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T93	3		T122	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	17		T29	14		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T119	11		T137	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	2		T138	3		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T119	1		T139	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	2		T173	11		T119	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T125	10		T152	12		T246	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T252	8		T212	2		T210	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T252	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T30	10		T140	10		T127	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T214	2		T255	9		T231	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T10	11		T153	12		T256	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T128	4		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	11		T161	15		T208	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	10		T30	25		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	4		T29	11		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	10		T144	16		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T5	14		T11	10		T21	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T264	14		T237	1		T176	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T124	8		T141	1		T76	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T117	13		T207	9		T125	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T161	9		T128	10		T63	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	11		T90	9		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T119	7		T123	13		T129	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T138	12		T255	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	7		T126	22		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	19		T119	3		T123	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30