Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19497

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3483

1

T1

1

T3

3

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17599

1

T1

2

T3

7

T6

7

auto[1]

5381

1

T2

2

T3

3

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	311	1			T138	15		T140	11		T153	25
values[0]	35	1			T252	15		T255	20		-	-
values[1]	819	1			T6	26		T9	19		T29	51
values[2]	505	1			T10	12		T30	19		T173	11
values[3]	745	1			T11	2		T29	21		T137	1
values[4]	622	1			T1	1		T3	3		T93	15
values[5]	613	1			T6	7		T117	29		T136	5
values[6]	599	1			T11	2		T30	8		T117	1
values[7]	477	1			T1	1		T10	11		T93	3
values[8]	2786	1			T2	2		T5	15		T11	24
values[9]	1040	1			T7	1		T8	17		T9	1
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T9	19		T93	12		T119	8
values[1]	627	1			T10	12		T11	2		T30	19
values[2]	564	1			T29	21		T93	15		T137	1
values[3]	585	1			T1	1		T3	3		T119	18
values[4]	764	1			T6	7		T30	8		T117	29
values[5]	530	1			T10	11		T11	2		T93	3
values[6]	2710	1			T1	1		T2	2		T5	15
values[7]	599	1			T12	3		T30	11		T165	9
values[8]	1033	1			T7	1		T8	17		T137	1
values[9]	148	1			T9	1		T144	32		T153	25
minimum	14665	1			T3	7		T6	26		T7	183

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	5		T120	1		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T93	1		T119	8		T127	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	12		T30	19		T123	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T173	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T140	3		T126	23		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T29	11		T93	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T122	1		T124	9		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T3	2		T119	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	8		T136	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	7		T117	14		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T93	1		T117	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	11		T11	1		T140	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	1		T2	2		T5	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	1		T161	10		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	2		T165	9		T161	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	11		T139	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T137	1		T140	11		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T7	1		T8	1		T138	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T9	1		T153	13		T92	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T144	17		T23	1		T298	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14413	1			T3	7		T6	14		T7	183
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T6	12		T29	12		T123	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	14		T120	4		T126	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T93	11		T206	6		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T208	14		T250	2		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T173	10		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T126	5		T174	11		T321	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	10		T93	14		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	8		T27	1		T256	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	1		T119	10		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	4		T209	12		T90	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T117	15		T119	7		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T93	2		T156	15		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	1		T213	5		T220	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T11	13		T143	32		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T130	9		T156	12		T152	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	1		T156	13		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	14		T175	11		T260	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T92	3		T214	14		T67	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T8	16		T138	2		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T153	12		T92	9		T22	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T144	15		T23	6		T248	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	13		T13	3		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T29	14		T211	10		T255	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T140	11		T153	13		T92	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T138	13		T128	11		T23	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T252	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	14		T9	5		T29	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	12		T29	12		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	12		T30	19		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T173	1		T139	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T123	20		T140	3		T124	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T29	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T122	1		T27	2		T256	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T3	2		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	1		T209	14		T90	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	7		T117	14		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	8		T117	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T119	4		T161	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T93	1		T161	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	11		T130	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T2	2		T5	15		T11	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	11		T139	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	1		T165	9		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T7	1		T8	1		T144	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T153	12		T92	12		T245	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T138	2		T128	10		T23	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T255	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	14		T29	13		T126	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	14		T93	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T120	4		T208	14		T232	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T173	10		T139	13		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T124	8		T126	5		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T29	10		T126	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T27	1		T256	3		T210	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T93	14		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T136	4		T209	12		T90	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T117	15		T141	3		T152	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T153	5		T84	5		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T119	7		T220	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T93	2		T156	15		T68	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T130	9		T152	1		T147	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	895	1			T11	13		T12	1		T143	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	14		T156	12		T175	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T129	7		T214	14		T22	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T8	16		T144	15		T206	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	15		T120	5		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T93	12		T119	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	1		T30	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T173	11		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T140	1		T126	6		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	11		T93	15		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T122	1		T124	9		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T3	2		T119	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T30	1		T136	5		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T117	16		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T93	3		T117	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T11	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T1	1		T2	2		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T130	10		T161	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T165	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	1		T139	15		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T137	1		T140	1		T92	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T7	1		T8	17		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T9	1		T153	13		T92	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T144	16		T23	7		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14474	1			T3	7		T6	1		T7	183
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T6	1		T29	15		T123	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	4		T125	7		T126	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T119	7		T127	12		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	11		T30	18		T123	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T126	14		T142	1		T172	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T140	2		T126	22		T261	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	10		T125	10		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T124	8		T27	1		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T119	7		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	7		T123	13		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	6		T117	13		T119	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T153	7		T246	11		T219	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	10		T140	8		T246	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T5	14		T11	10		T21	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T161	9		T156	13		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T165	8		T161	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	10		T175	10		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T140	10		T247	10		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T138	12		T127	9		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T153	12		T63	6		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T144	16		T298	12		T248	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T6	13		T29	11		T246	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T6	11		T29	11		T123	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T140	1		T153	13		T92	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T138	3		T128	11		T23	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T255	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	1		T9	15		T29	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T29	15		T93	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	1		T30	1		T120	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T173	11		T139	14		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T123	1		T140	1		T124	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	2		T29	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T122	1		T27	2		T256	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T3	2		T93	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	5		T209	13		T90	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T117	16		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	1		T117	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	2		T119	8		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T93	3		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	1		T130	10		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T2	2		T5	1		T11	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	1		T139	15		T156	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	1		T165	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T7	1		T8	17		T144	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T140	10		T153	12		T245	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T138	12		T128	10		T278	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T252	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	13		T9	4		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	11		T29	11		T119	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	11		T30	18		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T142	1		T172	7		T204	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T123	19		T140	2		T124	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	10		T125	10		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T27	1		T256	1		T210	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T119	7		T207	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T209	13		T90	17		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	6		T117	13		T141	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	7		T123	13		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T119	3		T161	9		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T161	7		T149	4		T76	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T10	10		T16	2		T246	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T5	14		T11	10		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T30	10		T156	13		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	8		T129	6		T247	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T144	16		T127	9		T157	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30