Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19792

1

T2

2

T3

7

T5

15

auto[ADC_CTRL_FILTER_COND_OUT]

3188

1

T1

2

T3

3

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17366

1

T1

2

T3

7

T6

7

auto[1]

5614

1

T2

2

T3

3

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	195	1			T8	17		T29	26		T93	3
values[0]	24	1			T210	9		T68	11		T298	4
values[1]	645	1			T6	14		T9	19		T12	3
values[2]	752	1			T11	4		T30	19		T93	12
values[3]	629	1			T10	12		T136	5		T139	14
values[4]	622	1			T1	1		T122	2		T139	15
values[5]	2891	1			T2	2		T5	15		T9	1
values[6]	676	1			T10	11		T93	15		T120	5
values[7]	589	1			T1	1		T29	21		T117	29
values[8]	567	1			T3	3		T6	7		T7	1
values[9]	962	1			T6	12		T29	25		T30	8
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	635	1			T6	14		T9	19		T12	3
values[1]	796	1			T10	12		T11	4		T30	19
values[2]	550	1			T139	14		T26	6		T206	11
values[3]	2818	1			T1	1		T2	2		T5	15
values[4]	694	1			T9	1		T11	24		T120	5
values[5]	630	1			T10	11		T93	15		T130	10
values[6]	603	1			T1	1		T29	21		T117	29
values[7]	665	1			T3	3		T6	7		T7	1
values[8]	887	1			T6	12		T8	17		T29	51
values[9]	59	1			T30	8		T214	8		T212	8
minimum	14643	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	8		T137	1		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	14		T9	5		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T11	1		T161	26		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	12		T11	1		T30	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T206	1		T84	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T139	1		T26	4		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T2	2		T5	15		T21	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T136	1		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	1		T120	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	11		T205	13		T123	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T93	1		T130	1		T141	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	11		T138	13		T208	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T156	1		T128	16		T90	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T29	11		T117	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	7		T7	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	2		T144	17		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	12		T29	24		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	1		T30	11		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T30	8		T214	3		T231	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T212	3		T297	3		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14394	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T119	8		T175	1		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T119	10		T209	12		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	14		T12	1		T90	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T244	14		T67	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	1		T93	11		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T206	10		T84	5		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T139	13		T26	2		T220	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T143	32		T159	9		T94	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	4		T126	11		T67	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	4		T139	14		T206	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	13		T92	9		T175	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T93	14		T130	9		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	2		T208	14		T290	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T156	15		T128	19		T90	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T29	10		T117	15		T152	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T63	4		T219	14		T260	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T144	15		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	27		T93	2		T119	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	16		T173	10		T156	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T214	5		T231	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T212	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	3		T25	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T68	10		T250	2		T265	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T29	12		T93	1		T214	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T8	1		T156	13		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T210	5		T298	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T68	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T119	8		T137	1		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	14		T9	5		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	1		T161	10		T140	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T30	19		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T206	1		T84	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	12		T136	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	2		T139	1		T126	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T126	15		T246	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T2	2		T5	15		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	11		T205	13		T123	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T93	1		T120	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	11		T138	13		T123	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	1		T128	16		T90	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	1		T29	11		T117	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	7		T7	1		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	2		T30	11		T144	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	12		T29	12		T30	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T173	1		T121	1		T156	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T29	14		T93	2		T214	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T8	16		T156	13		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T210	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T68	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T119	10		T209	12		T181	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	14		T12	1		T90	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T157	12		T244	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T93	11		T152	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T206	10		T84	5		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	4		T139	13		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	14		T126	5		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T126	11		T67	4		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T143	32		T159	9		T94	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	13		T92	9		T175	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T93	14		T120	4		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T138	2		T208	14		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T156	15		T128	19		T90	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T29	10		T117	15		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T63	4		T219	14		T260	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	1		T144	15		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T29	13		T119	7		T124	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T173	10		T156	12		T129	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T119	11		T137	1		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T9	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	2		T161	2		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T11	2		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T206	11		T84	6		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	14		T26	4		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T2	2		T5	1		T21	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T136	5		T126	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T120	5		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	14		T205	1		T123	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T93	15		T130	10		T141	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	1		T138	3		T208	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T156	16		T128	21		T90	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T29	11		T117	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T7	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	2		T144	16		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T29	29		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T8	17		T30	1		T173	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T30	1		T214	6		T231	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T212	6		T297	2		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T119	1		T175	1		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T119	7		T140	2		T125	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	13		T9	4		T12	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T161	24		T244	17		T223	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	11		T30	18		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	1		T149	4		T255	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T26	2		T246	7		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T5	14		T21	34		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	14		T254	1		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T161	7		T140	8		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	10		T205	12		T123	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T141	1		T142	1		T172	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	10		T138	12		T208	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T128	14		T90	17		T219	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	10		T117	13		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	6		T125	7		T264	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T144	16		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T29	22		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T30	10		T156	25		T129	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T30	7		T214	2		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T212	2		T297	1		T249	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T181	5		T150	10		T324	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T119	7		T250	15		T265	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T29	15		T93	3		T214	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	17		T156	14		T152	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T210	5		T298	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T68	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T119	11		T137	1		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T9	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	2		T161	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	2		T30	1		T93	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T206	11		T84	6		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	1		T136	5		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	2		T139	15		T126	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	1		T126	12		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	2		T5	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	14		T205	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T93	15		T120	5		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T138	3		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T156	16		T128	21		T90	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	1		T29	11		T117	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T7	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	2		T30	1		T144	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	1		T29	14		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T173	11		T121	1		T156	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T29	11		T214	2		T23	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T156	12		T212	2		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T210	4		T298	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T119	7		T161	15		T125	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	13		T9	4		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T161	9		T140	2		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	18		T207	9		T304	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T223	7		T149	4		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	11		T211	10		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T126	22		T127	9		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T126	14		T246	7		T254	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	14		T21	34		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	10		T205	12		T123	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T161	7		T141	1		T172	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	10		T138	12		T123	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	14		T90	17		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	10		T117	13		T252	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	6		T125	7		T264	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	1		T30	10		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	11		T29	11		T30	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T156	13		T129	6		T179	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30