Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19618

1

T1

1

T2

2

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3362

1

T1

1

T3

3

T8

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17242

1

T1

1

T3

7

T6

7

auto[1]

5738

1

T1

1

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	294	1			T6	12		T126	28		T206	7
values[0]	12	1			T140	3		T207	1		T67	3
values[1]	456	1			T30	11		T136	5		T137	1
values[2]	2897	1			T2	2		T5	15		T10	11
values[3]	617	1			T3	3		T10	12		T29	46
values[4]	582	1			T6	7		T9	19		T11	2
values[5]	707	1			T8	17		T30	8		T165	9
values[6]	614	1			T119	18		T121	1		T13	1
values[7]	706	1			T7	1		T93	15		T119	19
values[8]	725	1			T117	29		T146	1		T209	26
values[9]	942	1			T1	2		T6	14		T9	1
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	558	1			T11	24		T30	11		T173	11
values[1]	2847	1			T2	2		T3	3		T5	15
values[2]	581	1			T6	7		T10	12		T12	3
values[3]	686	1			T9	19		T11	2		T29	25
values[4]	663	1			T8	17		T165	9		T119	18
values[5]	570	1			T119	11		T13	1		T161	10
values[6]	764	1			T7	1		T93	15		T117	29
values[7]	671	1			T30	19		T146	1		T209	26
values[8]	947	1			T1	2		T6	26		T9	1
values[9]	166	1			T152	21		T215	32		T301	4
minimum	14527	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	11		T173	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	11		T137	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	2		T5	15		T21	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	2		T10	11		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	7		T10	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	2		T138	13		T207	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	5		T29	12		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	1		T30	8		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T165	9		T137	1		T92	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	1		T119	8		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	4		T211	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T161	10		T140	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T119	8		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T93	1		T117	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T30	19		T209	14		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T146	1		T128	5		T181	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T1	1		T6	26		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	1		T93	1		T161	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T152	13		T155	3		T325	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T215	18		T301	4		T172	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14344	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T63	3		T302	1		T326	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	13		T173	10		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T139	14		T141	3		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	871	1			T29	10		T143	32		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T29	14		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	9		T208	14		T126	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	1		T138	2		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	14		T29	13		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T156	13		T22	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T92	9		T241	9		T256	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	16		T119	10		T128	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T119	7		T211	10		T250	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T152	1		T219	14		T305	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T174	11		T175	11		T147	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T93	14		T117	15		T144	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T209	12		T92	9		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T128	9		T181	5		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	1		T93	2		T126	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T93	11		T23	6		T67	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T152	8		T327	15		T303	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T215	14		T172	11		T248	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	4		T13	3		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T63	5		T302	15		T326	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	12		T126	23		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T328	1		T280	4		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T207	1		T67	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T140	3		T326	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T136	1		T84	1		T63	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	11		T137	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	2		T5	15		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	11		T29	12		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	12		T29	23		T125	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	2		T132	1		T138	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	7		T9	5		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	1		T12	2		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T165	9		T137	1		T153	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	1		T30	8		T128	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T211	11		T127	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T119	8		T121	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T119	12		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T93	1		T122	1		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T209	14		T92	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T117	14		T146	1		T179	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	1		T6	14		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	1		T93	1		T161	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T126	5		T206	6		T152	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T329	17		T248	20		T330	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T67	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T136	4		T84	5		T63	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T141	3		T157	12		T63	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T11	13		T143	32		T159	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	14		T139	27		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T29	23		T181	5		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T138	2		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	14		T130	9		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	1		T12	1		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T153	5		T92	9		T256	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	16		T128	10		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T211	10		T241	9		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T119	10		T152	1		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T119	7		T174	11		T175	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T93	14		T144	15		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T209	12		T92	9		T80	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T117	15		T181	5		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T93	2		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T93	11		T128	9		T23	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	14		T173	11		T152	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	1		T137	1		T139	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T2	2		T5	1		T21	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	2		T10	1		T29	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	1		T10	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	2		T138	3		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	15		T29	14		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	2		T30	1		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T165	1		T137	1		T92	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	17		T119	11		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T119	8		T211	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T161	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T119	1		T174	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T93	15		T117	16		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	1		T209	13		T92	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T146	1		T128	10		T181	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T1	1		T6	2		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T93	12		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T152	9		T155	1		T325	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T215	15		T301	4		T172	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14448	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T63	6		T302	16		T326	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	10		T63	2		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	10		T140	2		T141	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	14		T21	34		T29	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T10	10		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	6		T10	11		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T138	12		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	4		T29	11		T205	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	7		T156	12		T23	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T165	8		T241	13		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T119	7		T128	10		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T119	3		T211	10		T252	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	9		T140	10		T252	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T119	7		T175	10		T214	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	13		T144	16		T123	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	18		T209	13		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T128	4		T181	5		T244	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	24		T126	22		T210	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T161	22		T140	8		T304	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T152	12		T155	2		T325	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T215	17		T172	12		T248	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T274	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T63	2		T331	12		T332	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	1		T126	6		T206	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T328	1		T280	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T207	1		T67	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T140	1		T326	2		T203	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	5		T84	6		T63	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T30	1		T137	1		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T2	2		T5	1		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T29	15		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	1		T29	25		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	2		T132	1		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T9	15		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	2		T12	2		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T165	1		T137	1		T153	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	17		T30	1		T128	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T211	11		T127	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T119	11		T121	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T119	9		T174	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T93	15		T122	1		T144	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T209	13		T92	10		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T117	16		T146	1		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T6	1		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	1		T93	12		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	11		T126	22		T152	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T280	3		T329	13		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T140	2		T203	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T63	2		T149	2		T265	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T30	10		T141	1		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T5	14		T11	10		T21	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	10		T29	11		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	11		T29	21		T125	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T138	12		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	6		T9	4		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	1		T156	12		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T165	8		T153	7		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	7		T128	10		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T211	10		T241	13		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T119	7		T161	9		T252	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T119	10		T175	10		T214	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T144	16		T123	23		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T209	13		T15	1		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	13		T179	2		T181	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	13		T30	18		T210	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T161	22		T140	8		T128	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30