Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22980

1

T1

2

T2

2

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17282

1

T1

1

T3

10

T6

12

auto[ADC_CTRL_FILTER_COND_OUT]

5698

1

T1

1

T2

2

T5

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17024

1

T1

1

T3

10

T6

19

auto[1]

5956

1

T1

1

T2

2

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19269

1

T1

2

T2

2

T3

9

auto[1]

3711

1

T3

1

T8

16

T9

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	286	1			T10	12		T29	26		T25	3
values[0]	42	1			T214	8		T272	15		T332	19
values[1]	659	1			T9	19		T29	46		T117	29
values[2]	582	1			T1	1		T11	2		T30	8
values[3]	629	1			T8	17		T93	15		T140	9
values[4]	510	1			T1	1		T9	1		T10	11
values[5]	748	1			T6	7		T7	1		T30	19
values[6]	765	1			T3	3		T12	3		T173	11
values[7]	758	1			T119	18		T122	1		T233	1
values[8]	745	1			T6	14		T165	9		T13	1
values[9]	2828	1			T2	2		T5	15		T6	12
minimum	14428	1			T3	7		T7	183		T9	307

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	604	1			T9	19		T11	2		T29	21
values[1]	2783	1			T1	1		T2	2		T5	15
values[2]	695	1			T1	1		T10	11		T11	24
values[3]	546	1			T6	7		T9	1		T30	19
values[4]	641	1			T7	1		T119	8		T136	5
values[5]	762	1			T3	3		T12	3		T173	11
values[6]	794	1			T165	9		T119	18		T120	5
values[7]	701	1			T6	14		T30	11		T13	1
values[8]	637	1			T6	12		T10	12		T11	2
values[9]	167	1			T29	26		T231	2		T232	29
minimum	14650	1			T3	7		T7	183		T9	307

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

3962

1

T3

1

T5

14

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	5		T11	1		T161	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	11		T117	14		T208	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T8	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1599	1			T2	2		T5	15		T21	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	11		T137	1		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T1	1		T10	11		T93	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	1		T93	1		T26	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	7		T30	19		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	1		T119	8		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T122	1		T123	20		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	2		T173	1		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	2		T207	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T119	8		T120	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T165	9		T233	1		T209	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	11		T13	1		T126	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	14		T139	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	12		T11	1		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	12		T117	1		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T231	1		T232	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T29	12		T232	12		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14383	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T141	2		T84	1		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	14		T11	1		T156	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	10		T117	15		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	16		T156	12		T152	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	919	1			T143	32		T159	9		T94	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	13		T211	10		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T93	13		T181	5		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T93	14		T26	2		T213	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T23	6		T236	5		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	4		T130	9		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T90	18		T92	3		T216	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T173	10		T119	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T156	15		T67	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T119	10		T120	4		T126	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T209	12		T157	12		T128	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T126	4		T231	13		T170	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T139	14		T128	9		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T144	15		T206	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T124	8		T92	9		T181	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T231	1		T232	1		T238	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T29	14		T232	15		T239	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	13		T138	2		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T141	3		T84	5		T174	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T144	17		T206	1		T210	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T10	12		T29	12		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T214	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T272	13		T332	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	5		T29	12		T138	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	11		T117	14		T208	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T11	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T30	8		T241	14		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T8	1		T140	9		T211	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T93	2		T127	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T11	11		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	1		T10	11		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	1		T136	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	7		T30	19		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	2		T173	1		T119	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	2		T207	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T119	8		T122	1		T126	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T233	1		T209	14		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T126	23		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	14		T165	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	12		T11	1		T30	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1609	1			T2	2		T5	15		T21	37
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14327	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T144	15		T206	10		T210	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T29	14		T92	9		T232	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T214	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T272	2		T332	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	14		T29	13		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	10		T117	15		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	1		T152	1		T92	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T241	9		T148	2		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	16		T211	10		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	13		T27	1		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	13		T93	14		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T181	5		T23	6		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	4		T139	13		T26	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T90	18		T216	12		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T173	10		T119	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T156	15		T92	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	10		T126	5		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T209	12		T22	7		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T126	15		T231	13		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	14		T157	12		T128	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T147	3		T220	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	931	1			T143	32		T159	9		T94	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T25	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	15		T11	2		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T29	11		T117	16		T208	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T8	17		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1248	1			T2	2		T5	1		T21	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	14		T137	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T10	1		T93	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	1		T93	15		T26	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	1		T30	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	1		T119	1		T136	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T122	1		T123	1		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	2		T173	11		T119	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	2		T207	1		T156	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T119	11		T120	5		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T165	1		T233	1		T209	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	1		T13	1		T126	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	1		T139	15		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T11	2		T144	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T117	1		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T231	2		T232	2		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T29	15		T232	16		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14500	1			T3	7		T7	183		T9	307
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T141	4		T84	6		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T9	4		T161	15		T156	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	10		T117	13		T208	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T123	17		T125	7		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T5	14		T21	34		T30	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	10		T140	8		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	10		T181	5		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	2		T63	8		T245	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	6		T30	18		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T119	7		T127	9		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T123	19		T90	17		T219	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T119	3		T161	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T179	2		T246	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T119	7		T126	14		T129	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T165	8		T209	13		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T30	10		T126	7		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	13		T125	10		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	11		T144	16		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	11		T205	12		T124	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T155	5		T333	13		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T29	11		T232	11		T239	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T29	11		T138	12		T140	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T141	1		T174	11		T272	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T144	16		T206	11		T210	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	1		T29	15		T25	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T214	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T272	3		T332	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	15		T29	14		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T29	11		T117	16		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	1		T11	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	1		T241	10		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	17		T140	1		T211	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T93	15		T127	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T11	14		T93	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	1		T10	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	1		T136	5		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T30	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	2		T173	11		T119	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	2		T207	1		T156	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T119	11		T122	1		T126	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T233	1		T209	13		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T126	17		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T165	1		T139	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T11	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T2	2		T5	1		T21	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T3	7		T7	183		T9	307
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T144	16		T210	4		T265	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T10	11		T29	11		T205	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T272	12		T332	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	4		T29	11		T138	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T29	10		T117	13		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T123	17		T250	15		T255	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	7		T241	13		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T140	8		T211	10		T125	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	1		T16	2		T246	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	10		T153	12		T63	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	10		T181	5		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T127	9		T26	2		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	6		T30	18		T123	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T119	10		T161	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T149	15		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T119	7		T126	22		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T209	13		T179	2		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T126	21		T231	13		T163	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	13		T165	8		T125	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	11		T30	10		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1268	1			T5	14		T21	34		T124	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19018

1

T1

2

T2

2

T3

9

auto[1]

auto[0]

3962

1

T3

1

T5

14

T6

30